JP4002422B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element including a semiconductor layer containing Al in an active layer waveguide and a method for manufacturing the same.
[0002]
[Prior art]
Waveguide by wet etching shown in FIG. 14 in 1980 Journal of Applied Physics, Vol. 51, pages 4539-4540 (JOURNAL OF APPLIED PHYSICS, P.4539-4540, VOL.51, 1980) 1 shows a structure of a semiconductor laser (BH-LD: Buried Heterostructure-Laser Diode) having a buried heterostructure formed with GaN.
[0003]
A waveguide including an InGaAsP active layer 4c, a p-type InP cladding layer 6b, and a p-type InGaAsP contact layer 10b is formed on an n-type InP (100) substrate 1a, and a p-type InP current blocking layer 8a and an n-type InP current blocking layer are formed. 8b, embedded with an n-type InGaAsP layer 8c.
[0004]
FIG. 15 shows a production process drawn based on the text of the document.
[0005]
First, an InGaAsP active layer 4c, a p-type InP clad layer 6b, and an InGaAsP cap layer 10c are grown on a Sn-doped n-type InP substrate 1a by a liquid phase growth method (FIG. 15A). The initial growth temperature is 630 ° C., and the cooling rate is 0.5 ° C./min. The composition of the active layer 4c is In_0.73Ga_0.27As_0.63P_0.37The oscillation wavelength at room temperature is 1.3 μm.
[0006]
Next, a stripe-shaped silicon oxide mask 13a having a width of 6 to 7 μm is formed in the [110] direction (FIG. 15B). Then, etching is performed with a Br (bromine) -methanol solution until the n-type InP substrate 1a is reached, thereby forming a waveguide (FIG. 15C). The Br-methanol solution has a reverse mesa shape because the etching rate of the (111) InP surface is slow. At this time, the etching is adjusted so that the InGaAsP active layer 4c has a width of 1 to 2 μm. Thereafter, the p-type InP current blocking layer 8a, the n-type InP current blocking layer 8b, and the n-type InGaAsP layer 8c are embedded (FIG. 15D). After removing the silicon oxide mask 13a, a Zn diffusion region 200 is selectively formed only in the mesa stripe portion until the p-type InP cladding layer 6b is reached (FIG. 14), and a p-type InGaAsP contact layer 10b is formed. The structure shown is obtained.
[0007]
Since the BH-LD can efficiently inject current into the active layer with a narrow active layer width and a current blocking structure with little leakage current, laser oscillation with low threshold current and high efficiency is possible. However, since the active layer width affects the threshold current and the beam pattern, it must be precisely controlled.
[0008]
However, since the conventional BH-LD shown in FIG. 14 uses an etchant such as Br-methanol for mesa etching and the mesa width is controlled by the etching time, the etching rate due to a slight concentration difference of the etchant. It is difficult to obtain sufficient controllability due to the difference between the two and side etching. In addition, in the process using a 2 to 3 inch substrate, in-plane variation becomes large. As a result, there is a problem that the laser characteristics differ from wafer to wafer and within the wafer surface, resulting in a decrease in yield. Also in the BH-LD shown in the above document (FIG. 14), the beam emission angle is 35 degrees × 35 degrees when the active layer width is 1 μm, and the active layer width is 15 degrees × 35 degrees when the active layer width is 2 μm. It is described that the beam radiation angle changes greatly.
[0009]
On the other hand, a semiconductor laser (ASM-LD: All Selective MOVPE grown Laser Diode) by full selective MOVPE growth has a feature that a BH structure can be produced without an etching process.
[0010]
FIG. 16 shows, in March 1999, IEE Journal of Quantum Electronics, Vol. 35, No. 3, pages 368-376 (IEEE JOURNAL OF QUANTUM ELECTRONICS, P.368-376, VOL. 35, No. 33, MARCH, 1999), shows a structural diagram of ASM-LD.
[0011]
An n-type InP clad layer 2a (thickness d = 100 to 200 nm) and an n-side InGaAsP light guide layer 3b (λ = 1. 13 μm, 60 nm), 0.7% compressive strain InGaAsP well (d = 6 nm), InGaAsP barrier (λ = 1.13 μm, d = 8 nm), strained multiple quantum well active layer 4b, p-side InGaAsP light A guide layer 5b (λ = 1.13 μm, 60 nm), a p-type InP first cladding layer 206a (d = 100 to 200 nm) are formed, and the mesa stripe has a p-type InP current blocking layer 8a (d = 600 nm), It is embedded with an n-type InP current blocking layer 8b (d = 600 nm). A p-type InP second cladding layer 9a (d = 1600 nm) and a p-type InGaAs contact layer 10a (300 nm) are formed thereon. A p-side electrode 11 and an n-side electrode 12 are formed.
[0012]
FIG. 17 shows a manufacturing process.
[0013]
First, two stripe-shaped silicon oxide masks 13a (mask width 5 μm) are formed along the [110] direction on an n-type InP substrate 1a having a (001) plane as a growth surface (FIG. 17A). The n-type InP clad layer 2a, the n-side light guide layer 3b, the strained multiple quantum well active layer 4b, and the p-side by selective MOVPE (Metal Organic Vapor Phase Epitaxy) growth in the region sandwiched between the masks (opening width 1.5 μm) A forward mesa stripe-shaped active layer waveguide composed of the light guide layer 5b and the p-type InP first cladding layer 206a is produced (FIG. 17B). Next, a silicon oxide mask 13a is formed only on the top of the mesa stripe by a self-alignment process (FIG. 17C), and using that as a mask, a p-type InP current blocking layer 8a, an n-type InP current blocking layer 8b, and a p-type InP. The current blocking layer 8a is selectively grown in this order (FIG. 17D). After removing the silicon oxide mask 13a, the p-type InP second cladding layer 9a and the p-type InGaAs contact layer 10a can be crystal-grown to produce a laser structure (FIG. 17E).
[0014]
FIG. 18 shows the self-alignment process. First, after the active layer waveguide is selectively grown, the thickness (dt) of the silicon oxide film 14 on the mesa stripe top is changed to the thickness (ds) on the side surface of the mesa stripe by thermal chemical vapor deposition (thermal CVD). ) To be thicker (dt> ds) (FIG. 18A). Next, the silicon oxide film on the side surface of the mesa stripe is etched until ds = 0 (FIG. 18B). Next, a resist 15 is formed by a general photolithography technique so as to cover the active layer waveguide, and only the silicon oxide film on the mesa bottom is removed by side etching (FIG. 18C). Then, the self-alignment process for removing the resist 15 and forming the silicon oxide mask 13a only on the mesa stripe top is completed (FIG. 18D).
[0015]
In the ASM-LD, the active layer waveguide produced by selective growth has a very smooth forward mesa shape surrounded by the (001) plane and the (111) B plane indicating the side surface. (Mesa stripe width) is determined by the opening width of the selective growth region and the mask width. Therefore, if the processing (patterning) of the dielectric mask can be controlled within the wafer surface or for each wafer, the active layer width is automatically determined. As a result, a semiconductor element having excellent in-plane uniformity and reproducibility can be manufactured, and the yield can be improved. The document also describes that the semiconductor laser shown in FIG. 16 exhibits excellent laser characteristics.
[0016]
[Problems to be solved by the invention]
A semiconductor laser using InAl (Ga) As as an active layer has a higher band offset on the electron side than an InGaAsP system, so that carrier confinement is strong, and laser characteristics such as low threshold current and high temperature characteristics are improved. I can expect.
[0017]
However, since the active layer contains aluminum (Al) that easily oxidizes, there is a concern that the BH structure that requires a process in which the side surface of the active layer is exposed to the atmosphere may deteriorate laser characteristics and reliability due to oxidation. In the conventional BH-LD shown in FIG. 14, the side surface of the active layer is always exposed to the atmosphere during the mesa etching shown in FIG. On the other hand, also in the ASM-LD shown in FIG. 16, the side surface of the active layer is exposed to the atmosphere in the step of FIG. 17C, and oxidation is inevitable.
[0018]
An object of the present invention is to oxidize an active layer in a semiconductor device using a semiconductor layer containing Al as an active layer, by covering the side of the active layer with a semiconductor layer not containing Al, thereby exposing the active layer to the atmosphere. Is to provide a semiconductor device with high reliability and yield and a method for manufacturing the same.
[0019]
[Means for Solving the Problems]
  In order to achieve the above object, a semiconductor device of the present invention comprises a first conductivity type cladding layer, an active layer containing Al, and a second conductivity type first cladding layer laminated in a predetermined region on an InP substrate (111 ) A stripe having a B surface; a current blocking layer in which the stripe is embedded; a second conductivity type second cladding layer formed on the stripe and the current block layer; and the second conductivity type second cladding. A semiconductor device comprising a second conductivity type contact layer formed on a layer, and having an InP protective layer between a stripe having a (111) B surface including the active layer and the current blocking layer, A semiconductor element in which the plane orientation of the substrate is tilted from (001) to the [110] direction or the [-1-10] direction.
[0020]
In the present invention, on an InP substrate inclined from (001) to the [110] direction or the [-1-10] direction.A first conductivity type cladding layer, an active layer containing Al, and a second conductivity type first cladding layer laminated in a predetermined region of(111) with B-planeTo stripeSince the InP protective layer is formed, the coverage of the protective layer formation on the stripe side surface is improved. Therefore, the thickness of the InP protective layer formed on the side surface of the stripe is increased, and the oxidation suppressing effect of the active layer is improved. As a result, deterioration of the laser characteristics due to oxidation of the active layer can be prevented, and a semiconductor element with high reliability and high yield can be obtained.
[0021]
The material of the second conductivity type first cladding layer and the protective layer is InP.
[0022]
For this reason,Simultaneously with the second conductivity type first cladding layerInP protective layerCan formInP substrateThe height of the stripe from the surface can be reduced.
[0025]
Further, the conditions for forming the protective layer not containing Al are: (x, y) = (Tg, where the growth temperature of the protective layer is Tg (° C.) and the growth rate of the protective layer is Rg (μm / h). (Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3) from the relationship between the growth temperature and the growth rate indicated on the xy plane by Rg). ), (560, 3) may be set to a growth temperature and a growth rate determined by an arbitrary point in a region surrounded by the five points.
[0026]
The conditions for forming the protective layer not containing Al are expressed in the xy plane by (x, y) = (Tg, Rg), where the growth temperature is Tg (° C.) and the growth rate is Rg (μm / h). From the relationship between the growth temperature and the growth rate, (Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3), (560, 3) Since it is determined at an arbitrary point in the region surrounded by the five points, the growth rate and growth temperature for forming the protective layer can be determined accurately, and the protective layer can be formed stably. Therefore, the oxidation suppression effect of the active layer can be obtained with certainty.
[0029]
Further, the stripe orientation indicating the longitudinal direction of the stripe-shaped region of the stripe composed of the first conductivity type cladding layer, the active layer containing Al and the second conductivity type first cladding layer laminated in the stripe region on the semiconductor substrate, It may be inclined from the [110] direction to the [−110] direction or the [1-10] direction within the surface of the semiconductor substrate.
[0030]
By tilting the stripe orientation indicating the longitudinal direction of the stripe from the [110] direction to the [−110] direction or the [1-10] direction within the semiconductor substrate surface, the coverage of forming the protective layer on the side surface of the stripe is further improved. . Therefore, the thickness of the protective layer formed on the side surface of the stripe is increased, and the effect of suppressing the oxidation of the active layer is improved.
[0031]
Further, the stripe orientation indicating the longitudinal direction of the stripe-shaped region is inclined from the [110] direction to the [−110] direction or the [1-10] direction within the semiconductor substrate surface, and the inclination is 0.01 degrees or more 3 Or less.
[0032]
The stripe orientation indicating the longitudinal direction of the stripe-shaped region is inclined from the [110] direction to the [−110] direction or the [1-10] direction within the surface of the semiconductor substrate, and the inclination is 0.01 degrees or more and 3 degrees or less. If so, not only the coverage of forming the protective layer on the side surface of the stripe is improved, but also the good shape of the stripe can be maintained.
[0034]
  On the other hand, in the method for manufacturing a semiconductor element of the present invention for achieving the above object, the plane orientation is inclined from the (001) plane to the [110] direction or the [-1-10] direction.On InP substrateAnd a first conductivity type cladding layer, an active layer containing Al, and a second conductivity type first cladding layer.(111) with B-planeAfter forming the stripe and forming the second conductivity type first cladding layer, without exposing to oxygen,The exposed surface of the stripe including the active layer is an InP protective layer.A step of forming a cover, a step of forming a dielectric mask on the stripe,
  SaidInP protective layerForming a current blocking layer on the stripe and the exposed surface of the semiconductor substrate; removing the dielectric mask; andInP protective layerOr a step of forming a second conductivity type second cladding layer on the exposed surface of the stripe and the current blocking layer; and a step of forming a second conductivity type contact layer on the second conductivity type second cladding layer; A method for manufacturing a semiconductor element comprising:
It consists of.
[0035]
On InP substrateAnd a first conductivity type cladding layer, an active layer containing Al, and a second conductivity type first cladding layer.(111) with B-planeAfter forming the stripe, without exposure to oxygen,InP protective layerSince the active layer is formed so as to cover the exposed surface of the active layer, the active layer is not exposed to oxygen in the atmosphere in the steps after the stripe formation. Therefore, oxidation of the active layer is suppressed, and a semiconductor element with high reliability and high yield can be manufactured.On this occasion,By tilting the plane orientation of the semiconductor substrate from the (001) plane to the [110] direction or the [-1-10] direction, the coverage of forming the protective layer on the stripe side surface is improved. Therefore, the thickness of the protective layer formed on the side surface of the stripe is increased, and the effect of suppressing the oxidation of the active layer is improved.
[0036]
Alternatively, the plane orientation is tilted from the (001) plane in the [110] direction or the [-1-10] direction.InP substrateabove,The first conductivity type cladding layer and the active layer containing Al whose mesa side surface is a (111) B surfaceAnd after the active layer formation, without exposure to oxygen,Second conductivity type InP first cladding layerCovering the upper part of the active layer and the exposed surface of the active layer, the first conductivity type cladding layer, the active layer and theSecond conductivity type InP first cladding layerForming a stripe comprising: a step of forming a dielectric mask on the stripe; a step of forming a current blocking layer on the stripe and the exposed surface of the semiconductor substrate; and a step of removing the dielectric mask. Forming a second conductivity type second cladding layer on the exposed surface of the stripe and the current blocking layer; and forming a second conductivity type contact layer on the second conductivity type second cladding layer; Consists of.
[0037]
  On InP substrateIn addition,The first conductivity type cladding layer and the active layer containing Al whose mesa side surface is a (111) B surfaceWithout exposure to oxygen after formingSecond conductivity type InP first cladding layerCovering the upper part of the active layer and the exposed surface of the active layer, the first conductivity type cladding layer, the active layer andSecond conductivity type InP first cladding layerIn the process after the stripe formation, the second conductivity type is formed.InPThe first cladding layer prevents oxidation of the active layer. Second conductivity typeInPSince the first cladding layer also has a function of a protective layer that prevents oxidation of the active layer, the second conductivity typeInPA step for forming a protective layer separately from the first cladding layer is not necessary, and the manufacturing period of the semiconductor element can be shortened. Also,InP substrateIs tilted from the (001) plane in the [110] direction or the [-1-10] direction,(111) B-side mesaThe coverage of forming the protective layer on the side surface is improved. Therefore, the thickness of the protective layer formed on the side surface of the stripe is increased, and the effect of suppressing the oxidation of the active layer is improved.
[0038]
Further, the conditions for forming the protective layer not containing Al are: (x, y) = (Tg, where the growth temperature of the protective layer is Tg (° C.) and the growth rate of the protective layer is Rg (μm / h). (Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3) from the relationship between the growth temperature and the growth rate indicated on the xy plane by Rg). ), (560, 3) may be set to a growth temperature and a growth rate determined by an arbitrary point in a region surrounded by the five points.
[0039]
The conditions for forming the second conductivity type first cladding layer not containing Al are (x, y) = (Tg, H) where the growth temperature is Tg (° C.) and the growth rate is Rg (μm / h). (Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3) from the relationship between the growth temperature and the growth rate indicated on the xy plane by Rg). ), (560, 3) may be set to a growth temperature and a growth rate determined by an arbitrary point in a region surrounded by the five points.
[0042]
When a stripe is formed in the stripe region on the semiconductor substrate, the stripe orientation indicating the longitudinal direction of the stripe region is changed from the [110] direction to the [−110] direction or [1-10] in the semiconductor substrate surface. It may be tilted in the direction.
[0043]
Further, the stripe orientation indicating the longitudinal direction of the stripe-shaped region is inclined from the [110] direction to the [−110] direction or the [1-10] direction within the semiconductor substrate surface, and the inclination is 0.01 degrees or more 3 Or less.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor element of the present invention and a manufacturing method thereof will be described with reference to the drawings.
[0046]
FIG. 1 shows a basic structure of a semiconductor element of the present invention. An active layer waveguide is formed on the semiconductor substrate 1, which includes a mesa stripe-shaped first conductivity type cladding layer 2, an active layer 4 containing aluminum (Al), and a second conductivity type first cladding layer 6. The waveguide is covered with a semiconductor layer (protective layer 7) that does not contain Al. The waveguide including the protective layer 7 is buried with a current blocking layer 8, and a second conductivity type second cladding layer 9 and a second conductivity type contact layer 10 are further laminated.
[0047]
FIG. 2 shows a manufacturing process. Two stripe-shaped dielectric masks 13 are formed on the semiconductor substrate 1 having a plane orientation (001) plane as a growth plane (FIG. 2A), and a first MOVPE growth is performed in a region sandwiched between the masks by selective MOVPE growth. A forward mesa-shaped active layer waveguide composed of the conductive cladding layer 2, the active layer 4 containing Al, and the second conductive first cladding layer 6 is produced (FIG. 2B). Further, the protective layer 7 is continuously formed without being exposed to oxygen without being taken out of the crystal growth furnace (FIG. 2C).
[0048]
Next, a dielectric mask 213 is formed only on the mesa top of the active layer waveguide by a self-alignment process (FIG. 2D), and the current blocking layer 8 is formed by selective growth using the dielectric mask 213 as a mask (FIG. 2E). . After removing the dielectric mask 213, the second conductivity type second cladding layer 9 and the second conductivity type contact layer 10 are formed, and the structure of FIG. 1 can be manufactured.
[0049]
Since the active layer waveguide is covered with the protective layer 7, even if the wafer is exposed to the atmosphere in the subsequent process, oxidation by oxygen in the atmosphere on the side surface of the active layer containing Al is suppressed, and the device characteristics deteriorate. And deterioration of reliability can be prevented. Oxidation is suppressed by the protective layer 7. When the protective layer 7 disappears in the process of completing the semiconductor element, the side surface of the active layer containing Al is oxidized. In order to suppress this, it is necessary to increase the thickness of the protective layer 7. In addition, it is necessary to configure the process so that it does not disappear intentionally.
[0050]
In the ASM-LD shown in the conventional example, since the active layer does not contain Al, there is no concept of a protective layer. Further, even if a side protective layer is formed by chance, it is finally lost by the process of embedding in the current blocking layer.
[0051]
The present invention provides a structure and manufacturing method of a semiconductor device having an Al-based active layer waveguide that can bring out an oxidation suppression effect by leaving this protective layer until the final step of the process, and can withstand practical use. is there.
[0052]
Below, the manufacturing direction for improving the persistence of a protective layer is described. The protective layer 7 includes: (1) lowering the growth temperature, (2) increasing the supply amount of Group III (In, Ga, etc.) raw materials and increasing the growth rate, and (3) two layers formed on the semiconductor substrate. By intentionally inclining the stripe direction of the stripe-shaped opening region formed by being sandwiched between the stripe-shaped dielectric masks, the growth rate on the mesa side surface can be increased compared to the growth rate of the mesa top. The reason is that the side surface of the active layer waveguide is the (111) B plane, and the group III atoms (In, Ga, etc.) on the surface are composed of the underlying group V atoms (As, P, etc.) and one bond. Only combined. Therefore, when the growth temperature is high, bonds are broken and desorption is likely to occur, and as a result, growth is suppressed. Hereinafter, the side surface of the active layer waveguide is referred to as a (111) B surface.
[0053]
Conversely, if the growth temperature is low, desorption is suppressed and growth on the (111) B plane can be promoted. Further, since the adsorption probability of group III atoms is proportional to the concentration of group III atoms, the growth rate on the (111) B plane increases as the growth rate on the (001) plane increases. Therefore, under growth conditions where the growth rate is somewhat high, it is easy to form a protective layer on the side surface of the active layer waveguide that is the (111) B plane. In addition, when the stripe orientation of the stripe-shaped opening region is tilted, the step density increases on the (111) B surface, which is the side surface of the active layer waveguide formed in the opening region, and the step flow growth is promoted compared to the case where the stripe orientation is not tilted. The As a result, the growth of the protective layer 7 on the (111) B surface is promoted and the coverage and flatness are also improved.
[0054]
When the active layer containing Al is used, if the oxidation of the side surface of the mesa stripe cannot be suppressed, a non-radiative recombination center is generated, resulting in deterioration of laser characteristics and reliability. Accordingly, a semiconductor laser that uses an Al-containing semiconductor layer as an active layer waveguide, for example, a semiconductor device having an ASM-LD structure, can realize a semiconductor laser that can withstand practical use for the first time by adopting the structure of the present invention. Can do.
[0055]
【Example】
(First embodiment)
FIG. 3 is a structural diagram of a 1.3 μm band ASM-LD using a semiconductor layer containing Al as an active layer in the first embodiment of the present invention.
[0056]
An n-type InP substrate 1a having a plane orientation (001) plane as a growth plane (carrier concentration n = 2 × 10¹⁸cm^-3) N-type InP cladding layer 2a having a mesa stripe shape (thickness d = 200 nm, n = 1 × 10¹⁸cm^-3), N-side InAlGaAs light guide layer 3a (d = 50 nm, non-doped), InAlGaAs well (d = 6 nm, 1.5% compressive strain, 7 well), InAlGaAs barrier (d = 10 nm, 0.9% tensile strain) The strained multiple quantum well active layer 4a, the p-side InAlGaAs light guide layer 5a (d = 50 nm, non-doped), and the p-type InP first cladding layer 56a (d = 50 nm, p = 5 × 10)¹⁷cm^-3), And the side surface of the active layer waveguide is covered with a p-type InP protective layer 7a. The thickness of the p-type InP protective layer 7a on the (001) plane is 200 nm, and the carrier concentration is p = 5 × 10.¹⁷cm^-3It is. The thickness of the p-type InP protective layer 7a on the (111) B surface on the side surface of the mesa stripe is 30 nm.
[0057]
The active layer waveguide is a p-type InP current blocking layer 8a (d = 700 nm, p = 7 × 10¹⁷cm^-3), N-type InP current blocking layer 8b (d = 600 nm, n = 1 × 10)¹⁸cm^-3P-type InP second cladding layer 9a (d = 1500 nm, p = 1 × 10)¹⁸cm^-3), P-type InGaAs contact layer 10a (300 nm, p = 1 × 10¹⁹cm^-3) Are stacked. Although not shown in FIG. 3, the p-side electrode 11 and the n-side electrode 12 shown in FIG. 16 are formed in the same manner as in the prior art, and detailed description thereof is omitted.
[0058]
Next, a manufacturing method will be described. FIG. 4 is a manufacturing process diagram of an ASM-LD which is the first embodiment of the present invention. Crystal growth uses the MOVPE method, and the raw materials are trimethylaluminum (TMAl), triethylgallium (TEGa), trimethylindium (TMIn), arsine (AsH)._Three), Phosphine (PH_Three) Is used. As n-type and p-type doping materials, disilane (Si₂H₆) And diethylzinc (DEZn), respectively. The carrier gas is hydrogen and the growth pressure is 100 hPa.
[0059]
First, a 100 nm thick silicon oxide film is deposited by thermal CVD on an n-type InP substrate 1a having a (001) plane as a growth surface. Then, it is processed into a pair of stripe-shaped silicon oxide masks 13a having a mask width of 5 μm and an opening width of 1.5 μm using a general photolithography technique (FIG. 4A). The stripe orientation indicating the longitudinal direction of the stripe is the [110] direction.
[0060]
Next, the substrate is set in the MOVPE apparatus, and the n-type InP cladding layer 2a, the n-side InAlGaAs light guide layer 3a, the strained multiple quantum well active layer 4a including the InAlGaAs layer, the p-side InAlGaAs light guide layer 5a, the p-type InP layer A normal mesa-shaped active layer waveguide composed of one clad layer 56a is formed by selective growth (FIG. 4B). Further, the p-type InP protective layer 7a is continuously grown without being exposed to the atmosphere (FIG. 4C). The growth temperature and the growth rate on the (001) plane of the selective growth region are 640 ° C. and 0.5 μm / h from the n-type InP cladding layer 2a to the p-type InP first cladding layer 56a, respectively, and the p-type InP protective layer 7a. 590 ° C. and 1.5 μm / h. Thereafter, it is taken out from the MOVPE apparatus, and a silicon oxide mask 213a is formed only on the mesa top by a self-alignment process (FIG. 4D).
[0061]
Next, it is set again in the MOVPE apparatus, and the p-type InP current blocking layer 8a and the n-type InP current blocking layer 8b are formed by selective growth at a growth temperature of 630 ° C. (FIG. 4E). After removing the silicon oxide mask 213a from the MOVPE apparatus, the p-type InP second cladding layer 9a and the p-type InGaAs contact layer 10a are grown at a growth temperature of 600 ° C. in the third MOVPE growth, and then the p-type electrode 11 is formed. The ASM-LD shown in FIG. 3 can be manufactured by forming, polishing the n-type InP substrate 1a, and forming the n-type electrode 12.
[0062]
When this semiconductor laser was subjected to end face coating with a resonator length of 300 μm, a front surface of 30%, and a rear surface of 90%, the laser characteristics were evaluated. The threshold current at 25 ° C. was 8 mA and the slope efficiency was as low as 0.45 W / A. Laser oscillation with threshold current and high efficiency was obtained. In addition, laser oscillation up to 120 ° C. was confirmed, and continuous operation at high temperature was also confirmed.
(Second embodiment)
FIG. 5 is a structural diagram of a 1.3 μm band ASM-LD using a semiconductor layer containing Al as an active layer in the second embodiment of the present invention, as in the first embodiment. The difference from the first embodiment is that the side surface of the active layer waveguide is covered with the p-type InP first cladding layer 6a, and the p-type InP first cladding layer 6a serves as the protective layer 7a in the first embodiment. I'm in charge.
[0063]
FIG. 6 shows a production process diagram of Example 2. As in the first embodiment, the MOVPE method is used for crystal growth, and TMAl, TEGa, TMIn, AsH are used as raw materials._Three, PH_ThreeAs an n-type and p-type doping material, Si is used.₂H₆And DEZn are used. The carrier gas is hydrogen and the growth pressure is 100 hPa.
[0064]
First, a 100 nm thick silicon oxide film is deposited by thermal CVD on an n-type InP substrate 1a having a (001) plane as a growth surface. Then, it is processed into a pair of stripe-shaped silicon oxide masks 13a having a mask width of 5 μm and an opening width of 1.5 μm using a general photolithography technique (FIG. 6A). The stripe orientation indicating the longitudinal direction of the stripe is the [110] direction.
[0065]
Next, the substrate is set in the MOVPE apparatus, and the n-type InP cladding layer 2a, the n-side InAlGaAs light guide layer 3a, the strained multiple quantum well active layer 4a containing InAlGaAs, the p-side InAlGaAs light guide layer 5a, the p-type InP first A forward mesa-shaped active layer waveguide composed of the clad layer 6a is formed by selective growth (FIG. 6B). The thickness of the p-type InP first clad layer 6a is 200 nm for the (001) plane that is the mesa top and 20 nm for the (111) B plane that is the mesa side surface. The growth temperature and the growth rate in the (001) plane of the selective growth region are 640 ° C. for the n-type InP cladding layer 2a, the n-side InAlGaAs light guide layer 3a, the multiple quantum well active layer 4a, and the p-side InAlGaAs light guide layer 5a. The p-type InP first cladding layer 6a is 620 ° C. and 2.5 μm / h at 0.5 μm / h. In the second embodiment, the growth on the side surface of the mesa stripe is promoted by lowering the growth temperature of the p-type InP first clad layer 6a to function as a protective layer.
[0066]
Thereafter, it is taken out from the MOVPE apparatus, and after the self-alignment process, the formation of the current blocking layer 8a, the formation of the p-type InP second cladding layer 9a, and the formation of the p-type InGaAs contact layer 10a as in the first embodiment, the structure of FIG. Can be produced.
[0067]
FIG. 7 shows the result of forming the InP protective layer on the side surface of the mesa stripe by changing the growth temperature and the growth rate in the (001) plane of the selective growth region. The stripe was formed so that the longitudinal direction of the stripe was the [110] direction. After the growth, the side surface of the mesa stripe was observed with a scanning electron microscope, and the relationship between the coating state of the (111) B surface and the growth conditions was plotted.
[0068]
FIG. 7 is a graph in which the relationship between the growth conditions consisting of the growth temperature (Tg) and the growth rate (Rg) is the xy plane according to (x, y) = (Tg, Rg), and the mesa side surface is completely Is marked on the xy plane if it is covered, △ is marked if it is partially covered, and x is marked if not covered.
[0069]
When the growth temperature was from 560 ° C. to 620 ° C., the growth rate was in the range of 0.3 μm / h to 3 μm / h in which the experiment was performed, and flat InP growth on the (111) B plane could be confirmed. However, the flatness decreased at 560 ° C. or lower, and the protective layer could not be sufficiently covered on the side of the mesa stripe. This is because (1) the migration length of In atoms was shortened due to a decrease in growth temperature, and (2) PH_ThreeThis is thought to be because the decomposition efficiency of the liquid crystal decreased and the crystallinity deteriorated due to insufficient P (phosphorus) pressure. Further, at 670 ° C. or higher, the growth to the (111) B plane was suppressed. This is presumably because the deposition rate of In atoms decreased because the growth temperature was too high. On the other hand, at 620 ° C. to 670 ° C., the (111) B plane can be grown by increasing the growth rate as the growth temperature rises. The growth rate is considered to be 3 μm / h or less on the (001) plane considering the flatness of the growth layer and the controllability of the thickness.
[0070]
Therefore, (Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3), and (560, 3) are surrounded by five points. By forming the protective layer on the side surface of the stripe at a growth temperature and growth rate at an arbitrary point in the region, growth with excellent coverage, flatness, and crystallinity is possible. In the first example, the p-type InP protective layer 7a is grown at 590 ° C. and 1.5 μm / h, and in Example 2, the p-type InP first clad layer is grown at 620 ° C. and 2.5 μm / h, thereby protecting the layer. Is formed on the side surface of the mesa stripe to suppress the oxidation of the semiconductor layer containing Al.
[0071]
Since the growth rate of the (001) plane does not change even if the growth plane is tilted several degrees, the relationship with respect to the (111) B plane shown in FIG. 7 is almost the same.
(Third embodiment)
FIG. 8 is a perspective view after the active layer waveguide is formed by selective growth in the third embodiment of the present invention. Similar to the first and second embodiments, it is a 1.3 μm band ASM-LD using a semiconductor layer containing Al as an active layer.
[0072]
N-type InP substrate 1a having a (001) plane as a growth plane (carrier concentration n = 2 × 10¹⁸cm^-3) Two striped silicon oxide masks 13a are formed on the (001) plane with an inclination of 0.5 degrees from the [110] direction, and a mesa striped n-type InP cladding layer 2a is sandwiched between them. (Thickness d = 200 nm, n = 1 × 10¹⁸cm^-3), N-side InAlGaAs light guide layer 3a (d = 50 nm, non-doped), InAlGaAs well (d = 6 nm, 1.5% compressive strain, 7 well), InAlGaAs barrier (d = 10 nm, 0.9% tensile strain) The strained multiple quantum well active layer 4a, the p-side InAlGaAs optical guide layer 5a (d = 50 nm, non-doped), and the p-type InP first cladding layer 6a (d = 200 nm, p = 5 × 10)¹⁷cm^-3) Is formed.
[0073]
The side surface of the strained multiple quantum well active layer 4a is covered with a p-type InP first cladding layer 6a, and the p-type InP first cladding layer 6a serves as a protective layer. The thickness of the p-type InP first cladding layer 6a on the (111) B plane is 40 nm.
[0074]
Next, a manufacturing method will be described. FIG. 9 is a manufacturing process diagram of the third embodiment and shows the process until the active layer waveguide is formed by selective growth. As in the first and second embodiments, the MOVPE method is used for crystal growth, and TMAl, TEGa, TMIn, AsH are used as raw materials._Three, PH_ThreeAs an n-type and p-type doping material, Si₂H₆And DEZn are used. The carrier gas is hydrogen and the growth pressure is 100 hPa.
[0075]
First, a 100 nm thick silicon oxide film is deposited by thermal CVD on an n-type InP substrate 1a having a (001) plane as a growth surface. Then, it is processed into a pair of stripe-shaped silicon oxide masks 13a each having a width of 5 μm and an opening width of 1.5 μm using a general photolithography technique (FIG. 9A). At this time, the longitudinal direction of the stripe is intentionally inclined by 0.5 degrees within the (001) plane from the [110] direction (FIG. 9B).
[0076]
Next, the substrate is set in the MOVPE apparatus, and the n-type InP cladding layer 2a, the n-side InAlGaAs light guide layer 3a, the strained multiple quantum well active layer 4a containing InAlGaAs, the p-side InAlGaAs light guide layer 5a, the p-type InP first A forward mesa-shaped DH (Double Hetero) structure composed of the clad layer 6a is formed by selective growth (FIG. 9C). The growth temperature and growth rate are 640 ° C. and 0.5 μm / h from the n-type InP cladding layer 2a to the p-side InAlGaAs optical guide layer 5a, and the p-type InP first cladding layer 6a is 600 ° C. and 0.5 μm / h. is there.
[0077]
Since the silicon oxide mask 13a is tilted by 0.5 degrees in the (001) plane from the [110] direction, the DH mesa stripe formed by selective growth is also tilted. Furthermore, since the mesa side surface is also inclined, the step density on the (111) B surface is increased, and the adsorption probability of the group III atoms is increased as compared with the case where the mesa side is not inclined. As a result, the growth on the mesa side surface is promoted during the growth of the p-type InP first cladding layer 6a, and the side surfaces of the Al-containing semiconductor layers (light guide layers (3a, 5a), active layer 4a) can be covered. .
[0078]
In the third embodiment, the case where the stripe inclination angle is 0.5 degrees has been described. Since the step interval on the (111) B surface is shortened and the step density is increased in proportion to the tilt angle, the effects of the present invention such as promoting growth and improving flatness on the (111) B surface are effective by slightly inclining the stripe. Can be obtained. Considering the range of tilt angles, if the stripe is tilted by X degrees from a reference in the [110] direction (for example, a cleavage plane), the stripe from the [110] direction stripe at a distance of L (μm) in length. The deviation amount S (μm) can be expressed by equation (1).
[0079]
S = L × 1000 tan (X) (1)
When a 2-inch substrate (diameter: about 50 mm) is used, S is about 9 μm when the tilt angle is 0.01 degrees. The size of 9 μm is a size that can be intentionally shifted by a human in a normal photolithography process using a contact exposure machine or the like. However, considering reproducibility for each substrate, it is considered appropriate to set the tilt angle to 0.01 degrees or more as the accuracy with which the tilt angle can be intentionally controlled.
[0080]
On the other hand, in FIGS. 10A, 10 </ b> B, and 10 </ b> C, the silicon oxide mask 13 a used for selective growth has a tilt angle from the [110] direction of 0 degree, 3 degrees, and 5 degrees after the formation of the protective layer. The mesa stripe shape is shown. The p-type InP first cladding layer 6a was used as the protective layer. As the stripe inclination angle increases, the growth rate on the (111) B plane increases, from a forward mesa shape (when the inclination angle is 0 degree) to a mushroom shape (3 degrees), a pseudo-inverse mesa shape (5 degrees). ).
[0081]
In the pseudo inverted mesa shape shown in FIG. 10C, a stagnation layer is formed in the lower part of the eaves when the silicon oxide film is deposited by thermal CVD in the self-alignment process shown in FIG. Becomes thicker. Therefore, it is impossible to form the silicon oxide film 14 so that dt> ds (see FIG. 18A). Therefore, it is better to set the inclination angle to 3 degrees or less.
[0082]
From the above results, it is desirable that the tilt angle of the silicon oxide mask 13a used for selective growth is 0.01 degrees or more and 3 degrees or less.
[0083]
In the third embodiment, the opening width and the mask width are constant, and the entire stripe mask is inclined by a certain angle. However, when a part of the mask is tilted as in the mask pattern shown in FIG. 11 (FIG. 11 (a)) or when a plurality of tilt angles are changed (FIG. 11 (b)), the opening width or mask width is changed. The present invention is effective if a protective layer that covers the side surface of the active layer waveguide can be formed by such action, such as in the case of FIG. 11 (c). In the first to third embodiments, the case of a semiconductor element having an ASM structure in which an active layer includes an InAlGaAs layer has been described. However, the present invention is effective even when AlGaAs, InAlGaP, or the like is used.
[0084]
In the first to third embodiments, the case where the plane orientation of the semiconductor substrate is the (001) plane has been described. However, even if the semiconductor substrate is inclined several degrees in the [1-10] direction or the [−110] direction. Good. This inclination of several degrees is an angle in a range in which the mesa side surface formed by selective MOVPE growth becomes the (111) B plane.
[0085]
As an example, FIG. 12 shows a cross-sectional structure after forming an active layer waveguide using a (001) InP substrate tilted by 5 degrees in the [1-10] direction. By tilting 5 degrees, the growth plane and the (111) B plane form 59.7 degrees and 49.7 degrees, respectively. However, the (111) B plane can be formed by selective growth, that is, the p-type InP first cladding layer 6a as a protective layer can be formed, and the present invention can be applied. The angle at which the effect of the present invention is obtained is up to about 15 degrees at which the (111) B plane can be formed.
[0086]
Further, the plane orientation of the semiconductor substrate may be tilted from the (001) plane in the [110] direction or the [-1-10] direction. Since the step density of the (111) B plane increases according to the tilt angle, the growth of the (111) B plane and the improvement in flatness, which are the functions of the present invention, can be obtained.
[0087]
As an example, FIG. 13 shows a cross-sectional view of an ASM-LD manufactured using a (001) InP substrate tilted by 1 degree in the [110] direction. FIG. 13A is a cross-sectional view as viewed from a direction perpendicular to the waveguide, and FIG. 13B is a cross-sectional view as viewed from a direction parallel to the waveguide. By tilting in the [110] direction by 1 degree, the end face formed by cleavage is also tilted by 1 degree. Since the (110) plane and the (-1-10) plane formed by cleavage as the reflection surface of the semiconductor laser are also inclined, the mirror loss increases and the threshold current increases, but the present invention is applied. Thus, if the effect of the present invention, that is, improvement of reliability and yield is sufficiently obtained, the present invention is effective up to the tilt angle. Furthermore, when the reflective surface is formed using dry etching, a vertical mirror can be formed without depending on the tilt angle of the substrate, so there is no need to worry about deterioration of the laser characteristics.
[0088]
In the first to third embodiments, the forward mesa shape stripe has been described. However, the stripe shape is not limited to the forward mesa shape, and the side surface of the stripe is perpendicular to the surface of the semiconductor substrate. May be.
[0089]
【The invention's effect】
According to the present invention, in a semiconductor device using a semiconductor layer containing Al as an active layer, reliability and yield can be obtained without exposing the active layer to the atmosphere by covering the stripe side with a semiconductor layer not containing Al. Semiconductor device and a manufacturing method thereof can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a basic structure of a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of a basic structure of the present invention.
FIG. 3 is a structural cross-sectional view of a 1.3 μm band ASM-LD using a semiconductor layer containing Al as an active layer in the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of the first embodiment of the present invention.
FIG. 5 is a structural cross-sectional view of an ASM-LD that is a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment of the present invention.
FIG. 7 is a graph showing the growth condition dependency of the mesa side surface covering form, which is the operation of the first and second embodiments of the present invention.
FIG. 8 is a perspective view showing a structure after forming an active layer waveguide in a third embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a manufacturing process of the third embodiment of the present invention.
FIG. 10 is a diagram showing the relationship between the shape of a mesa stripe formed by selective growth and the tilt angle.
FIG. 11 is a diagram showing a mask pattern for selective growth as an application example of the third embodiment of the present invention.
12 is a cross-sectional structure diagram after an active layer waveguide is formed on an InP substrate having a plane orientation (001) inclined by 5 degrees in the [1-10] direction. FIG.
FIG. 13 is a cross-sectional structure diagram of an ASM-LD formed on an InP substrate having a plane orientation (001) inclined by 1 degree in the [110] direction.
FIG. 14 is a cross-sectional view of a BH-LD in which a waveguide is formed by wet etching.
FIG. 15 is a cross-sectional view showing a manufacturing process of a BH-LD in which a waveguide is formed by wet etching.
FIG. 16 is a cross-sectional view showing the structure of a conventional ASM-LD.
FIG. 17 is a cross-sectional view showing a manufacturing process of a conventional ASM-LD.
FIG. 18 is a cross-sectional view showing a self-alignment process.
[Explanation of symbols]
1 Semiconductor substrate
1a n-type InP substrate
2 First conductivity type cladding layer
2a n-type InP cladding layer
2b n-type InP first cladding layer
2c n-type InAlGaAs second cladding layer
3a n-side InAlGaAs light guide layer
3b n-side InGaAsP light guide layer
4 Active layer
4a, 4b Strained multiple quantum well active layer
4c InGaAsP active layer
5a p-side InAlGaAs light guide layer
5b p-side InGaAsP light guide layer
6 Second conductivity type first cladding layer
6a, 56a, 206 p-type InP first cladding layer
7 Protective layer
7a p-type InP protective layer
8 Current blocking layer
8a p-type InP current blocking layer
8b n-type InP current blocking layer
9 Second conductivity type second cladding layer
9a p-type InP second cladding layer
10 Second conductivity type contact layer
10a p-type InGaAs contact layer
10b p-type InGaAsP contact layer
10c InGaAsP cap layer
11 p-side electrode
12 n-side electrode
13, 213 Dielectric mask
13a, 213a Silicon oxide mask
14 Silicon oxide film
15 resist
200 Zn diffusion region

Claims (7)

A stripe having a (111) B plane composed of a first conductivity type cladding layer, an active layer containing Al, and a second conductivity type first cladding layer laminated in a predetermined region on an InP substrate;
A current blocking layer having the stripe embedded therein;
A second conductivity type second cladding layer formed on the stripe and the current blocking layer;
In a semiconductor device comprising a second conductivity type contact layer formed on the second conductivity type second cladding layer,
An InP protective layer between the stripe having the (111) B surface including the active layer and the current blocking layer;
A semiconductor element in which a plane orientation of the semiconductor substrate is inclined from (001) to a [110] direction or a [-1-10] direction. The semiconductor element according to claim 1 , wherein a material of the second conductivity type first cladding layer and the protective layer is InP . The conditions for forming the InP protective layer are as follows:
Let the growth temperature be Tg (° C)
If the growth rate is Rg (μm / h),
From the relationship between the growth temperature and the growth rate indicated on the xy plane by (x, y) = (Tg, Rg),
(Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3), (560, 3) in a region surrounded by connecting the five points The semiconductor element according to claim 1 , wherein the semiconductor element has a growth temperature and a growth rate determined at an arbitrary point. A first conductivity type cladding layer, an active layer containing Al, and a second conductivity type first cladding layer on an InP substrate whose plane orientation is inclined in the [110] direction or [-1-10] direction from the (001) plane Forming a stripe having a (111) B surface comprising:
Forming the second conductive type first cladding layer so as to cover the exposed surface of the stripe including the active layer with an InP protective layer without exposure to oxygen;
Forming a dielectric mask on top of the stripe;
Forming a current blocking layer on the exposed surface of the InP protective layer , the stripe and the semiconductor substrate;
Removing the dielectric mask;
Forming a second conductivity type second cladding layer on the exposed surface of the InP protective layer or the stripe and the current blocking layer;
Forming a second conductivity type contact layer on the second conductivity type second clad layer. On a InP substrate whose plane orientation is inclined in the [110] direction or [-1-10] direction from the (001) plane, the mesa side surface is a (111) B plane and includes a first conductivity type cladding layer and Al Forming an active layer ;
After forming the active layer, without exposing to oxygen, a second conductivity type InP first cladding layer is formed so as to cover the upper part of the active layer and the exposed surface of the active layer, and the first conductivity type cladding layer, Forming a stripe composed of the active layer and the second conductivity type InP first cladding layer ;
Forming a dielectric mask on top of the stripe;
Forming a current blocking layer on the stripe and the exposed surface of the semiconductor substrate;
Removing the dielectric mask;
Forming a second conductivity type second cladding layer on the exposed surface of the stripe and the current blocking layer;
Forming a second conductivity type contact layer on the second conductivity type second clad layer. The conditions for forming the InP protective layer are as follows:
Let the growth temperature be Tg (° C)
If the growth rate is Rg (μm / h),
From the relationship between the growth temperature and the growth rate indicated on the xy plane by (x, y) = (Tg, Rg),
(Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3), (560, 3) in a region surrounded by connecting the five points The method for manufacturing a semiconductor device according to claim 4 , wherein the growth temperature and the growth rate are determined at an arbitrary point. The conditions for forming the second conductivity type InP first cladding layer are as follows:
Let the growth temperature be Tg (° C)
If the growth rate is Rg (μm / h),
From the relationship between the growth temperature and the growth rate indicated on the xy plane by (x, y) = (Tg, Rg),
(Tg, Rg) = (560, 0.3), (620, 0.3), (670, 2), (670, 3), (560, 3) in a region surrounded by connecting the five points The method for manufacturing a semiconductor device according to claim 5 , wherein the growth temperature and the growth rate are determined at an arbitrary point.

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