JP7010546B2 - Optical semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to an optical semiconductor device and a method for manufacturing the same.

An optical semiconductor device that outputs light is used in an optical communication system or the like (Patent Document 1). In order to realize high output operation of the optical semiconductor element in a high temperature environment, it is important to reduce the series resistance of the optical semiconductor element and to efficiently inject a current into the active layer which is a light emitting layer. In order to improve the efficiency of current injection, for example, a thyristor structure in which n-type, p-type, n-type, and p-type conductive semiconductor layers are laminated may be formed in the vicinity of the active layer.

Japanese Unexamined Patent Publication No. 5-55696

In order to form a thyristor structure, a clad layer is laminated on the active layer, and a conductive block layer opposite to the clad layer is provided on the clad layer. However, since the current injected into the active layer is narrowed by the block layer, the series resistance of the optical semiconductor device increases. In addition, a leak current may occur between the active layer and the block layer.

Therefore, it is an object of the present invention to provide an optical semiconductor device capable of reducing series resistance and suppressing leakage current, and a method for manufacturing the same.

The optical semiconductor device according to the present invention is provided on a semiconductor substrate, an n-type clad layer provided on the semiconductor substrate, an active layer provided on the n-type clad layer, and an active layer. A second p-type clad layer provided on both sides of the first p-type clad layer on the active layer and having a higher carrier concentration than the first p-type clad layer. The p-type clad layer, the n-type block layer provided on the second p-type clad layer, and the third p-type clad layer and the third n-type block layer provided on the n-type block layer. It is provided with a p-type clad layer.

The method for manufacturing an optical semiconductor device according to the present invention includes a step of forming an n-type clad layer on a semiconductor substrate, a step of forming an active layer on the n-type clad layer, and a first step on the active layer. 1. A step of forming a p-type clad layer, a step of forming a striped mask on the first p-type clad layer, a step of forming a striped mesa using the striped mask as a mask, and the above-mentioned step. Using the step of retracting the mask by etching and the retracted mask, carriers on both sides of the first p-type clad layer on the active layer are higher than those of the first p-type clad layer. A step of forming a second p-type clad layer having a concentration, a step of forming an n-type block layer on the second p-type clad layer, and the first p-type clad layer and the n-type block. It has a step of forming a third p-type clad layer on the layer.

According to the above invention, it is possible to reduce the series resistance and suppress the leakage current.

FIG. 1 is a cross-sectional view illustrating the optical semiconductor device used in the simulation. FIG. 2A is a calculation result of the series resistance of the optical semiconductor device. FIG. 2B shows the experimental results of the drive current. FIG. 3A is a calculation result of the potential of the conduction band. FIG. 3B is a calculation result of the energy barrier. FIG. 4A is a diagram showing the relationship between the carrier concentration and the energy barrier. FIG. 4B is a diagram showing the relationship between the thickness and the carrier concentration. FIG. 5A is a plan view illustrating the optical semiconductor device according to the first embodiment. 5 (b) is a cross-sectional view taken along the line AA of FIG. 5 (a). FIG. 6 is an enlarged cross-sectional view of the vicinity of the mesa. 7 (a) and 7 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. 8 (a) and 8 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. 9 (a) and 9 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. 10 (a) and 10 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. 11 (a) and 11 (b) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the second embodiment. FIG. 12 is a diagram showing the relationship between the DMZ flow rate and the carrier concentration. FIG. 13 is a cross-sectional view illustrating the optical semiconductor device according to the third embodiment. 14 (a) to 14 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. 15 (a) to 15 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. 16 (a) to 16 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device.

[Explanation of Embodiments of the present invention]
First, the contents of the embodiments of the present invention will be listed and described.
One embodiment of the present invention comprises (1) a semiconductor substrate, an n-type clad layer provided on the semiconductor substrate, an active layer provided on the n-type clad layer, and an active layer on the active layer. A first p-type clad layer provided and a second p-type clad layer provided on both sides of the first p-type clad layer on the active layer and having a higher carrier concentration than the first p-type clad layer. 2. The p-type clad layer, the n-type block layer provided on the second p-type clad layer, and the third p-type clad layer and the third n-type block layer provided on the first p-type clad layer and the n-type block layer. An optical semiconductor device comprising the p-type clad layer of the above. Since the carrier concentration of the second p-type clad layer is high, it is possible to reduce the series resistance and suppress the leakage current flowing from the active layer to the n-type block layer.
(2) The thickness of the second p-type clad layer may be 0.05 μm or more and 0.15 μm or less. This makes it possible to reduce the series resistance of the optical semiconductor device.
(3) The n-type clad layer and the active layer form a mesa, and a p-type embedded layer provided on both sides of the n-type clad layer on the n-type clad layer is provided. The p-type clad layer 2 may be provided from above the active layer to above the embedded layer. As a result, the series resistance can be reduced and the leakage current can be suppressed.
(4) The n-type clad layer and the active layer form a mesa, provided with embedded layers provided on both sides of the mesa, and the second p-type clad layer is provided on the active layer. It does not have to be provided on the embedded layer. As a result, the series resistance can be reduced and the leakage current can be suppressed.
(5) The present invention comprises a step of forming an n-type clad layer on a semiconductor substrate, a step of forming an active layer on the n-type clad layer, and a first p-type clad on the active layer. A step of forming a layer, a step of forming a striped mask on the first p-type clad layer, a step of forming a striped mesa using the striped mask as a mask, and a step of retreating the mask by etching. A second step, using the retracted mask, having a higher carrier concentration than the first p-type clad layer on both sides of the first p-type clad layer on the active layer. A step of forming the p-type clad layer, a step of forming an n-type block layer on the second p-type clad layer, and a first step on the first p-type clad layer and the n-type block layer. 3 is a method for manufacturing an optical semiconductor device having a step of forming a p-type clad layer. Since the carrier concentration of the second p-type clad layer is high, it is possible to reduce the series resistance and suppress the leakage current flowing from the active layer to the n-type block layer.
(6) In the step of forming the second p-type clad layer, the step of etching the first p-type clad layer using the retracted mask and the step of etching the first p-type clad layer. After the step, the step of forming the second p-type clad layer by the MOCVD method may be included. A second p-type clad layer can be formed by the MOCVD method.
(7) The step of forming the second p-type clad layer is also a step of forming the second p-type clad layer by gas-phase diffusing a dopant in a part of the first p-type clad layer. good. This makes it possible to form a second p-type clad layer having a high carrier concentration.
(8) The second p-type clad layer is formed by having a step of forming a p-type embedded layer on both sides of the mesa and a step of forming another mask on the embedded layer. The step may be a step of gas-phase diffusing the dopant in a portion of the first p-type clad layer exposed from the retracted mask and the other mask. This makes it possible to form a second p-type clad layer having a high carrier concentration.

[Details of Embodiments of the present invention]
Specific examples of the optical semiconductor device and the manufacturing method thereof according to the embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

(simulation)
First, a simulation that verifies the series resistance and leakage current of an optical semiconductor device will be described. FIG. 1 is a cross-sectional view illustrating the optical semiconductor device 90 used in the simulation.

As shown in FIG. 1, an n-type clad layer 12, an active layer 14, and a p-type clad layer 16 are laminated on a substrate 10, and these form a mesa 11. Embedded layers 18 are provided on both sides of the mesa 11 on the n-type clad layer 12. The n-type block layer 22 is provided from the peripheral edge of the upper surface of the p-type clad layer 16 to the upper surface of the embedded layer 18. The p-type clad layer 24 is provided on the central portion of the p-type clad layer 16 and the n-type block layer 22, and the p-type contact layer 26 is provided on the p-type clad layer 24. From the substrate 10 to the p-type contact layer 26, a thyristor structure in which n-type, p-type, n-type, and p-type conductive layers are laminated is formed. An insulating film 28 and an electrode 30 are provided on the p-type contact layer 26. An electrode 36 is provided on the lower surface of the substrate 10.

The substrate 10 and the n-type clad layer 12 are formed of silicon (Si) -doped n-type indium phosphide (InP). The active layer 14 has a multi-quantum well (MQW) structure in which a plurality of indium gallium arsenide phosphorus (InGaAsP) layers doped with zinc (Zn) are laminated. The p-type clad layers 16 and 24 and the embedded layer 18 are formed of Zn-doped p-type InP. The n-type block layer 22 is formed of n-type InP. The p-type contact layer 26 is formed of Zn-doped p-type InGaAs. The insulating film 28 is made of silicon nitride (SiN). The electrodes 30 and 36 are made of gold (Au) or the like.

FIG. 2A is a calculation result of the series resistance of the optical semiconductor element 90. The horizontal axis represents the thickness of the p-type clad layer 16, and the vertical axis represents the series resistance. The higher the carrier concentration of the p-type clad layer 16, the lower the electrical resistance of the p-type clad layer 16 and the lower the series resistance of the optical semiconductor element 90. In the simulation of FIG. 2 (a), the carrier concentration was set to be constant at 1.8 × 10 ¹⁸ cm ^-3 . The thickness of the n-type block layer 22 was 0.15 μm, the width of the active layer 14 was 1.25 μm, and the resonator length was 150 μm. As shown in FIG. 2A, the thinner the p-type clad layer 16 is, the lower the series resistance is. The current is injected into the active layer 14 via the p-type clad layers 24 and 16. It is presumed that the series resistance increases as the n-type block layer 22 narrows the current. It is considered that when the p-type clad layer 16 becomes thin, the distance through which the narrowed current flows becomes short, and the increase in series resistance is suppressed. That is, in order to reduce the series resistance, it is effective to make the p-type clad layer 16 thin. However, the leakage current may increase.

FIG. 2B shows the experimental results of the drive current. The horizontal axis represents the temperature of the optical semiconductor element 90. The vertical axis represents the drive current for producing an optical output of 16 mW. The larger the drive current, the larger the leak current flowing from the active layer 14 to the n-type block layer 22 via the p-type clad layer 16. In the figure, the squares represent the experimental results when the thickness of the p-type clad layer 16 is 0.05 μm, the triangles represent the experimental results when the thickness is 0.07 μm, and the circles represent the experimental results when the thickness is 0.1 μm. .. As shown in FIG. 2B, the higher the temperature, the larger the drive current, and the thinner the p-type clad layer 16, the larger the drive current.

As described above, by thinning the p-type clad layer 16, the series resistance can be lowered, but the leakage current increases. In order to suppress the leakage current, it is preferable that a large energy barrier is formed in the conduction band. The simulation of the energy barrier will be described below.

FIG. 3A is a calculation result of the potential of the conduction band. The horizontal axis represents the depth from the surface of the p-type contact layer 26, and the vertical axis represents the potential of the conduction band of the optical semiconductor device 90. The solid line is the calculation result when the thickness of the p-type clad layer 16 is 0.5 μm, and the broken line is the calculation result when the thickness is 0.1 μm. The carrier concentration was 5 × 10 ¹⁷ cm ^-3 . As shown in FIG. 3A, energy barriers b1 and b2 are formed in the conduction band at the interface of the np junction (the interface between the p-type clad layer 16 and the n-type block layer 22). The energy barrier b1 when the thickness is 0.5 μm is about 0.2 V, which is larger than the energy barrier b2 when the thickness is 0.1 μm.

FIG. 3B is a calculation result of the energy barrier. The horizontal axis is the thickness of the p-type clad layer 16, and the vertical axis is the energy barrier at the interface between the p-type clad layer 16 and the n-type block layer 22. The carrier concentration of the p-type clad layer 16 was 5 × 10 ¹⁷ cm ^-3 . As shown in FIG. 3B, the thinner the p-type clad layer 16, the smaller the energy barrier. For example, if the thickness is 0.1 μm, the energy barrier is 0.008 V.

The smaller the thickness, the smaller the energy barrier as shown in FIGS. 4 (a) and 4 (b), and the larger the leak current as shown in FIG. 2 (b). That is, if the energy barrier is low, the leakage current increases. Therefore, in order to reduce the leakage current, it is effective to raise the energy barrier.

FIG. 4A is a diagram showing the relationship between the carrier concentration and the energy barrier. The horizontal axis represents the carrier concentration of the p-type clad layer 16, and the vertical axis represents the energy barrier. The circle is the calculation result when the thickness of the p-type clad layer 16 is 0.1 μm, the triangle is the calculation result when the thickness is 0.08 μm, the square is the calculation result when the thickness is 0.06 μm, and the diamond is the thickness. The calculation result in the case of 0.04 μm is shown. The higher the carrier concentration at any thickness, the greater the energy barrier. For example, at a thickness of 0.04 μm, the carrier concentration can be set to 1 × 10 ¹⁹ cm ^-3 , so that the size of the energy barrier can be set to about 0.07 V.

FIG. 4B is a diagram showing the relationship between the thickness and the carrier concentration, and shows the thickness and the carrier concentration adjusted so that the energy barrier is 0.05V. The horizontal axis represents the thickness of the p-type clad layer 16, and the vertical axis represents the carrier concentration of the p-type clad layer 16. The solid line in the figure shows the relationship between the thickness and the carrier concentration so that the energy barrier is 0.05 V. As shown in FIG. 4B, the carrier concentration is increased as the p-type clad layer 16 is made thinner. As a result, the height of the energy barrier can be maintained at 0.05V. For example, in the case of a thickness of 0.1 μm, the carrier concentration is about 2 × 10 ¹⁸ cm ^-3 . If the thickness is 0.06 μm, the carrier concentration is about 5 × 10 ¹⁸ cm ^-3 . From the result of FIG. 4B, in order to make the energy barrier 0.05V or more, the following equation (1) may be established. T is the thickness of the p-type clad layer 16, d is the carrier concentration, and n is 1.5.
d × T ⁿ > 6.5e16 (1)

As shown in FIG. 2A, the series resistance can be reduced by thinning the p-type clad layer 16. Further, as shown in FIGS. 4 (a) and 4 (b), the energy barrier can be increased and the leakage current can be suppressed by increasing the carrier concentration. Examples based on the above findings will be described.

(Optical semiconductor device)
FIG. 5A is a plan view illustrating the optical semiconductor device 100 according to the first embodiment. 5 (b) is a cross-sectional view taken along the line AA of FIG. 5 (a). FIG. 6 is an enlarged cross-sectional view of the vicinity of the mesa 11. The X, Y and Z directions are orthogonal to each other.

As shown in FIG. 5A, the optical semiconductor device 100 is a rectangular semiconductor laser device extending in the XY plane. The length L1 in the X direction and the length L2 in the Y direction are, for example, 200 μm to 500 μm.

As shown in FIG. 5B, an n-type clad layer 12 is provided on the substrate 10 (semiconductor substrate), and grooves 13 and 15 are formed in the n-type clad layer 12. A mesa 11 is formed between the groove 13 and the groove 15. The configuration around the mesa 11 will be described later. In each region from the groove 13 to the −X side end and from the groove 15 to the + X side end, the embedded layer 18, the p-type clad layer 20, and the n-type block layer 22 are placed on the n-type clad layer 12. , The p-type clad layer 24, the p-type contact layer 26, and the insulating film 28 are laminated in this order. The insulating film 28 covers the surface of the optical semiconductor device 100 and has openings in the groove 13 and on the mesa 11.

An electrode 31 that comes into contact with the n-type clad layer 12 is provided in the groove 13. A wiring 32 is provided on the insulating film 28 from the groove 13 onto the p-type contact layer 26 on the −X side. The electrode 33 comes into contact with the upper surface of the wiring 32. The wiring 32 contacts the electrode 31 in the groove 13. A wiring 34 is provided on the insulating film 28 from the mesa 11 to the p-type contact layer 26 on the + X side. The electrode 35 comes into contact with the upper surface of the wiring 34. The wiring 34 contacts the electrode 30 on the mesa 11. The wiring 32 and the wiring 34 are separated from each other. The wiring 32, the electrodes 31 and 33 are electrically connected to each other. The wiring 34, the electrodes 30 and 35 are electrically connected to each other.

As shown in FIG. 5B, the mesa 11 is located between the grooves 13 and 15, and the mesa 11 extends in the Y direction. As shown in FIG. 6, the n-type clad layer 12, the active layer 14, and the p-type clad layer 16 form a striped mesa 11. The n-type clad layer 12 has a convex shape, and the active layer 14 is in contact with the upper surface of the n-type clad layer 12. The p-type clad layer 16 (first p-type clad layer) is in contact with the central portion of the upper surface of the active layer 14. The embedded layer 18 is located on both sides of the mesa 11 and contacts the side surfaces of the n-type clad layer 12 and the active layer 14. A p-type clad layer 20 (second p-type clad layer) is provided from above the embedded layer 18 to the peripheral edge of the upper surface of the active layer 14. The n-type block layer 22 is provided on the p-type clad layer 20 and not on the p-type clad layer 16. The p-type clad layer 20 is in contact with the upper surfaces of the embedded layer 18 and the active layer 14, and the n-type block layer 22 is in contact with the upper surface of the p-type clad layer 20.

The p-type clad layer 24 (third p-type clad layer) is provided on the p-type clad layer 16 and the n-type block layer 22 and comes into contact with the upper surfaces thereof. The p-type contact layer 26 and the insulating film 28 are laminated in this order on the p-type clad layer 24. The insulating film 28 has an opening 28a on the mesa 11. The electrode 30 comes into contact with the p-type contact layer 26 exposed from the opening 28a. The electrode 36 comes into contact with the lower surface of the substrate 10. For example, a modulation signal and a bias current are supplied to the electrode 30 via the electrode 35 and the wiring 34 shown in FIG. 5 (b). The electrode 30 functions as an electrode for supplying an electric current to the active layer 14.

The substrate 10 and the n-type clad layer 12 are formed of, for example, an n-type InP doped with silicon (Si), and the carrier concentration is, for example, 1 × 10 ¹⁸ cm ^-3 . The active layer 14 has a multiple quantum well structure in which a plurality of Zn-doped InGaAsP layers are laminated, and generates light by recombination of carriers. The p-type clad layers 16 and 24 and the embedded layer 18 are formed of, for example, Zn-doped p-type InP. The thickness of the p-type clad layer 16 is, for example, 0.1 μm, and the thickness of the p-type clad layer 24 is, for example, 1.5 μm. The carrier concentrations of the p-type clad layers 16 and 24 are, for example, 5 × 10 ¹⁷ cm ^-3 .

The p-type clad layer 20 is formed of, for example, Zn-doped p-type InP. The thickness is, for example, 0.1 μm, which is equal to the thickness of the p-type clad layer 16. The carrier concentration of the p-type clad layer 20 is higher than that of the embedded layer 18, the p-type clad layers 16 and 24, for example, 2 × 10 ¹⁸ cm ^-3 . The n-type block layer 22 is formed of, for example, Si-doped n-type InP, has a carrier concentration of 2 × 10 ¹⁸ cm ^-3 , and a thickness of 0.3 μm. The p-type contact layer 26 is formed of Zn-doped p-type InGaAs and has a thickness of, for example, 0.1 μm. On both sides of the mesa 11, a thyristor structure in which n-type, p-type, n-type, and p-type conductive layers are laminated is formed from the substrate 10 to the p-type contact layer 26. The insulating film 28 is formed of an insulator such as SiN. The electrodes 30 and 36 are made of a metal such as Au.

(Production method)
7 (a) to 10 (b) are cross-sectional views illustrating a method for manufacturing the optical semiconductor device 100, and show a portion corresponding to FIG. Other parts of the optical semiconductor device 100 are also formed by the same process.

As shown in FIG. 7 (a), for example, by the organic metal vapor deposition (MOCVD) method, the n-type clad layer 12, the active layer 14, and the p-type clad layer 16 are placed on the substrate 10. Epitaxially grows in order. The thickness of the p-type clad layer 16 is, for example, 0.1 μm. The temperature (growth temperature) in the MOCVD apparatus is, for example, 620 ° C., and the growth pressure is, for example, 0.1 atm. The raw material gas of the n-type clad layer 12 contains, for example, trimethylindium (TMIn: Trimethyl Indium), phosphin (PH ₃ ) and silane (SiH ₄ ). The raw material gas of the active layer 14 contains, for example, TMIn, Triethyl Gallium (TEGa), PH ₃ and arsine (AsH ₃ ). The raw material gas of the p-type clad layer 16 contains, for example, TMIn, PH ₃ and DMZ. The flow rate of the DMZ, which is the raw material gas for the dopant, is, for example, 0.02 ccm, which is less than 0.1 ccm. A striped silicon oxide (SiO ₂ ) mask 40 is formed on the upper surface of the p-type clad layer 16. The mask 40 covers a part of the p-type clad layer 16.

As shown in FIG. 7B, the p-type clad layer 16, the active layer 14, and the n-type clad layer 12 are etched by, for example, a dry etching method to form a mesa 11. The etching depth is, for example, 1.5 μm. The portion under the mask 40 is not etched.

As shown in FIG. 8A, for example, the MOCVD method is used to grow p-type InP embedded layers 18 on both sides of the mesa 11. The raw material gas includes, for example, TMIn, PH ₃ and DMZ. Since the mask 40 functions as a growth mask, the embedded layer 18 does not grow under the mask 40. As shown in FIG. 8B, the mask 40 is etched with, for example, diluted hydrofluoric acid and retracted. The width and height of the mask 40 are reduced, and the peripheral edge of the upper surface of the p-type clad layer 16 is exposed from the mask 40.

As shown in FIG. 9A, the p-type clad layer 16 and the embedded layer 18 are etched with, for example, diluted oxalic acid. As a result, the peripheral portion of the p-type clad layer 16 is removed, and the active layer 14 is exposed. Further, the embedded layer 18 is etched to the same height as the active layer 14. The portion of the p-type clad layer 16 under the mask 40 is not etched, and the p-type clad layer 16 remains in the central portion of the upper surface of the active layer 14. As shown in FIG. 9B, the p-type clad layer 20 of p-type InP is grown by, for example, the MOCVD method using a mask 40. The raw material gas contains, for example, TMIn, PH ₃ and DMZ, and the flow rate of DMZ is, for example, 0.1 ccm or more. The carrier concentration of the p-type clad layer 20 is, for example, 2 × 10 ¹⁸ cm ^-3 . The p-type clad layer 20 is provided from the portion of the upper surface of the active layer 14 exposed from the mask 40 to the upper surface of the embedded layer 18, and is in contact with them. The thickness of the p-type clad layer 20 is 0.1 μm, which is the same as that of the p-type clad layer 16, for example.

As shown in FIG. 10A, an n-type block layer 22 of n-type InP is grown on the p-type clad layer 20 by, for example, a MOCVD method using a mask 40. The source gas contains, for example, TMIn, PH ₃ , and SiH ₄ . As shown in FIG. 10 (b), the mask 40 is removed by immersing the mask 40 in, for example, hydrofluoric acid for 1 minute. After removing the mask 40, the p-type clad layer 24 and the p-type contact layer 26 are sequentially grown on the p-type clad layer 16 and the n-type block layer 22 by the MOCVD method. The raw material gas of the p-type clad layer 24 contains, for example, TMIn, PH ₃ , and DMZ. The raw material gas of the p-type contact layer 26 contains, for example, TMIn, TEGa, AsH ₃ and DMZ. As shown in FIG. 6, an insulating film 28 is formed on the p-type contact layer 26 by, for example, a plasma CVD method, and an electrode 30 is provided on the p-type contact layer 26 by a vapor deposition method or the like, and under the substrate 10. The electrode 36 is formed on the surface. The optical semiconductor device 100 is formed by the above steps.

According to Example 1, the p-type clad layers 16 and 20 are provided on the active layer 14, and the n-type block layer 22 is provided on the p-type clad layer 20. The carrier concentration of the p-type clad layer 20 is, for example, 2 × 10 ¹⁸ cm ^-3 , which is higher than that of the p-type clad layer 16. Therefore, the energy barrier at the interface between the p-type clad layer 20 and the n-type block layer 22 becomes high (see FIG. 4A). As a result, the leakage current flowing from the active layer 14 to the n-type block layer 22 can be suppressed. Further, since the p-type clad layer 20 having a high carrier concentration has a lower resistance than the p-type clad layer 16, the series resistance of the optical semiconductor element 100 can be lowered.

The p-type dopant (Zn) may diffuse into the active layer 14, causing an increase in non-luminescent recombination centers and mixed crystal formation in multiple quantum wells. According to Example 1, the p-type clad layer 20 is provided on both sides of the p-type clad layer 16 on the active layer 14, and comes into contact with the peripheral edge of the upper surface of the active layer 14. Since the contact area between the p-type clad layer 20 and the active layer 14 is small, the diffusion of Zn is suppressed.

In the manufacturing process of the p-type clad layer 20, the flow rate of the DMZ is increased as compared with the manufacturing process of the p-type clad layer 16. Thereby, the p-type clad layer 20 having a high concentration can be formed by using the MOCVD method. For example, by setting the flow rate of the DMZ to 0.1 cm or more, the carrier concentration of the p-type clad layer 20 can be set to, for example, 2 × 10 ¹⁸ cm ^-3 .

In order to set the energy barrier between the p-type clad layer 20 and the n-type block layer 22 to, for example, 0.05 V or more, the above-mentioned relationship (1) may be established. That is, when the thickness of the p-type clad layer 20 is T, the carrier concentration is d, and n is 1.5, the relationship is as follows.
d × T ⁿ > 6.5e16 (1)
When the carrier concentration is low, the p-type clad layer 20 is thickened, and when the carrier concentration is high, the p-type clad layer 20 is thinned. The maximum carrier concentration of the p-type clad layer 20 that grows epitaxially is, for example, about 2 × 10 ¹⁸ cm ^-3 . From FIG. 4B, the relationship of the above-mentioned equation (1) is satisfied by setting the thickness to, for example, about 0.1 μm. As a result, an energy barrier of 0.05 V or higher can be formed. n may be, for example, 1 or more and 1.5 or less.

As shown in FIG. 2A, the thinner the p-type clad layer, the smaller the series resistance, but as shown in FIG. 2B, the leakage current increases. The thickness of the p-type clad layer 20 is preferably in an appropriate range in order to achieve both reduction of series resistance and suppression of leakage current. For example, as shown in FIG. 4B, the thickness is preferably 0.05 μm or more and 0.15 μm or less, and even 0.03 μm or more, 0.07 μm or more, 0.1 μm or less, 0.2 μm or less. good. Further, in order to reduce the series resistance, the thickness of the p-type clad layer 16 is preferably 0.05 μm or more and 0.15 μm or less, and may be equal to the thickness of the p-type clad layer 20.

A p-type embedded layer 18 is provided on both sides of the mesa 11 on the n-type clad layer 12. The p-type clad layer 20, the n-type block layer 22, the p-type clad layer 24, and the p-type contact layer 26 are laminated in this order on the embedded layer 18. That is, a thyristor structure is formed by arranging n-type, p-type, n-type, and p-type layers in order from the n-type clad layer 12 to the p-type contact layer 26. This enables efficient current injection into the active layer 14.

Example 2 is an example in which a manufacturing method different from that of Example 1 is used. The description of the same configuration as that of the first embodiment will be omitted. The optical semiconductor element is the same as that shown in FIGS. 5A to 6. 11 (a) and 11 (b) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the second embodiment. The steps from FIG. 7 (a) to FIG. 8 (b) are the same as those in the first embodiment.

As shown in FIG. 11A, the mask 40 is etched to expose the peripheral portion of the p-type clad layer 16 from the mask 40. By flowing the DMZ, Zn is diffused near the upper surfaces of the p-type clad layer 16 exposed from the mask 40 and the embedded layer 18. The mask 40 functions as a diffusion mask, and since the central portion of the p-type clad layer 16 is located below the mask 40, Zn is difficult to diffuse. For example, the flow rate of the DMZ is 3.4 slm, the diffusion time of Zn is 1 minute, and the temperature is 520 ° C. As a result, as shown in FIG. 11B, a region having a higher carrier concentration than the p-type clad layer 16, that is, a p-type clad layer 20, is formed on the p-type clad layer 16 and the embedded layer 18. The Zn concentration of the p-type clad layer 20 is, for example, 5 × 10 ¹⁸ cm ^-3 . The process after forming the p-type clad layer 20 is the same as that in the first embodiment.

According to the second embodiment, it is possible to reduce the series resistance and suppress the leakage current as in the first embodiment. Further, the p-type clad layer 20 is formed by the vapor phase diffusion of Zn. Therefore, the carrier concentration can be increased as compared with the epitaxially grown p-type clad layer 20.

FIG. 12 is a diagram showing the relationship between the DMZ flow rate and the carrier concentration. The horizontal axis represents the flow rate of the DMZ used for vapor phase diffusion, and the vertical axis represents the carrier concentration of the p-type clad layer 20. As shown in FIG. 12, the carrier concentration increases as the flow rate of the DMZ increases. In epitaxial growth, the maximum carrier concentration is, for example, about 2 × 10 ¹⁸ cm ^-3 , but the carrier concentration can be further increased by vapor phase diffusion. By increasing the flow rate of the DMZ, the carrier concentration can be set to, for example, 3 × 10 ¹⁸ cm ^-3 or more, 5 × 10 ¹⁸ cm ^-3 or more, and the like.

In order to set the energy barrier to 0.05 V or more, the carrier concentration and the thickness of the p-type clad layer 20 are determined so that the above-mentioned equation (1) holds. As shown in FIG. 4 (b), it is preferable to reduce the thickness as the carrier concentration increases. According to Example 2, since the carrier concentration can be, for example, 2 × 10 ¹⁸ cm ^-3 or more, the thickness is preferably 0.1 μm or less. When the carrier concentration is, for example, 5 × 10 ¹⁸ cm ^-3 , the thickness of the p-type clad layer 20 is, for example, 0.06 μm. Leakage current can be suppressed by setting the energy barrier to 0.05 V or more. Further, by thinning the p-type clad layers 16 and 20, the series resistance can be lowered.

(Optical semiconductor device)
Example 3 is an example in which the size of the p-type clad layer 20 is changed from that of Examples 1 and 2. The description of the same configuration as that of the first or second embodiment will be omitted. FIG. 13 is a cross-sectional view illustrating the optical semiconductor device 300 according to the third embodiment. As shown in FIG. 13, the p-type clad layer 20 of the optical semiconductor device 300 is provided on the peripheral edge of the upper surface of the active layer 14, and is not provided on the embedded layer 18. The embedded layer 18 is formed of, for example, iron (Fe) -doped p-type InP, and is provided on both sides of the n-type clad layer 12, the active layer 14, and the p-type clad layer 20. That is, the p-type clad layer 20 is sandwiched between the p-type clad layer 16 and the embedded layer 18. The n-type block layer 22 is provided on the p-type clad layer 16 and the embedded layer 18.

(Production method)
14 (a) to 16 (b) are cross-sectional views illustrating a method for manufacturing the optical semiconductor device 300. The steps from FIG. 7 (a) to FIG. 8 (b) are the same as in the first embodiment, but as the raw material gas of the embedded layer 18, for example, TMIn, PH ₃ , and ferrocene (Fe (C ₅ H ₅ ) ₂ ). ) Is used.

As shown in FIG. 14A, the mask 40 is etched to expose the peripheral edge portion of the upper surface of the p-type clad layer 16 from the mask 40. As shown in FIG. 14B, for example, a mask 42 of SiO ₂ is formed on the upper surface of the embedded layer 18. The mask 40 and the mask 42 are separated from each other, and the p-type clad layer 16 is exposed between them.

As shown in FIG. 15A, Zn is diffused in the p-type clad layer 16 by flowing a DMZ. For example, the flow rate of the DMZ is 3.4 slm, the diffusion time of Zn is 1 minute, and the temperature is 520 ° C. As a result, the p-type clad layer 20 having a high carrier concentration is formed from the peripheral portion of the p-type clad layer 16. The Zn concentration of the p-type clad layer 20 is, for example, 5 × 10 ¹⁸ cm ^-3 . The mesa 11 is formed by an n-type clad layer 12, an active layer 14, a p-type clad layer 16 and a p-type clad layer 20. The masks 40 and 42 function as diffusion masks, and Zn is difficult to diffuse into the p-type clad layer 16 under the mask 40 and the embedded layer 18 under the mask 42.

As shown in FIG. 15 (b), the mask 42 is removed using, for example, diluted hydrofluoric acid. As shown in FIG. 16A, the n-type block layer 22 is grown on the embedded layer 18 and the p-type clad layer 20 by, for example, the MOCVD method. As shown in FIG. 16B, after removing the mask 40, the p-type clad layer 24 and the p-type contact layer 26 are grown, for example, by the MOCVD method. Subsequent steps are the same as in the first embodiment, and the optical semiconductor device 300 is formed.

According to the third embodiment, the p-type clad layer 20 having a high carrier concentration can be formed by the vapor phase diffusion of Zn as in the second embodiment. This makes it possible to reduce the series resistance and suppress the leakage current. In order to set the energy barrier to 0.05 V or more, the carrier concentration and the thickness of the p-type clad layer 20 are determined so that the above-mentioned equation (1) holds. For example, when the carrier concentration is 5 × 10 ¹⁸ cm ^-3 or more, the thickness of the p-type clad layer 20 and the p-type clad layer 16 is, for example, 0.06 μm.

In Example 2, the p-type clad layer 20 is formed by gas-phase diffusion of Zn in the embedded layer 18 and the p-type clad layer 16. Therefore, the embedded layer 18 is formed of Zn-doped InP. On the other hand, in Example 3, the p-type clad layer 20 is formed by vapor phase diffusion of Zn in the p-type clad layer 16, and Zn is not diffused in the embedded layer 18. Therefore, as the dopant of the embedded layer 18, a dopant different from that of the p-type clad layer 20 (for example, Fe) may be used. As a result, the embedded layer 18 with high resistance is obtained. In Example 3, the embedded layer 18 may be formed with Zn-doped InP.

In Examples 1 to 3, cadmium (Cd), carbon (C), beryllium (Be) and the like may be used in addition to Zn as the dopant of the p-type clad layers 16 and 20. In Examples 1 to 3, the substrate 10 and the n-type clad layer 12 may be formed of a compound semiconductor other than InP. However, it is preferable that the substrate 10 and the n-type clad layer 12 are also formed of InP for lattice matching with the InP layer such as the embedded layer 18, the p-type clad layer 20, and the n-type block layer 22.

10 Substrate 11 Mesa 12 n-type clad layer 13, 15 Groove 14 Active layer 16, 20, 24 p-type clad layer 18 Embedded layer 22 n-type block layer 26 p-type contact layer 28 Insulation film 28a Openings 30, 31, 33 , 35, 36 Electrodes 32, 34 Wiring 40, 42 Mask 90, 100, 300 Optical semiconductor devices

Claims (3)

With a semiconductor substrate,
An n-type clad layer provided on the semiconductor substrate and an active layer provided on the n-type clad layer having a mesa structure .
A first p-type clad layer provided on the active layer and narrower than the active layer ,
A second p-type clad layer on the active layer, which is provided in contact with both side surfaces of the first p-type clad layer and has a higher carrier concentration than the first p-type clad layer.
It has a lower carrier concentration than the second p-type clad layer, which is provided extending from the side surface of the n-type clad layer and the active layer of the mesa structure to the lower surface of the second p-type clad layer. With a p-shaped embedded layer,
An n-type block layer provided on the second p-type clad layer including a region above the active layer, and an n-type block layer.
An optical semiconductor device comprising the first p-type clad layer and a third p-type clad layer provided on the n-type block layer. The optical semiconductor device according to claim 1, wherein the thickness of the second p-type clad layer is 0.05 μm or more and 0.15 μm or less. The process of forming an n-type clad layer on a semiconductor substrate and
The step of forming an active layer on the n-type clad layer and
The step of forming the first p-type clad layer on the active layer and
The step of forming a striped mask on the first p-type clad layer and
A step of forming a mesa composed of the striped n-type clad layer, the active layer, and the first p-type clad layer using the striped mask as a mask.
The step of forming a p-type embedded layer on both sides of the mesa, and
A step of retracting the striped mask by etching to expose the first p-type clad layer from the striped mask .
A step of narrowing the width of the first p-type clad layer to be narrower than that of the active layer by using the retracted mask.
Using the retracted mask, a second layer on the active layer, in contact with both sides of the first p-type clad layer, has a higher carrier concentration than the first p-type clad layer. The process of forming the p-type clad layer and
A step of forming an n-type block layer on the second p-type clad layer including a region above the active layer, and a step of forming the n-type block layer.
It has a step of forming a third p-type clad layer on the first p-type clad layer and the n-type block layer, and the carrier concentration of the p-type embedded layer is the second p. A method for manufacturing an optical semiconductor device , which is lower than the mold clad layer .

Images