JP2019071397A - Optical semiconductor device and method of manufacturing the same - Google Patents

Abstract

To provide an optical semiconductor device and a manufacturing method thereof capable of reducing series resistance and suppressing leakage current.SOLUTION: An optical semiconductor device includes a semiconductor substrate, an n-type cladding layer provided on the semiconductor substrate, an active layer provided on the n-type cladding layer, a first p-type cladding layer provided on the active layer, a second p-type cladding layer provided on the active layer on both sides of the first p-type cladding layer and having a higher carrier concentration than the first p-type cladding layer, and an n-type block layer provided on the second p-type cladding layer, and a third p-type cladding layer provided on the first p-type cladding layer and the n-type block layer.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an optical semiconductor device and a method of manufacturing the same.

  An optical semiconductor device that outputs light is used in an optical communication system and the like (Patent Document 1). In order to realize high output operation of the optical semiconductor device under a high temperature environment, it is important to reduce the series resistance of the optical semiconductor device and efficiently inject current into the active layer which is the light emitting layer. In order to increase the efficiency of current injection, for example, a thyristor structure in which semiconductor layers of n-type, p-type, n-type and p-type conductivity types are stacked may be formed in the vicinity of the active layer.

Japanese Patent Laid-Open No. 5-55696

  In order to form a thyristor structure, a clad layer is laminated on the active layer, and a block layer of a conductivity type opposite to the clad layer is provided on the clad layer. However, since the current injected into the active layer is narrowed by the block layer, the series resistance of the optical semiconductor element is increased. In addition, there is a possibility that a leak current may occur between the active layer and the block layer.

  Therefore, it is an object of the present invention to provide an optical semiconductor device capable of reducing series resistance and suppressing leakage current, and a method of manufacturing the same.

  An optical semiconductor device according to the present invention is provided on a semiconductor substrate, an n-type cladding layer provided on the semiconductor substrate, an active layer provided on the n-type cladding layer, and the active layer. A second p-type cladding layer, and a second carrier layer provided on the active layer and on both sides of the first p-type cladding layer and having a higher carrier concentration than the first p-type cladding layer A p-type cladding layer, an n-type block layer provided on the second p-type cladding layer, a third p-type cladding layer provided on the first p-type cladding layer and the n-type block layer and a p-type cladding layer.

  A method of manufacturing an optical semiconductor device according to the present invention comprises the steps of: forming an n-type cladding layer on a semiconductor substrate; forming an active layer on the n-type cladding layer; Forming a stripe-like mask on the first p-type cladding layer; forming a stripe-like mesa using the stripe-like mask as a mask; Etching back the mask by etching, and using the recessed mask, carriers higher than the first p-type cladding layer on the active layer and on both sides of the first p-type cladding layer Forming a second p-type cladding layer having a concentration, forming an n-type block layer on the second p-type cladding layer, the first p-type cladding layer and the n-type block Third on the layer Forming a p-type cladding layer, and has a.

  According to the above invention, it is possible to reduce the series resistance and suppress the leak current.

FIG. 1 is a cross-sectional view illustrating an optical semiconductor device used for simulation. FIG. 2A shows the calculation result of the series resistance of the optical semiconductor device. FIG. 2 (b) is an experimental result of the drive current. FIG. 3A shows the calculation result of the potential of the conduction band. FIG. 3 (b) shows the calculation result of the energy barrier. FIG. 4A shows the relationship between carrier concentration and energy barrier. FIG. 4B is a view showing the relationship between the thickness and the carrier concentration. FIG. 5A is a plan view illustrating the optical semiconductor device according to the first embodiment. FIG. 5 (b) is a cross-sectional view taken along line A-A of FIG. 5 (a). FIG. 6 is an enlarged sectional view of the vicinity of the mesa. FIG. 7A and FIG. 7B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 8A and FIG. 8B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 9A and FIG. 9B are cross-sectional views illustrating a method of manufacturing an optical semiconductor device. FIG. 10A and FIG. 10B are cross-sectional views illustrating a method of manufacturing an optical semiconductor device. 11A and 11B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the second embodiment. FIG. 12 is a diagram showing the relationship between the DMZ flow rate and the carrier concentration. FIG. 13 is a cross-sectional view illustrating an optical semiconductor device according to the third embodiment. FIG. 14A to FIG. 14B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 15A to FIG. 15B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. 16 (a) to 16 (b) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device.

Description of an embodiment of the present invention
First, the contents of the embodiment of the present invention will be listed and described.
One embodiment of the present invention comprises: (1) a semiconductor substrate, an n-type cladding layer provided on the semiconductor substrate, an active layer provided on the n-type cladding layer, and the active layer A first p-type cladding layer provided, and provided on both sides of the first p-type cladding layer above the active layer and having a carrier concentration higher than that of the first p-type cladding layer No. 2 p-type cladding layer, an n-type block layer provided on the second p-type cladding layer, and a third provided on the first p-type cladding layer and the n-type block layer An optical semiconductor element comprising the p-type cladding layer of Since the carrier concentration of the second p-type cladding layer is high, the series resistance can be reduced, and the leak current flowing from the active layer to the n-type block layer can be suppressed.
(2) The thickness of the second p-type cladding layer may be 0.05 μm or more and 0.15 μm or less. Thereby, the series resistance of the optical semiconductor device can be reduced.
(3) The n-type cladding layer and the active layer form a mesa, and include a p-type buried layer provided on the n-type cladding layer and on both sides of the mesa. A second p-type cladding layer may be provided on the active layer and the buried layer. Thereby, series resistance can be reduced and leakage current can be suppressed.
(4) The n-type cladding layer and the active layer form a mesa, and include embedded layers provided on both sides of the mesa, and the second p-type cladding layer is provided on the active layer And may not be provided on the buried layer. Thereby, series resistance can be reduced and leakage current can be suppressed.
(5) The present invention comprises the steps of forming an n-type cladding layer on a semiconductor substrate, forming an active layer on the n-type cladding layer, and forming a first p-type cladding on the active layer. Forming a layer, forming a stripe-like mask on the first p-type cladding layer, forming a stripe-like mesa using the stripe-like mask as a mask, and retreating the mask by etching A second step having a higher carrier concentration than the first p-type cladding layer on the active layer and on both sides of the first p-type cladding layer using the retreated mask Forming a p-type cladding layer, forming an n-type block layer on the second p-type cladding layer, and forming a second p-type cladding layer on the first p-type cladding layer and the n-type block layer. Form 3 p-type cladding layers And that step is a method for manufacturing an optical semiconductor device having a. Since the carrier concentration of the second p-type cladding layer is high, the series resistance can be reduced, and the leak current flowing from the active layer to the n-type block layer can be suppressed.
(6) In the step of forming the second p-type cladding layer, the step of etching the first p-type cladding layer using the receded mask, and the step of etching the first p-type cladding layer And forming a second p-type cladding layer by MOCVD after the step. The second p-type cladding layer can be formed by the MOCVD method.
(7) The step of forming the second p-type cladding layer is also a step of forming the second p-type cladding layer by vapor phase diffusing the dopant into a part of the first p-type cladding layer Good. Thereby, the second p-type cladding layer with high carrier concentration can be formed.
(8) forming a second p-type cladding layer, comprising: forming a p-type embedded layer on both sides of the mesa; and forming another mask on the embedded layer The step of depositing may be a step of vapor phase diffusing the dopant into a portion of the first p-type cladding layer exposed from the recessed mask and the other mask. Thereby, the second p-type cladding layer with high carrier concentration can be formed.

[Details of the Embodiment of the Present Invention]
Specific examples of an optical semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to these exemplifications, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

(simulation)
First, a simulation verifying the series resistance and the leak current of the optical semiconductor device will be described. FIG. 1 is a cross-sectional view of an optical semiconductor device 90 used for the simulation.

  As shown in FIG. 1, an n-type cladding layer 12, an active layer 14 and a p-type cladding layer 16 are stacked on a substrate 10, and these form a mesa 11. Buried layers 18 are provided on the n-type cladding layer 12 and on both sides of the mesa 11. An n-type block layer 22 is provided from the peripheral portion of the upper surface of the p-type cladding layer 16 to the upper surface of the buried layer 18. A p-type cladding layer 24 is provided on the central portion of the p-type cladding layer 16 and the n-type block layer 22, and a p-type contact layer 26 is provided on the p-type cladding layer 24. A thyristor structure in which layers of n-type, p-type, n-type and p-type conductivity types are stacked is formed from the substrate 10 to the p-type contact layer 26. An insulating film 28 and an electrode 30 are provided on the p-type contact layer 26. An electrode 36 is provided on the lower surface of the substrate 10.

  The substrate 10 and the n-type cladding layer 12 are formed of n-type indium phosphide (InP) doped with silicon (Si). The active layer 14 has a multiple quantum well (MQW: Multi Quantum Well) structure in which a plurality of zinc (Zn) -doped indium gallium arsenide phosphide (InGaAsP) layers are stacked. The p-type cladding layers 16 and 24 and the buried layer 18 are formed of p-type InP doped with Zn. The n-type block layer 22 is formed of n-type InP. The p-type contact layer 26 is formed of Zn-doped p-type InGaAs. The insulating film 28 is formed of silicon nitride (SiN). The electrodes 30 and 36 are formed of gold (Au) or the like.

FIG. 2A shows the calculation result of the series resistance of the optical semiconductor device 90. FIG. The abscissa represents the thickness of the p-type cladding layer 16 and the ordinate represents the series resistance. As the carrier concentration of the p-type cladding layer 16 is higher, the electrical resistance of the p-type cladding layer 16 is lower, and the series resistance of the optical semiconductor device 90 is also lower. In the simulation of FIG. 2A, the carrier concentration is constant at 1.8 × 10 ¹⁸ cm ⁻³ . The thickness of the n-type block layer 22 is 0.15 μm, the width of the active layer 14 is 1.25 μm, and the resonator length is 150 μm. As shown in FIG. 2A, the series resistance decreases as the p-type cladding layer 16 becomes thinner. Current is injected into the active layer 14 through the p-type cladding layers 24 and 16. It is presumed that the series resistance is increased by the n-type blocking layer 22 constricting the current. When the p-type cladding layer 16 becomes thinner, it is considered that the distance in which the narrowed current flows becomes short, and the increase in series resistance is suppressed. That is, in order to reduce the series resistance, it is effective to make the p-type cladding layer 16 thinner. However, the leak current may increase.

  FIG. 2 (b) is an experimental result of the drive current. The horizontal axis represents the temperature of the optical semiconductor device 90. The vertical axis represents drive current for producing an optical output of 16 mW. The larger the drive current, the larger the leak current flowing from the active layer 14 to the n-type block layer 22 via the p-type cladding layer 16. The squares in the figure represent the experimental results when the thickness of the p-type cladding layer 16 is 0.05 μm, the triangles represent the experimental results when the thickness is 0.07 μm, and the circles represent the experimental results when the thickness is 0.1 μm. . As shown in FIG. 2B, as the temperature rises, the drive current increases, and as the p-type cladding layer 16 becomes thinner, the drive current increases.

  As described above, the series resistance can be lowered by thinning the p-type cladding layer 16, but the leakage current will increase. In order to suppress the leakage current, it is preferable that a large energy barrier be formed in the conduction band. The simulation of the energy barrier will be described below.

FIG. 3A shows the calculation result of the potential of the conduction band. The horizontal axis represents the depth from the surface of the p-type contact layer 26, and the vertical axis represents the potential of the conduction band of the optical semiconductor device 90. The solid line is the calculation result when the thickness of the p-type cladding layer 16 is 0.5 μm, and the broken line is the calculation result when the thickness is 0.1 μm. The carrier concentration was 5 × 10 ¹⁷ cm ⁻³ . As shown in FIG. 3A, energy barriers b1 and b2 are formed at the interface of the np junction (the interface between the p-type cladding layer 16 and the n-type block layer 22) in the conduction band. The energy barrier b1 at a thickness of 0.5 μm is about 0.2 V, which is larger than the energy barrier b2 at a thickness of 0.1 μm.

FIG. 3 (b) shows the calculation result of the energy barrier. The horizontal axis represents the thickness of the p-type cladding layer 16, and the vertical axis represents the energy barrier at the interface between the p-type cladding layer 16 and the n-type block layer 22. The carrier concentration of the p-type cladding layer 16 is 5 × 10 ¹⁷ cm ⁻³ . As shown in FIG. 3 (b), the thinner the p-type cladding layer 16, the smaller the energy barrier. For example, if the thickness is 0.1 μm, the energy barrier is 0.008V.

  The smaller the thickness, the smaller the energy barrier as shown in FIGS. 4A and 4B, and the larger the leakage current as shown in FIG. 2B. That is, if the energy barrier is low, the leakage current will increase. Therefore, in order to reduce the leakage current, it is effective to raise the energy barrier.

FIG. 4A shows the relationship between carrier concentration and energy barrier. The horizontal axis represents the carrier concentration of the p-type cladding layer 16, and the vertical axis represents the energy barrier. Circles indicate calculation results when the thickness of the p-type cladding layer 16 is 0.1 μm, triangles indicate calculation results when the thickness is 0.08 μm, squares indicate calculation results when the thickness is 0.06 μm, and diamonds have thickness The calculation result in the case of 0.04 μm is shown. The higher the carrier concentration at any thickness, the greater the energy barrier. For example, by setting the carrier concentration to 1 × 10 ¹⁹ cm ⁻³ at a thickness of 0.04 μm, the size of the energy barrier can be approximately 0.07 V.

FIG. 4 (b) shows the relationship between thickness and carrier concentration, showing the thickness and carrier concentration adjusted to make the energy barrier 0.05V. The horizontal axis represents the thickness of the p-type cladding layer 16 and the vertical axis represents the carrier concentration of the p-type cladding layer 16. The solid line in the figure represents the relationship between thickness and carrier concentration such that the energy barrier is 0.05 V. As shown in FIG. 4B, as the p-type cladding layer 16 is made thinner, the carrier concentration is increased. Thereby, the height of the energy barrier can be maintained at 0.05V. For example, when the thickness is 0.1 μm, the carrier concentration is about 2 × 10 ¹⁸ cm ⁻³ . When the thickness is 0.06 μm, the carrier concentration is about 5 × 10 ¹⁸ cm ⁻³ . From the results of FIG. 4B, in order to set the energy barrier to 0.05 V or more, the following equation (1) may be established. T is the thickness of the p-type cladding layer 16, d is the carrier concentration, and n is 1.5.
d × T ⁿ > 6.5e16 (1)

  The series resistance can be lowered by thinning the p-type cladding layer 16 as shown in FIG. Further, as shown in FIGS. 4A and 4B, by increasing the carrier concentration, the energy barrier can be increased and the leakage current can be suppressed. An embodiment based on the above findings will be described.

(Optical semiconductor device)
FIG. 5A is a plan view illustrating the optical semiconductor device 100 according to the first embodiment. FIG. 5 (b) is a cross-sectional view taken along line A-A of FIG. 5 (a). FIG. 6 is an enlarged sectional view of the vicinity of the mesa 11. The X, Y and Z directions are orthogonal to one another.

  As shown in FIG. 5A, the optical semiconductor device 100 is a rectangular semiconductor laser device extending in the XY plane. The length L1 in the X direction and the length L2 in the Y direction are, for example, 200 μm to 500 μm.

  As shown in FIG. 5B, an n-type cladding layer 12 is provided on a substrate 10 (semiconductor substrate), and grooves 13 and 15 are formed in the n-type cladding layer 12. The mesa 11 is formed between the groove 13 and the groove 15. The configuration in the vicinity of the mesa 11 will be described later. The buried layer 18, the p-type cladding layer 20, and the n-type block layer 22 are formed on the n-type cladding layer 12 in the regions from the groove 13 to the −X side end and from the groove 15 to the + X side end. The p-type cladding layer 24, the p-type contact layer 26, and the insulating film 28 are sequentially stacked. The insulating film 28 covers the surface of the optical semiconductor element 100 and has an opening in the groove 13 and on the mesa 11.

  An electrode 31 in contact with the n-type cladding layer 12 is provided in the groove 13. A wire 32 is provided on the insulating film 28 from the groove 13 to the p-type contact layer 26 on the −X side. The electrode 33 contacts the top surface of the wiring 32. The wiring 32 contacts the electrode 31 in the groove 13. A wire 34 is provided on the insulating film 28 from the mesa 11 to the + X-side p-type contact layer 26. The electrode 35 contacts the top surface of the wiring 34. The wiring 34 contacts the electrode 30 on the mesa 11. The wiring 32 and the wiring 34 are separated. The wiring 32, the electrodes 31 and 33 are electrically connected to each other. Wiring 34 and electrodes 30 and 35 are electrically connected to each other.

  As shown in FIG. 5B, the mesa 11 is located between the grooves 13 and 15, and the mesa 11 extends in the Y direction. As shown in FIG. 6, the n-type cladding layer 12, the active layer 14 and the p-type cladding layer 16 form a stripe-shaped mesa 11. The n-type cladding layer 12 has a convex shape, and the active layer 14 is in contact with the upper surface of the n-type cladding layer 12. The p-type cladding layer 16 (first p-type cladding layer) is in contact with the central portion of the upper surface of the active layer 14. The buried layers 18 are located on both sides of the mesa 11 and are in contact with the side surfaces of the n-type cladding layer 12 and the active layer 14. A p-type cladding layer 20 (second p-type cladding layer) is provided from the top of the buried layer 18 to the peripheral portion of the top surface of the active layer 14. The n-type block layer 22 is provided on the p-type cladding layer 20 and is not provided on the p-type cladding layer 16. The p-type cladding layer 20 is in contact with the upper surfaces of the buried layer 18 and the active layer 14, and the n-type blocking layer 22 is in contact with the upper surface of the p-type cladding layer 20.

  The p-type cladding layer 24 (third p-type cladding layer) is provided on the p-type cladding layer 16 and the n-type block layer 22 and is in contact with the upper surface thereof. A p-type contact layer 26 and an insulating film 28 are sequentially stacked on the p-type cladding layer 24. The insulating film 28 has an opening 28 a on the mesa 11. The electrode 30 contacts the p-type contact layer 26 exposed from the opening 28a. An electrode 36 is in contact with the lower surface of the substrate 10. For example, a modulation signal and a bias current are supplied to the electrode 30 via the electrode 35 and the wiring 34 shown in FIG. 5B. The electrode 30 functions as an electrode for supplying a current to the active layer 14.

The substrate 10 and the n-type cladding layer 12 are formed of, for example, n-type InP doped with silicon (Si), and the carrier concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ . The active layer 14 has a multiple quantum well structure in which a plurality of Zn-doped InGaAsP layers are stacked, and generates light by carrier recombination. The p-type cladding layers 16 and 24 and the buried layer 18 are formed of, for example, Zn-doped p-type InP. The thickness of the p-type cladding layer 16 is, for example, 0.1 μm, and the thickness of the p-type cladding layer 24 is, for example, 1.5 μm. The carrier concentration of the p-type cladding layers 16 and 24 is 5 × 10 ¹⁷ cm ⁻³ , for example.

The p-type cladding layer 20 is formed of, for example, p-type InP doped with Zn. The thickness is, for example, 0.1 μm, which is equal to the thickness of the p-type cladding layer 16. The carrier concentration of the p-type cladding layer 20 is higher than that of the buried layer 18 and the p-type cladding layers 16 and 24 and is, for example, 2 × 10 ¹⁸ cm ⁻³ . The n-type block layer 22 is formed of, for example, n-type InP doped with Si, and has a carrier concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of 0.3 μm. The p-type contact layer 26 is formed of Zn-doped p-type InGaAs and has a thickness of, for example, 0.1 μm. A thyristor structure in which layers of n-type, p-type, n-type and p-type conductivity types are stacked is formed from the substrate 10 to the p-type contact layer 26 on both sides of the mesa 11. The insulating film 28 is formed of, for example, an insulator such as SiN. The electrodes 30 and 36 are formed of a metal such as Au.

(Production method)
FIG. 7A to FIG. 10B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device 100, and a portion corresponding to FIG. 6 is illustrated. The other parts of the optical semiconductor device 100 are also formed by the same process.

As shown in FIG. 7A, the n-type cladding layer 12, the active layer 14, and the p-type cladding layer 16 are formed on the substrate 10 by metal organic chemical vapor deposition (MOCVD: Metal Oxide Chemical Vapor Deposition), for example. Are epitaxially grown in order. The thickness of the p-type cladding layer 16 is, for example, 0.1 μm. The temperature (growth temperature) in the MOCVD apparatus is, for example, 620 ° C., and the growth pressure is, for example, 0.1 atm. The source gas of the n-type cladding layer 12 contains, for example, trimethyl indium (TMIn: Trimethyl Indium), phosphine (PH ₃ ) and silane (SiH ₄ ). The source gas of the active layer 14 includes, for example, TMIn, Triethyl Gallium (TEGa), PH ₃ and Arsine (AsH ₃ ). source gas of the p-type cladding layer 16 includes, for example, TMIn, a PH ₃ and DMZ. The flow rate of DMZ, which is a dopant source gas, is, for example, 0.02 ccm and less than 0.1 ccm. A stripe-shaped silicon oxide (SiO ₂ ) mask 40 is formed on the top surface of the p-type cladding layer 16. The mask 40 covers a portion of the p-type cladding layer 16.

  As shown in FIG. 7B, the p-type cladding layer 16, the active layer 14, and the n-type cladding layer 12 are etched by dry etching, for example, to form a mesa 11. The etching depth is, for example, 1.5 μm. The portion under the mask 40 is not etched.

As shown in FIG. 8A, a buried layer 18 of p-type InP is grown on both sides of the mesa 11 by using, for example, the MOCVD method. Source gas include, for example, TMIn, PH ₃ and DMZ and the like. The buried layer 18 is not grown under the mask 40 because the mask 40 functions as a growth mask. As shown in FIG. 8B, the mask 40 is etched using, for example, diluted hydrofluoric acid or the like, and is retracted. The width and height of the mask 40 are reduced, and the peripheral portion of the upper surface of the p-type cladding layer 16 is exposed from the mask 40.

As shown in FIG. 9A, the p-type cladding layer 16 and the buried layer 18 are etched using, for example, diluted oxalic acid. Thus, the peripheral portion of the p-type cladding layer 16 is removed to expose the active layer 14. Also, the buried layer 18 is etched to the same height as the active layer 14. The portion of the p-type cladding layer 16 under the mask 40 is not etched, and the p-type cladding layer 16 remains on the central portion of the upper surface of the active layer 14. As shown in FIG. 9B, the p-type cladding layer 20 of p-type InP is grown by the MOCVD method using a mask 40, for example. Source gas include, for example, TMIn, PH ₃ and DMZ etc., DMZ flow is for example 0.1ccm more. The carrier concentration of the p-type cladding layer 20 is, for example, 2 × 10 ¹⁸ cm ⁻³ . The p-type cladding layer 20 is provided from the portion of the top surface of the active layer 14 exposed from the mask 40 to the top surface of the buried layer 18 and is in contact with these. The thickness of the p-type cladding layer 20 is, for example, 0.1 μm similar to that of the p-type cladding layer 16.

As shown in FIG. 10A, an n-type block layer 22 of n-type InP is grown on the p-type cladding layer 20 by the MOCVD method using a mask 40, for example. The source gas includes, for example, TMIn, PH ₃ , and SiH ₄ . As shown in FIG. 10 (b), the mask 40 is removed, for example, by immersion in hydrofluoric acid for 1 minute. After removing the mask 40, the p-type cladding layer 24 and the p-type contact layer 26 are sequentially grown on the p-type cladding layer 16 and the n-type block layer 22 by MOCVD. The source gas of the p-type cladding layer 24 includes, for example, TMIn, PH ₃ , and DMZ. The source gas of the p-type contact layer 26 includes, for example, TMIn, TEGa, AsH ₃ and DMZ. As shown in FIG. 6, an insulating film 28 is formed on the p-type contact layer 26 by plasma CVD, for example, and the electrode 30 is provided on the p-type contact layer 26 by evaporation or the like. To form an electrode 36. The optical semiconductor element 100 is formed by the above steps.

According to the first embodiment, the p-type cladding layers 16 and 20 are provided on the active layer 14, and the n-type block layer 22 is provided on the p-type cladding layer 20. The carrier concentration of the p-type cladding layer 20 is, for example, 2 × 10 ¹⁸ cm ⁻³ and is higher than that of the p-type cladding layer 16. Therefore, the energy barrier at the interface between the p-type cladding layer 20 and the n-type block layer 22 becomes high (see FIG. 4A). As a result, the leak current flowing from the active layer 14 to the n-type block layer 22 can be suppressed. Further, since the high carrier concentration p-type cladding layer 20 has lower resistance than the p-type cladding layer 16, the series resistance of the optical semiconductor device 100 can be reduced.

  The p-type dopant (Zn) may diffuse into the active layer 14 and cause an increase in non-radiative recombination centers, and mixed crystallization of multiple quantum wells. According to the first embodiment, the p-type cladding layer 20 is provided on the active layer 14 and on both sides of the p-type cladding layer 16 and is in contact with the peripheral portion of the upper surface of the active layer 14. Since the contact area between the p-type cladding layer 20 and the active layer 14 is small, the diffusion of Zn is suppressed.

In the manufacturing process of the p-type cladding layer 20, the flow rate of DMZ is made larger than in the manufacturing process of the p-type cladding layer 16. Thereby, the high concentration p-type cladding layer 20 can be formed using the MOCVD method. For example, by setting the flow rate of DMZ to 0.1 ccm or more, the carrier concentration of the p-type cladding layer 20 can be set to 2 × 10 ¹⁸ cm ⁻³ , for example.

In order to set the energy barrier between the p-type cladding layer 20 and the n-type block layer 22 to, for example, 0.05 V or more, the relationship of the above-mentioned equation (1) may be established. That is, when the thickness of the p-type cladding layer 20 is T, the carrier concentration is d, and n is 1.5, the following relationship is established.
d × T ⁿ > 6.5e16 (1)
When the carrier concentration is low, the p-type cladding layer 20 is thickened, and when the carrier concentration is high, the p-type cladding layer 20 is thin. The carrier concentration of the epitaxially grown p-type cladding layer 20 is, for example, about 2 × 10 ¹⁸ cm ⁻³ at the maximum. From FIG. 4B, the relationship of the above-mentioned equation (1) is satisfied by setting the thickness to, for example, about 0.1 μm. As a result, an energy barrier of 0.05 V or more can be formed. n may be, for example, 1 or more and 1.5 or less.

  As shown in FIG. 2A, the series resistance decreases as the p-type cladding layer becomes thinner, but the leakage current increases as shown in FIG. 2B. The thickness of the p-type cladding layer 20 is preferably in an appropriate range in order to achieve both reduction in series resistance and suppression of leakage current. For example, as shown in FIG. 4B, the thickness is preferably 0.05 μm or more and 0.15 μm or less, and is preferably 0.03 μm or more, 0.07 μm or more, 0.1 μm or less, and 0.2 μm or less Good. Further, in order to reduce series resistance, the thickness of the p-type cladding layer 16 is also preferably 0.05 μm or more and 0.15 μm or less, for example, and may be equal to the thickness of the p-type cladding layer 20.

  A p-type buried layer 18 is provided on the n-type cladding layer 12 and on both sides of the mesa 11. The p-type cladding layer 20, the n-type block layer 22, the p-type cladding layer 24, and the p-type contact layer 26 are sequentially stacked on the buried layer 18. That is, a thyristor structure is formed by sequentially arranging n-type, p-type, n-type and p-type layers from the n-type cladding layer 12 to the p-type contact layer 26. This enables efficient current injection to the active layer 14.

  The second embodiment is an example using a manufacturing method different from that of the first embodiment. The description of the same configuration as that of the first embodiment is omitted. The optical semiconductor device is the same as that shown in FIG. 5 (a) to FIG. 11A and 11B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the second embodiment. The steps from FIG. 7 (a) to FIG. 8 (b) are the same as in the first embodiment.

As shown in FIG. 11A, the mask 40 is etched to expose the peripheral portion of the p-type cladding layer 16 from the mask 40. By flowing DMZ, Zn is diffused in the vicinity of the upper surface of the p-type cladding layer 16 exposed from the mask 40 and the buried layer 18. The mask 40 functions as a diffusion mask, and Zn is less likely to diffuse since the central portion of the p-type cladding layer 16 is located below the mask 40. For example, the flow rate of DMZ is 3.4 slm, the diffusion time of Zn is 1 minute, and the temperature is 520.degree. As a result, as shown in FIG. 11B, a region of higher carrier concentration than the p-type cladding layer 16, ie, the p-type cladding layer 20 is formed on the p-type cladding layer 16 and the buried layer 18. The Zn concentration of the p-type cladding layer 20 is 5 × 10 ¹⁸ cm ⁻³ , for example. The steps after forming the p-type cladding layer 20 are the same as in the first embodiment.

  According to the second embodiment, as in the first embodiment, the series resistance can be reduced and the leakage current can be suppressed. The p-type cladding layer 20 is formed by vapor phase diffusion of Zn. Therefore, the carrier concentration can be increased compared to the epitaxially grown p-type cladding layer 20.

FIG. 12 is a diagram showing the relationship between the DMZ flow rate and the carrier concentration. The horizontal axis represents the flow rate of DMZ used for gas phase diffusion, and the vertical axis represents the carrier concentration of the p-type cladding layer 20. As shown in FIG. 12, the carrier concentration increases as the flow rate of DMZ increases. In epitaxial growth, the carrier concentration is at most, for example, about 2 × 10 ¹⁸ cm ⁻³ , but the carrier concentration can be further increased by gas phase diffusion. By increasing the flow rate of DMZ, the carrier concentration can be, for example, 3 × 10 ¹⁸ cm ⁻³ or more, 5 × 10 ¹⁸ cm ⁻³ or more.

In order to set the energy barrier to 0.05 V or more, the carrier concentration and thickness of the p-type cladding layer 20 are determined so that the aforementioned equation (1) holds. As shown in FIG. 4 (b), it is preferable to reduce the thickness as the carrier concentration is higher. According to the second embodiment, the carrier concentration can be, for example, 2 × 10 ¹⁸ cm ⁻³ or more, so the thickness is preferably 0.1 μm or less. When the carrier concentration is, eg, 5 × 10 ¹⁸ cm ⁻³ , the thickness of the p-type cladding layer 20 is, eg, 0.06 μm. Leakage current can be suppressed by setting the energy barrier to 0.05 V or more. Further, by thinning the p-type cladding layers 16 and 20, the series resistance can be lowered.

(Optical semiconductor device)
The third embodiment is an example in which the size of the p-type cladding layer 20 is changed in the first and second embodiments. The description of the same configuration as that of Embodiment 1 or 2 is omitted. FIG. 13 is a cross-sectional view illustrating an optical semiconductor device 300 according to the third embodiment. As shown in FIG. 13, the p-type cladding layer 20 of the optical semiconductor device 300 is provided on the periphery of the top surface of the active layer 14 and is not provided on the embedded layer 18. The buried layer 18 is made of, for example, p-type InP doped with iron (Fe), and is provided on both sides of the n-type cladding layer 12, the active layer 14, and the p-type cladding layer 20. That is, the p-type cladding layer 20 is sandwiched between the p-type cladding layer 16 and the embedded layer 18. The n-type block layer 22 is provided on the p-type cladding layer 16 and the buried layer 18.

(Production method)
FIG. 14A to FIG. 16B are cross-sectional views illustrating the method for manufacturing the optical semiconductor device 300. The steps from FIG. 7 (a) to FIG. 8 (b) are the same as in Example 1, but as source gases for the buried layer 18, for example, TMIn, PH ₃ and ferrocene (Fe (C ₅ H ₅ ) ₂ Use).

As shown in FIG. 14A, the mask 40 is etched to expose the peripheral portion of the upper surface of the p-type cladding layer 16 from the mask 40. As shown in FIG. 14B, a mask 42 of, eg, SiO ₂ is formed on the upper surface of the buried layer 18. The mask 40 and the mask 42 are spaced apart, and the p-type cladding layer 16 is exposed between them.

As shown in FIG. 15A, Zn is diffused in the p-type cladding layer 16 by flowing DMZ. For example, the flow rate of DMZ is 3.4 slm, the diffusion time of Zn is 1 minute, and the temperature is 520.degree. Thus, the p-type cladding layer 20 having a high carrier concentration is formed from the peripheral portion of the p-type cladding layer 16. The Zn concentration of the p-type cladding layer 20 is 5 × 10 ¹⁸ cm ⁻³ , for example. The mesa 11 is formed of an n-type cladding layer 12, an active layer 14, a p-type cladding layer 16 and a p-type cladding layer 20. The masks 40 and 42 function as diffusion masks, and Zn does not easily diffuse into the p-type cladding layer 16 under the mask 40 and the embedded layer 18 under the mask 42.

  As shown in FIG. 15B, the mask 42 is removed using, for example, diluted hydrofluoric acid. As shown in FIG. 16A, an n-type block layer 22 is grown on the buried layer 18 and the p-type cladding layer 20 by MOCVD, for example. As shown in FIG. 16B, after removing the mask 40, the p-type cladding layer 24 and the p-type contact layer 26 are grown by, eg, MOCVD. The subsequent steps are the same as in the first embodiment, and the optical semiconductor device 300 is formed.

According to the third embodiment, as in the second embodiment, the p-type cladding layer 20 having a high carrier concentration can be formed by vapor phase diffusion of Zn. This makes it possible to reduce series resistance and suppress leakage current. In order to set the energy barrier to 0.05 V or more, the carrier concentration and thickness of the p-type cladding layer 20 are determined so that the aforementioned equation (1) holds. For example, when the carrier concentration is 5 × 10 ¹⁸ cm ⁻³ or more, the thicknesses of the p-type cladding layer 20 and the p-type cladding layer 16 are set to, for example, 0.06 μm.

  In the second embodiment, Zn is vapor-phase diffused into the buried layer 18 and the p-type cladding layer 16 to form the p-type cladding layer 20. Therefore, the buried layer 18 is formed of Zn-doped InP. On the other hand, in the third embodiment, the p-type cladding layer 20 is formed by vapor phase diffusion of Zn into the p-type cladding layer 16 and does not diffuse Zn into the buried layer 18. Therefore, as the dopant of the buried layer 18, one different from the p-type cladding layer 20 (for example, Fe) may be used. Thereby, a high resistance embedded layer 18 is obtained. Also in the third embodiment, the buried layer 18 may be formed of Zn-doped InP.

  In Examples 1 to 3, cadmium (Cd), carbon (C), beryllium (Be) or the like may be used as the dopant for the p-type cladding layers 16 and 20 in addition to Zn. In Examples 1 to 3, the substrate 10 and the n-type cladding layer 12 may be formed of a compound semiconductor other than InP. However, for lattice matching with layers of InP such as the buried layer 18, the p-type cladding layer 20, and the n-type block layer 22, the substrate 10 and the n-type cladding layer 12 are also preferably made of InP.

DESCRIPTION OF SYMBOLS 10 substrate 11 mesa 12 n-type cladding layer 13, 15 groove | channel 14 active layer 16, 20, 24 p-type cladding layer 18 embedded layer 22 n-type block layer 26 p-type contact layer 28 insulating film 28a opening part 30, 31, 33 , 35, 36 electrode 32, 34 wiring 40, 42 mask 90, 100, 300 optical semiconductor device

Claims (8)

A semiconductor substrate,
An n-type cladding layer provided on the semiconductor substrate;
An active layer provided on the n-type cladding layer,
A first p-type cladding layer provided on the active layer;
A second p-type cladding layer provided on the active layer on both sides of the first p-type cladding layer and having a higher carrier concentration than the first p-type cladding layer;
An n-type block layer provided on the second p-type cladding layer;
An optical semiconductor device comprising: the first p-type cladding layer; and a third p-type cladding layer provided on the n-type block layer.   The optical semiconductor device according to claim 1, wherein a thickness of the second p-type cladding layer is 0.05 μm or more and 0.15 μm or less. The n-type cladding layer and the active layer form a mesa,
A p-type buried layer provided on the n-type cladding layer and on both sides of the mesa;
The optical semiconductor device according to claim 1, wherein the second p-type cladding layer is provided on the active layer and the embedded layer. The n-type cladding layer and the active layer form a mesa,
Comprising buried layers provided on both sides of the mesa,
The optical semiconductor device according to claim 1, wherein the second p-type cladding layer is provided on the active layer and not provided on the embedded layer. Forming an n-type cladding layer on the semiconductor substrate;
Forming an active layer on the n-type cladding layer;
Forming a first p-type cladding layer on the active layer;
Forming a stripe-like mask on the first p-type cladding layer;
Forming a stripe-shaped mesa using the stripe-shaped mask as a mask;
Retracting the mask by etching;
A second p-type cladding having a higher carrier concentration than the first p-type cladding layer on the active layer and on both sides of the first p-type cladding layer using the recessed mask Forming a layer;
Forming an n-type block layer on the second p-type cladding layer;
Forming a third p-type cladding layer on the first p-type cladding layer and the n-type block layer.   In the step of forming the second p-type cladding layer, a step of etching the first p-type cladding layer using the receded mask and a step of etching the first p-type cladding layer The method of manufacturing an optical semiconductor device according to claim 5, comprising the step of forming the second p-type cladding layer by MOCVD.   The step of forming the second p-type cladding layer is a step of forming the second p-type cladding layer by vapor phase diffusing a dopant into a part of the first p-type cladding layer. 5. The manufacturing method of the optical semiconductor element as described in 5. Forming p-type buried layers on both sides of the mesa;
Forming another mask on the buried layer;
The step of forming the second p-type cladding layer is a step of vapor-phase diffusing the dopant in a portion of the first p-type cladding layer exposed from the recessed mask and the other mask. Item 8. A method for producing an optical semiconductor device according to item 7.

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