JP2000077670A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JP2000077670A
JP2000077670A JP10250131A JP25013198A JP2000077670A JP 2000077670 A JP2000077670 A JP 2000077670A JP 10250131 A JP10250131 A JP 10250131A JP 25013198 A JP25013198 A JP 25013198A JP 2000077670 A JP2000077670 A JP 2000077670A
Authority
JP
Japan
Prior art keywords
film
oxide film
heat treatment
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10250131A
Other languages
Japanese (ja)
Other versions
JP3648998B2 (en
Inventor
Mitsutoshi Miyasaka
光敏 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25013198A priority Critical patent/JP3648998B2/en
Publication of JP2000077670A publication Critical patent/JP2000077670A/en
Application granted granted Critical
Publication of JP3648998B2 publication Critical patent/JP3648998B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To reform an oxide film and the interface between the oxide film and a semiconductor film to a high-quality film and a interface, by performing a first heat treatment on the oxide film in an oxidizing atmosphere and a second heat treatment on the semiconductor film and oxide film, and bonding hydrogen to the unpaired bonding pair held by the semiconductor film. SOLUTION: After a silicon oxide film 104 is formed, a first heat treatment is performed on the film 104 in an oxidizing atmosphere. Then the film 104 is dried through a second heat treatment. After the film 104 is dried, a substrate 101 is immediately introduced to a parallel plate capacitively coupled plasma chemical vapor deposition(PECVD) device and irradiated with light emitted from the hydrogen plasma. Thus, the deposition of a gate insulating film and the reformation of the oxide film 104 and the interface between the oxide film 104 and a semiconductor film are completed. Successively, a gate electrode 105 is formed of a metallic thin film by sputtering. Then impurity ions which become a donor or an acceptor are implanted by using the gate electrodes 105 as a mask, and source and drain areas 107 and channel forming area 108 are formed in an self-aligning way against the gate electrode 105. Thereafter, the manufacturing of a thin film semiconductor device is completed by depositing an interlayer insulating film 109 and forming wiring 110.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は薄膜トランジスタ
(TFT)等に代表される半導体装置の製造方法に関す
る。更に詳しくは、本願発明は高性能で信頼性に富む半
導体装置を、600℃程度以下の比較的低温にて製造す
る方法に関する。
The present invention relates to a method for manufacturing a semiconductor device typified by a thin film transistor (TFT) and the like. More specifically, the present invention relates to a method for manufacturing a semiconductor device having high performance and high reliability at a relatively low temperature of about 600 ° C. or lower.

【0002】[0002]

【従来の技術】多結晶硅素薄膜トランジスタ(p−Si
TFT)に代表される半導体装置を汎用ガラス基板を
使用し得る600℃程度以下の低温にて製造する場合、
従来以下の如き製造方法が取られて居た。まずエキシマ
レーザー照射法などで多結晶硅素膜(p−Si膜)形成
した後、ゲート絶縁膜と成る酸化硅素膜を化学気相堆積
法(CVD法)や物理気相堆積法(PVD法)にて形成
する。次にタンタル等でゲート電極を作成して、金属
(ゲート電極)−酸化膜(ゲート絶縁膜)−半導体(多
結晶硅素膜)から成る電界効果トランジスタ(MOS−
FET)を構成せしめて居た。
2. Description of the Related Art Polycrystalline silicon thin film transistors (p-Si
When manufacturing a semiconductor device typified by TFT) at a low temperature of about 600 ° C. or less, which can use a general-purpose glass substrate,
Conventionally, the following manufacturing method has been adopted. First, a polycrystalline silicon film (p-Si film) is formed by an excimer laser irradiation method or the like, and then a silicon oxide film serving as a gate insulating film is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Formed. Next, a gate electrode is formed of tantalum or the like, and a field effect transistor (MOS) composed of a metal (gate electrode) -oxide film (gate insulating film) -semiconductor (polycrystalline silicon film) is formed.
FET).

【0003】[0003]

【発明が解決しようとする課題】しかしながら此等従来
の半導体装置の製造方法では酸化硅素膜が多量の酸化膜
捕獲電荷を有する等の多くの問題を抱えて居り、その膜
品質が窮めて貧弱で有るとの課題を有して居た。斯くし
た事実に則し、従来の製造方法にてp−Si TFT等
の半導体装置を製造すると、完成した半導体装置はその
電気特性が悪いにのみならず、使用途上に経時劣化が生
ずる等の信頼性にも課題を有して居た。
However, the conventional method of manufacturing a semiconductor device has many problems such as a silicon oxide film having a large amount of charge trapped by an oxide film, and the film quality is poor and poor. Had the problem of being. In accordance with such a fact, when a semiconductor device such as a p-Si TFT is manufactured by a conventional manufacturing method, not only the completed semiconductor device has poor electrical characteristics but also reliability such as deterioration over time during use. There was also a problem with gender.

【0004】そこで本発明は上述の諸事情を鑑み、その
目的とする所は600℃程度以下との低温工程で優良な
半導体装置を製造する方法を提供する事に有る。
The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing an excellent semiconductor device in a low-temperature process at about 600 ° C. or less.

【0005】[0005]

【課題を解決するための手段】本発明は絶縁性物質上に
形成された半導体膜と、この半導体膜上に形成された酸
化硅素に代表される酸化膜の二者を構成要件として居る
半導体装置の製造方法に関し、少なくとも以下の五工程
を以てその特徴と為す。即ち半導体膜を形成する第一工
程と、気相堆積法にて酸化膜を半導体膜上に堆積する第
二工程と、酸化膜に酸化性雰囲気下にて第一熱処理を施
す第三工程と、半導体膜と酸化膜に対して第二熱処理を
施す第四工程と、半導体膜が内有する不対結合対に水素
を結合させる第五工程とで有る。
According to the present invention, there is provided a semiconductor device comprising two components, a semiconductor film formed on an insulating material and an oxide film typified by silicon oxide formed on the semiconductor film. The method is characterized by at least the following five steps. That is, a first step of forming a semiconductor film, a second step of depositing an oxide film on the semiconductor film by a vapor deposition method, and a third step of performing a first heat treatment on the oxide film in an oxidizing atmosphere, A fourth step of performing a second heat treatment on the semiconductor film and the oxide film; and a fifth step of bonding hydrogen to an unpaired pair included in the semiconductor film.

【0006】まず本発明は第一工程としてガラス基板や
三次元半導体装置の層間絶縁膜等の縁性物質上に多結晶
硅素(p−Si)に代表される半導体膜を形成する。こ
の半導体膜は結晶状態に有っても非晶質状態に有っても
構わないが、多結晶状態に有る時に本願発明は殊の外そ
の効果を示す。此は本願発明が半導体膜と絶縁膜との界
面に存在する捕獲準位(界面準位)を低減せしめると共
に、結晶粒と結晶粒との間に位置する捕獲準位(粒界準
位)をも低減せしめるが故で有る。言う迄もなく界面準
位は結晶状態に拘わらず半導体膜と絶縁膜との接合界面
には必ず存在する。この界面準位を低減させるから、本
願発明は半導体膜の状態の如何に拘わらず有効なので有
る。一方、多結晶膜に対しては此の効果に加え、粒界準
位を減らすとの効果も認められる。半導体膜は硅素(S
i)や硅素ゲルマニウム(SiGe1−x:0<x<
1)等如何なる半導体物質で有っても構わないが、簡便
に良好なMOS界面を構成するとの視点からは、硅素単
体や硅素をその主構成元素(硅素原子構成比が80%程
度以上)として居る半導体物質が優れて居る。半導体膜
は物理気相堆積法(PVD法)や化学気相堆積法(CV
D法)等の気相堆積法等で形成される。PVD法にはス
パッター法や蒸着法等が考えられる。又CVD法には常
圧化学気相堆積法(APCVD法)や低圧化学気相堆積
法(LPCVD法)、プラズマ化学気相堆積法(PEC
VD法)等が使用され得る。気相堆積法で形成された半
導体膜は、堆積直後には通常多結晶状態か非晶質状態
に、又はこれらの混合状態に有る。多結晶状態に有る薄
膜は多結晶膜と称され、非晶質状態や混合状態に有る薄
膜は非晶質膜や混晶質膜と其々称される。半導体装置の
能動部(電界効果型トランジスタのソース・ドレイン領
域やチャンネル形成領域、及びバイポーラ型トランジス
タのエミッター・ベース・コレクター領域)としては堆
積直後に得られた多結晶膜をその侭使用する事も可能で
有る。此とは対照的に非晶質膜や混晶質膜を結晶化した
り、或いは多結晶膜を再結晶化するなどして、新たな多
結晶膜を得た後に此等を能動部として使用する事も可能
で有る。結晶化や再結晶化を行うにはレーザー照射や急
速熱処理が用いられる。
First, in the present invention, as a first step, a semiconductor film typified by polycrystalline silicon (p-Si) is formed on an edge material such as a glass substrate or an interlayer insulating film of a three-dimensional semiconductor device. The semiconductor film may be in a crystalline state or an amorphous state, but when it is in a polycrystalline state, the present invention exhibits its effects. This is because the present invention reduces the trap level (interface level) existing at the interface between the semiconductor film and the insulating film, and reduces the trap level (grain boundary level) located between crystal grains. Is also reduced. Needless to say, the interface state always exists at the bonding interface between the semiconductor film and the insulating film regardless of the crystal state. Since this interface state is reduced, the present invention is effective regardless of the state of the semiconductor film. On the other hand, for a polycrystalline film, in addition to this effect, an effect of reducing the grain boundary level is also recognized. The semiconductor film is silicon (S
i) and silicon germanium (Si x Ge 1-x: 0 <x <
1) Any semiconductor material may be used, but from the viewpoint of easily forming a good MOS interface, silicon alone or silicon is used as its main constituent element (silicon atom composition ratio is about 80% or more). The semiconductor material is excellent. Semiconductor films can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CV).
D method) or the like. As the PVD method, a sputtering method, an evaporation method, or the like can be considered. The CVD method includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma chemical vapor deposition (PEC).
VD method) or the like can be used. A semiconductor film formed by a vapor deposition method is usually in a polycrystalline state, an amorphous state, or a mixed state thereof immediately after deposition. A thin film in a polycrystalline state is called a polycrystalline film, and a thin film in an amorphous state or a mixed state is called an amorphous film or a mixed crystalline film, respectively. For the active part of the semiconductor device (source / drain region and channel formation region of a field effect transistor, and emitter / base / collector region of a bipolar transistor), a polycrystalline film obtained immediately after deposition may be used as it is. It is possible. In contrast, a new polycrystalline film is obtained by crystallizing an amorphous film or mixed crystal film, or recrystallizing a polycrystalline film, and then using these as an active part. Things are possible. Laser irradiation or rapid heat treatment is used for crystallization or recrystallization.

【0007】次に第二工程として気相堆積法にて酸化膜
を半導体膜上に堆積する。酸化膜の堆積は高くとも60
0℃程度以下の温度で、通常は400℃程度以下の温度
で行われる。此は本願が対象として居る半導体装置を汎
用ガラス基板やプラスチック基板等、耐熱性の乏しい基
板上に製造する事を前提として居るからで有る。此の酸
化膜をMOS−FETのゲート絶縁膜として利用する。
半導体膜と絶縁膜との良好な界面を簡便に得るには、酸
化膜の主構成物質は酸化硅素(SiO:0<x≦2)
で有る事が望ましい。酸化膜は物理気相堆積法(PVD
法)や化学気相堆積法(CVD法)等の気相堆積法等で
形成される。PVD法にはスパッター法や蒸着法等が考
えられる。CVD法には常圧化学気相堆積法(APCV
D法)や低圧化学気相堆積法(LPCVD法)、プラズ
マ化学気相堆積法(PECVD法)等が使用され得る。
斯様にして得られた酸化膜は、1100℃程度以上の温
度で形成される熱酸化膜に比べて酸化膜中に酸化膜捕獲
準位や固定電荷を多量に含み、更に界面準位も遥かに高
いのが普通で有る。それ故、本願発明では以下の三工程
(第三、第四、第五工程)を以て、酸化膜と界面及び結
晶粒界の改質を図る訳で有る。
Next, as a second step, an oxide film is deposited on the semiconductor film by a vapor deposition method. Oxide deposition at most 60
It is performed at a temperature of about 0 ° C. or less, usually at a temperature of about 400 ° C. or less. This is because it is assumed that the semiconductor device to which the present invention is applied is manufactured on a substrate having poor heat resistance, such as a general-purpose glass substrate or a plastic substrate. This oxide film is used as a gate insulating film of a MOS-FET.
In order to easily obtain a good interface between the semiconductor film and the insulating film, the main constituent material of the oxide film is silicon oxide (SiO x : 0 <x ≦ 2).
It is desirable that it is. Oxide film is deposited by physical vapor deposition (PVD).
) Or a vapor phase deposition method such as a chemical vapor deposition method (CVD method). As the PVD method, a sputtering method, an evaporation method, or the like can be considered. Atmospheric pressure chemical vapor deposition (APCV)
D), low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), and the like.
The oxide film thus obtained contains a larger amount of oxide film trapping levels and fixed charges in the oxide film than the thermal oxide film formed at a temperature of about 1100 ° C. or higher, and further has a much higher interface state. It is usually high. Therefore, in the present invention, the following three steps (third, fourth, and fifth steps) are performed to reform the oxide film, the interface, and the crystal grain boundaries.

【0008】第三工程では酸化膜に酸化性雰囲気下に
て、200℃程度から600℃程度の温度で第一熱処理
を施す。酸化性雰囲気は塩酸(HCl)や硝酸(HNO
)、弗酸(HF)等の酸や水(HO)と云った半導
体膜に対する酸化促進物質と、酸素(O)や亜酸化窒
素(N0)、二酸化炭素(CO)と云った酸素含有
気体とを少なくとも含んだ気体から構成される。此の雰
囲気は酸化促進物質と酸素含有気体と不活性気体から成
って居ても無論良い。最も簡単な一例は水蒸気を含有し
た空気で有る。此の場合、水蒸気が酸化促進物質で有
り、空気中の酸素が酸素含有気体で有る。前者の酸化促
進物質は、酸化硅素膜等の酸化膜を構成する元素(硅素
や酸素)間の歪んだ結合や弱い結合を切断する性質を有
して居ると共に、半導体膜の酸化を促進する触媒の性質
をも有して居る。此に対して後者は酸素欠損を生じて居
る酸化膜や界面に酸素を供給し、不完全な酸化膜(例え
ばSiO:0<x<2)や酸素欠損の多い界面を完全
な酸化膜(例えばSiO)や酸素欠損の少ない界面へ
と改善する。此の第一熱処理に依り酸化膜を構成する歪
んだ結合や弱い結合は切断と再結合を繰り返され、最終
的に酸化膜は正常で強い結合から成るSi−O−Si結
合の編み目構想を取るに到る。斯様にして酸化膜捕獲準
位や固定電荷、界面準位が大幅に低減されるので有る。
此の事は半導体装置の立場からすると、フラットバンド
電位を理想値(ゲート電極を構成する金属の仕事関数と
半導体の仕事関数の差)に近づけ、閾値電圧を小さく
し、更に半導体装置の信頼性を増して居るを意味して居
る。第三工程の処理温度はそれが高い程、その処理時間
は短くて済む。常識的な処理時間(長くとも24時間程
度)で処理を完了させるには最低でも200℃程度の温
度が必要と成る。一方、他の半導体装置上やガラス基板
上に本願発明の半導体装置を作製する場合には、他の半
導体装置や基板を保護するとの立場から最高温度は60
0℃程度と成る。大型液晶装置に本願発明の半導体装置
を適応する場合には、大型化に伴い(ガラス基板寸法が
400mm×500mm程度以上)基板の耐熱性が劣っ
て来るので、最高温度は450℃程度が望まれる。本願
発明では第五工程で半導体膜が有する欠陥を水素にて補
修する。然るに此の欠陥は少なければ少ないに越した事
はない。半導体膜が多結晶膜の場合、第三工程の熱処理
で多結晶膜の欠陥を終端して居る水素が離脱し、欠陥が
増す恐れが有る。水素離脱を防ぎ多結晶膜の欠陥を最少
に止める為には、第三工程の処理温度は350℃程度以
下が好ましい。
In a third step, a first heat treatment is performed on the oxide film at a temperature of about 200 ° C. to about 600 ° C. in an oxidizing atmosphere. The oxidizing atmosphere is hydrochloric acid (HCl) or nitric acid (HNO
3 ) an acid such as hydrofluoric acid (HF) or an oxidation promoting substance for a semiconductor film such as water (H 2 O); oxygen (O 2 ), nitrous oxide (N 20 ), carbon dioxide (CO 2 ) And a gas containing at least an oxygen-containing gas. This atmosphere may of course consist of an oxidation promoting substance, an oxygen-containing gas and an inert gas. One of the simplest examples is air with water vapor. In this case, water vapor is an oxidation promoting substance, and oxygen in the air is an oxygen-containing gas. The former oxidation-promoting substance has the property of breaking distorted or weak bonds between elements (silicon and oxygen) constituting an oxide film such as a silicon oxide film, and a catalyst that promotes oxidation of a semiconductor film. It also has the property of On the other hand, the latter supplies oxygen to an oxide film or an interface having an oxygen deficiency, and forms an incomplete oxide film (for example, SiO x : 0 <x <2) or an interface having many oxygen deficiencies to a complete oxide film ( For example, it is improved to an interface having few SiO 2 ) or oxygen vacancies. Due to this first heat treatment, the distorted bonds and weak bonds constituting the oxide film are repeatedly cut and recombined, and finally the oxide film takes a stitch concept of a normal and strong bond of Si-O-Si bond. To reach. In this way, the oxide film trap level, fixed charge, and interface level are greatly reduced.
From the standpoint of a semiconductor device, this implies that the flat band potential approaches the ideal value (the difference between the work function of the metal forming the gate electrode and the work function of the semiconductor), reduces the threshold voltage, and further improves the reliability of the semiconductor device. It means that we are increasing. The higher the processing temperature of the third step, the shorter the processing time. A temperature of at least about 200 ° C. is required to complete the processing in a common sense processing time (at most about 24 hours). On the other hand, when manufacturing the semiconductor device of the present invention on another semiconductor device or a glass substrate, the maximum temperature is set to 60 from the standpoint of protecting the other semiconductor device and the substrate.
It is about 0 ° C. When the semiconductor device of the present invention is applied to a large-sized liquid crystal device, the heat resistance of the substrate becomes inferior with the increase in size (the size of the glass substrate is about 400 mm × 500 mm or more). . In the present invention, defects in the semiconductor film are repaired with hydrogen in the fifth step. But the flaws are few and few. In the case where the semiconductor film is a polycrystalline film, hydrogen which terminates defects in the polycrystalline film may be released by the heat treatment in the third step, and the number of defects may increase. In order to prevent hydrogen elimination and minimize defects in the polycrystalline film, the processing temperature in the third step is preferably about 350 ° C. or less.

【0009】第四工程の第二熱処理は非酸化性雰囲気下
にて行われる。その内でも特に窒素(N)やアルゴン
(Ar)等の不活性雰囲気下や、此等不活性雰囲気中に
水素を含有した雰囲気、或いは水素単体から成る雰囲気
下にて行われる。第四工程の第二熱処理では第一熱処理
の最中に酸化膜中に拡散した酸や水等の物質を取り除
く。此等の物質が酸化膜中に残存すると潜在的な酸化膜
準位や界面準位と化し、半導体装置の信頼性を低下させ
る事と成る。従って第四工程の第二熱処理を行う事で半
導体装置の信頼性は著しく増大する事に成る。酸化膜中
に拡散した酸や水を除去するには、酸や水を含まぬ雰囲
気下で熱処理を行えば、其の効果は認められる。但し酸
素を含む等の酸化性雰囲気下にてこの第二熱処理を行う
と、酸化の進行に伴い新たに不完全な界面が形成されて
仕舞い、界面準位の低減効果は弱まる事に成る。それ
故、第二熱処理は不活性雰囲気下乃至は弱還元性雰囲気
下にて行われる。斯うすると界面準位が低い侭に保た
れ、優良な半導体装置が得られるので有る。界面準位を
更に低減するには第二熱処理を水素含有雰囲気下にて行
う事が好ましい。この場合、水素単体の雰囲気下で行っ
ても良いが、安全性を考慮すると水素を窒素やアルゴン
と云った不活性気体で、濃度が爆発下限界以下と成る4
%程度未満に希釈して熱処理を行う事が望ましい。第四
工程の熱処理温度は第三工程の熱処理温度と略同じで有
るか、或いは第三工程の熱処理温度よりも高く設定す
る。此は酸化膜中から不要な物質を早急且つ効果的に除
去し、更に酸化膜の編み目構造をより改善するには、第
二熱処理の温度は高い方が好ましいからで有る。そうし
た意味では此の第四工程の熱処理温度が第二工程以降、
半導体装置が完成する迄の全工程中の最高温度で有る事
が最も好ましい。第一熱処理の温度と第二熱処理の温度
の関係は概ね第二熱処理温度が第一熱処理温度よりも2
5℃程度から75℃程度高い事が望ましい。例えば第一
熱処理を300℃程度から350℃程度で行い、第二熱
処理を350℃程度から400℃程度で行うのが理想と
言えよう。此の温度関係ならば熱処理炉の温度変動を考
慮しても、第一熱処理の酸化膜編み目構造補修効果も第
二熱処理の不要物質除去効果も確実に達成出来、且つ半
導体膜からの水素離脱も最小限に押さえる事が可能だか
らで有る。
The second heat treatment in the fourth step is performed in a non-oxidizing atmosphere. Of these, the process is performed under an inert atmosphere such as nitrogen (N 2 ) or argon (Ar), an atmosphere containing hydrogen in the inert atmosphere, or an atmosphere consisting of hydrogen alone. In the second heat treatment of the fourth step, substances such as acid and water diffused into the oxide film during the first heat treatment are removed. When these substances remain in the oxide film, they become potential oxide film levels or interface states, which lowers the reliability of the semiconductor device. Therefore, performing the second heat treatment in the fourth step significantly increases the reliability of the semiconductor device. In order to remove the acid and water diffused in the oxide film, the effect can be recognized by performing a heat treatment in an atmosphere containing no acid or water. However, if this second heat treatment is performed in an oxidizing atmosphere containing oxygen or the like, a new imperfect interface is formed with the progress of oxidation, and the second heat treatment is performed, and the effect of reducing the interface state is weakened. Therefore, the second heat treatment is performed in an inert atmosphere or a weak reducing atmosphere. In this case, the interface state is kept low, and an excellent semiconductor device can be obtained. In order to further reduce the interface state, the second heat treatment is preferably performed in a hydrogen-containing atmosphere. In this case, the reaction may be performed in an atmosphere of hydrogen alone, but considering safety, hydrogen is an inert gas such as nitrogen or argon and the concentration is lower than the lower explosion limit.
It is desirable to perform the heat treatment after diluting to less than about%. The heat treatment temperature in the fourth step is substantially the same as the heat treatment temperature in the third step, or is set higher than the heat treatment temperature in the third step. This is because the temperature of the second heat treatment is preferably higher in order to quickly and effectively remove unnecessary substances from the oxide film and to further improve the stitch structure of the oxide film. In that sense, the heat treatment temperature in this fourth step is
Most preferably, it is the highest temperature during the entire process until the semiconductor device is completed. The relationship between the temperature of the first heat treatment and the temperature of the second heat treatment is generally such that the second heat treatment temperature is 2 times lower than the first heat treatment temperature.
It is desirable that the temperature be higher by about 5 ° C. to about 75 ° C. For example, ideally, the first heat treatment is performed at about 300 ° C. to about 350 ° C., and the second heat treatment is performed at about 350 ° C. to about 400 ° C. With this temperature relationship, the effect of repairing the knitted structure of the oxide film in the first heat treatment and the effect of removing unnecessary substances in the second heat treatment can be reliably achieved even if the temperature fluctuation of the heat treatment furnace is taken into consideration, and the desorption of hydrogen from the semiconductor film is also reduced. This is because it can be kept to a minimum.

【0010】第四工程が終了した後に、第五工程として
半導体膜が有する不対結合対に水素を結合させる水素化
処理を行う。第三工程や第四工程に依り半導体膜表面の
捕獲準位数は価電子帯近傍や伝導帯近傍を主として低減
されて居るが、本第五工程で残った界面の不対結合対や
多結晶性半導体膜の結晶粒界に存在する不対結合対を水
素で終端し、禁制帯中の中心部付近(真性フェルミレベ
ル近傍)に於ける捕獲準位(ディープ・ステイツ)を減
少させるので有る。第三工程では界面の歪んだ結合等を
修繕して禁制帯中の浅いレベル(禁制帯中で価電子帯や
伝導帯に近い所)の捕獲準位(テール・ステイツ)を大
幅に低減した。其の一方で修繕に伴い必然的に不対結合
対が発生し、ディープ・ステイツは増加する事に成る。
又、第三工程や第四工程の温度が高い程、酸化膜や界面
の改質効果は大きいのだが、此は取りも直さず半導体膜
中の不対結合対を終端して居る水素の離脱を促し、結果
として半導体のディープ・ステイツを増大させる事に成
る。言い換えれば第三工程や第四工程では半導体装置の
フラットバンド電位を理想値に近づけ、テール・ステイ
ツを減少させ、更に半導体装置の信頼性を増して居るの
だが、同時にディープ・ステイツを増大させる事にも繋
がり得るので有る。そこで本第五工程に依り此のディー
プ・ステイツをも減少させる。ディープ・ステイツの主
因は半導体膜の界面や粒界に存在する不対結合対で有
る。此等は水素化処理に依り容易に不活性とされ、不活
性化されれば捕獲準位は減少する。最も簡単に水素化処
理を行うには基板に水素プラズマを照射する事で有る。
水素化処理は基板温度が低過ぎる(100℃程度未満)
と反応が進行せず、基板温度が高過ぎる(450℃程度
以上)と水素離脱と言った逆反応の進行が速く成るの
で、100℃程度から450℃程度の間の基板温度で行
う。理想的には250℃程度から400℃程度の間の温
度で有る。前述の如く本願発明では第四工程の熱処理温
度が第二工程以降で半導体装置が完成する迄の最高温度
と成って居る。従って第五工程の温度も第四工程の温度
と同等かそれ以下で有る。第五工程で不対結合対を終端
した水素が半導体装置完成迄に離脱させない為には、此
以後の工程は総て第五工程で水素化を行った基板温度よ
りも低い温度で処理されねばならない。即ち、第五工程
以降の最高温度は第五工程の基板温度よりも必ず低く、
其の温度は水素離脱の生じない400℃程度以下とす
る。第五工程に於ける水素化処理時間は10秒間程度か
ら10分間程度で有る。10秒程度未満だと水素化の効
果は現れず、10分程度以上だと酸化膜や半導体膜にプ
ラズマダメージ等の損傷が入る恐れが有るからで有る。
After the fourth step is completed, a hydrogenation treatment for bonding hydrogen to the unpaired pair of the semiconductor film is performed as a fifth step. The trap level on the surface of the semiconductor film is reduced mainly in the vicinity of the valence band and the conduction band by the third step and the fourth step. This is because an unpaired bond pair present in the crystal grain boundary of the intrinsic semiconductor film is terminated with hydrogen, and the trap level (deep states) near the center of the forbidden band (near the intrinsic Fermi level) is reduced. In the third step, the trapped states (tail states) at shallow levels in the forbidden band (close to the valence band and conduction band in the forbidden band) were greatly reduced by repairing the distorted bonds at the interface. On the other hand, unpaired pairs are inevitably generated due to the repair, and the deep state increases.
Also, the higher the temperature in the third and fourth steps, the greater the effect of reforming the oxide film and the interface, but this is not eliminated, and the desorption of hydrogen terminating the unpaired pair in the semiconductor film is not eliminated. And increase the deep state of the semiconductor as a result. In other words, in the third and fourth steps, the flat band potential of the semiconductor device approaches the ideal value, the tail state is reduced, and the reliability of the semiconductor device is further increased. It can also lead to Therefore, the deep state is also reduced according to the fifth step. The main cause of deep states is an unpaired pair existing at the interface or grain boundary of the semiconductor film. These are easily made inert by the hydrogenation treatment, and if they are inactivated, the trap level decreases. The easiest way to perform the hydrogenation treatment is to irradiate the substrate with hydrogen plasma.
Substrate temperature is too low for hydrogenation (less than 100 ° C)
When the substrate temperature is too high (about 450 ° C. or more), the reverse reaction such as hydrogen elimination progresses rapidly. Therefore, the reaction is performed at a substrate temperature of about 100 ° C. to about 450 ° C. Ideally, the temperature is between about 250 ° C. and about 400 ° C. As described above, in the present invention, the heat treatment temperature in the fourth step is the maximum temperature until the semiconductor device is completed after the second step. Therefore, the temperature of the fifth step is also equal to or lower than the temperature of the fourth step. In order to prevent the hydrogen terminating the unpaired pair in the fifth step from being released by the time the semiconductor device is completed, all of the subsequent steps must be performed at a temperature lower than the temperature of the substrate subjected to the hydrogenation in the fifth step. No. That is, the maximum temperature after the fifth step is always lower than the substrate temperature in the fifth step,
The temperature is set to about 400 ° C. or less at which hydrogen desorption does not occur. The hydrogenation time in the fifth step is from about 10 seconds to about 10 minutes. If the time is less than about 10 seconds, the effect of hydrogenation does not appear. If the time is about 10 minutes or more, there is a possibility that the oxide film or the semiconductor film may be damaged such as plasma damage.

【0011】尚、第四工程終了から第五工程開始迄の期
間は、第四工程にて生じた不対結合対に空気中の酸素や
硼素等の不純物が結合せぬ様に、出来る限り短時間とす
べきで、その期間は概ね6時間程度未満とせねばならな
い。
The period from the end of the fourth step to the start of the fifth step is as short as possible so that impurities such as oxygen and boron in the air do not bond to the unpaired pair generated in the fourth step. It should be time, and the duration should be less than about six hours.

【0012】結局、半導体特性の視点より第三乃至第五
工程の効果を論ずると、第三工程でフラットバンド電位
を理想値に近づけると共にテール・ステイツを減少さ
せ、第四工程で酸化膜漏れ電流や酸化膜内捕獲準位の低
減と云った半導体装置の信頼性を増し、第五工程でディ
ープ・ステイツを低減して居る事に成る。捕獲準位(テ
ール・ステイツやディープ・ステイツ)が低減される
と、電気伝導に寄与する荷電担体数が増加するにのみな
らず、捕獲電荷に依る荷電担体の散乱も減るので移動度
も大きく成る。又、サブスレーシュホールド・スイング
や閾値電圧が小さくなり、急峻なスイッチ性能を示す良
好な半導体装置が得られる事と成る。
After all, from the viewpoint of semiconductor characteristics, the effects of the third to fifth steps are discussed. In the third step, the flat band potential approaches the ideal value, the tail state is reduced, and the oxide film leakage current is reduced in the fourth step. In addition, the reliability of the semiconductor device, such as the reduction of the trap level in the oxide film, is increased, and the deep state is reduced in the fifth step. When the trap level (tail state or deep state) is reduced, not only the number of charge carriers contributing to electric conduction is increased, but also the scattering of the charge carriers due to the trapped charges is reduced, so that the mobility is increased. . In addition, the sub-threshold swing and the threshold voltage are reduced, and a good semiconductor device showing a steep switching performance can be obtained.

【0013】[0013]

【発明の実施の形態】(実施例1)図1(a)〜(d)
はMOS型電界効果トランジスタを形成する薄膜半導体
装置の製造工程を断面で示した図で有る。本実施例1で
は基板101として歪点が650℃程度の汎用無アルカ
リガラスを用いた。まず基板101上にECR−PEC
VD法で酸化硅素膜を200nm程度堆積し、下地保護
膜102とした。酸化硅素膜のECR−PECVD法で
の堆積条件は以下の通りで有る。
(Embodiment 1) FIGS. 1 (a) to 1 (d)
FIG. 2 is a cross-sectional view showing a manufacturing process of a thin film semiconductor device for forming a MOS field effect transistor. In the first embodiment, a general-purpose non-alkali glass having a strain point of about 650 ° C. was used as the substrate 101. First, ECR-PEC is placed on the substrate 101.
A silicon oxide film was deposited to a thickness of about 200 nm by the VD method to form a base protective film 102. The conditions for depositing the silicon oxide film by the ECR-PECVD method are as follows.

【0014】 モノシラン(SiH)流量・・・60sccm 酸素(O)流量・・・100sccm 圧力・・・2.40mTorr マイクロ波(2.45GHz)出力・・・2250W 印可磁場・・・875Gauss 基板温度・・・100℃ 成膜時間・・・40秒 此の下地保護膜上に半導体膜として真性非晶質硅素膜を
LPCVD法にて50nm程度の膜厚に堆積した。LP
CVD装置はホット・ウォール型で容積が184.5l
で、基板挿入後の反応総面積は約44000cmで有
る。堆積温度は425℃で原料ガスとして純度99.9
9%以上のジシラン(Si)を用い、200sc
cm反応炉に供給した。堆積圧力は凡そ1.1Torr
で有り、此の条件下で硅素膜の堆積速度は0.77nm
/minで有った。斯様にして得られた非晶質半導体膜
にクリプトン弗素(KrF)エキシマレーザーを照射し
て半導体膜の結晶化を進めた。照射レーザーエネルギー
密度は245mJ・cm−2で、半導体膜が膜厚方向全
体に渡り完全溶融して微結晶化が生ずるエネルギー密度
よりも15mJ・cm−2低いエネルギー密度で有っ
た。こうして結晶性半導体膜(多結晶硅素膜)を形成し
た(第一工程)後、この結晶性半導体膜を島状に加工し
て、後に半導体装置の能動層と成る半導体膜の島103
を形成した。(図1−a) 次にパターニング加工された半導体膜の島103を被う
様に酸化硅素膜104をECR−PECVD法にて形成
(第二工程)した。此の酸化硅素膜は半導体装置のゲー
ト絶縁膜として機能する。ゲート絶縁膜と成る酸化硅素
膜堆積条件は堆積時間が24秒と短縮された事を除い
て、下地保護膜の酸化硅素膜の堆積条件と同一で有る。
但し、酸化硅素膜堆積の直前にはECR−PECVD装
置内で基板に酸素プラズマを照射して、半導体の表面に
低温プラズマ酸化膜を形成した。プラズマ酸化条件は次
の通りで有る。
Monosilane (SiH 4 ) flow rate: 60 sccm Oxygen (O 2 ) flow rate: 100 sccm Pressure: 2.40 mTorr Microwave (2.45 GHz) output: 2250 W Applied magnetic field: 875 Gauss Substrate temperature ... 100 ° C. Film formation time... 40 seconds An intrinsic amorphous silicon film was deposited as a semiconductor film to a thickness of about 50 nm on the underlying protective film by LPCVD. LP
The CVD equipment is a hot wall type with a volume of 184.5 l
The total reaction area after inserting the substrate is about 44000 cm 2 . The deposition temperature is 425 ° C. and the purity is 99.9 as a source gas.
200 sc using disilane (Si 2 H 6 ) of 9% or more
cm reactor. Deposition pressure is about 1.1 Torr
Under these conditions, the deposition rate of the silicon film is 0.77 nm.
/ Min. The amorphous semiconductor film thus obtained was irradiated with a krypton fluorine (KrF) excimer laser to promote crystallization of the semiconductor film. The irradiation laser energy density was 245 mJ · cm −2, which was 15 mJ · cm −2 lower than the energy density at which the semiconductor film was completely melted over the entire thickness direction and microcrystallization was caused. After the crystalline semiconductor film (polycrystalline silicon film) is thus formed (first step), the crystalline semiconductor film is processed into an island shape, and the island 103 of the semiconductor film which will later become the active layer of the semiconductor device
Was formed. (FIG. 1A) Next, a silicon oxide film 104 was formed by ECR-PECVD so as to cover the island 103 of the semiconductor film subjected to the patterning process (second step). This silicon oxide film functions as a gate insulating film of the semiconductor device. The conditions for depositing the silicon oxide film as the gate insulating film are the same as the conditions for depositing the silicon oxide film as the base protective film, except that the deposition time is reduced to 24 seconds.
However, immediately before the deposition of the silicon oxide film, the substrate was irradiated with oxygen plasma in an ECR-PECVD apparatus to form a low-temperature plasma oxide film on the surface of the semiconductor. The plasma oxidation conditions are as follows.

【0015】 酸素(O)流量・・・100sccm 圧力・・・1.85mTorr マイクロ波(2.45GHz)出力・・・2000W 印可磁場・・・875Gauss 基板温度・・・100℃ 処理時間・・・24秒 プラズマ酸化に依り凡そ3.5nmの酸化膜が半導体表
面に形成されて居る。酸素プラズマ照射が終了した後、
真空を維持した侭連続で酸化膜を堆積した。従ってゲー
ト絶縁膜と成る酸化硅素膜はプラズマ酸化膜と気相堆積
膜の二者から成り、その膜厚は125nmで有った。
Oxygen (O 2 ) flow rate: 100 sccm Pressure: 1.85 mTorr Microwave (2.45 GHz) output: 2000 W Applicable magnetic field: 875 Gauss Substrate temperature: 100 ° C. Processing time: An oxide film of about 3.5 nm is formed on the semiconductor surface by plasma oxidation for 24 seconds. After the oxygen plasma irradiation ends,
An oxide film was deposited continuously while maintaining the vacuum. Therefore, the silicon oxide film serving as the gate insulating film was composed of a plasma oxide film and a vapor deposition film, and had a thickness of 125 nm.

【0016】第二工程で酸化硅素膜を形成した後、第三
工程として酸化性雰囲気下にて第一熱処理を行った。濃
度16%の塩化水素酸水溶液を空気中に露点で96℃含
む塩酸水蒸気空気下にて熱処理は施こされた。処理温度
は345℃で処理時間は2時間、処理室内圧力は1気圧
で有った。この塩酸に依る熱処理が終了した後、引き続
いて酸化膜中のハロゲン元素を抜く目的で1時間の熱処
理を継続した。この熱処理雰囲気は露点96℃の水蒸気
含有空気中で行われ、雰囲気に塩酸は含まれて居ない。
熱処理温度は矢張り345℃で圧力は1気圧で有る。
After the silicon oxide film was formed in the second step, a first heat treatment was performed in an oxidizing atmosphere as a third step. The heat treatment was performed in hydrochloric acid steam air containing a hydrochloric acid aqueous solution having a concentration of 16% in air at a dew point of 96 ° C. The processing temperature was 345 ° C., the processing time was 2 hours, and the processing chamber pressure was 1 atm. After the completion of the heat treatment using hydrochloric acid, the heat treatment was continued for one hour in order to remove the halogen element in the oxide film. This heat treatment atmosphere is performed in steam-containing air having a dew point of 96 ° C., and the atmosphere does not contain hydrochloric acid.
The heat treatment temperature is 345 ° C. and the pressure is 1 atm.

【0017】斯うして第三工程が終了した後に第四工程
の第二熱処理を行い、酸化膜を乾燥さた。第二熱処理は
アルゴン中に水素を3%含む非酸化性雰囲気下にて1気
圧、400℃で2時間施された。
After the completion of the third step, the second heat treatment of the fourth step was performed to dry the oxide film. The second heat treatment was performed in a non-oxidizing atmosphere containing 3% of hydrogen in argon at 1 atm and 400 ° C. for 2 hours.

【0018】第四工程終了後、基板は直ちに平行平板容
量結合型PECVD装置に導入され、基板に対して水素
プラズマ照射(第五工程)が施された。水素プラズマ条
件は以下の通りで有る。
After the fourth step, the substrate was immediately introduced into a parallel plate capacitively coupled PECVD apparatus, and the substrate was irradiated with hydrogen plasma (fifth step). The hydrogen plasma conditions are as follows.

【0019】 水素(H)流量・・・1000sccm 圧力・・・500mTorr rf波(13.56MHz)出力・・・100W 電極間距離・・・25mm 基板温度・・・370℃ 処理時間・・・90秒 斯様にしてゲート絶縁膜堆積と、酸化膜及び界面の改質
が完了した。(図1−b) 引き続いて金属薄膜に依りゲート電極105をスパッタ
ー法にて形成する。スパッター時の基板温度は150℃
で有った。本実施例1では750nmの膜厚を有するα
構造のタンタル(Ta)にてゲート電極を作成し、この
ゲート電極のシート抵抗は0.8Ω/□で有った。次に
ゲート電極をマスクとして、ドナー又はアクセプターと
なる不純物イオン106を打ち込み、ソース・ドレイン
領域107とチャンネル形成領域108をゲート電極に
対して自己整合的に作成する。本実施例1ではCMOS
半導体装置を作製した。NMOSトランジスタを作製す
る際にはPMOSトランジスタ部をアルミニウム(A
l)薄膜で覆った上で、不純物元素として水素中に5%
の濃度で希釈されたフォスヒィン(PH)を選び、加
速電圧80kVにて水素を含んだ総イオンを7×10
15cm−2の濃度でNMOSトランジスタのソース・
ドレイン領域に打ち込んだ。反対にPMOSトランジス
タを作製する際にはNMOSトランジスタ部をアルミニ
ウム(Al)薄膜で覆った上で、不純物元素として水素
中に5%の濃度で希釈されたジボラン(B)を選
び、加速電圧80kVにて水素を含んだ総イオンを5×
1015cmー2の濃度でPMOSトランジスタのソー
ス・ドレイン領域に打ち込んだ。(図1−c)イオン打
ち込み時の基板温度は300℃で有る。
Hydrogen (H 2 ) flow rate: 1000 sccm Pressure: 500 mTorr rf wave (13.56 MHz) output: 100 W Distance between electrodes: 25 mm Substrate temperature: 370 ° C. Processing time: 90 Second In this manner, the deposition of the gate insulating film and the modification of the oxide film and the interface are completed. (FIG. 1B) Subsequently, the gate electrode 105 is formed by a sputtering method using a metal thin film. The substrate temperature during sputter is 150 ° C
It was. In the first embodiment, α having a thickness of 750 nm
A gate electrode was formed from tantalum (Ta) having a structure, and the sheet resistance of the gate electrode was 0.8Ω / □. Next, using the gate electrode as a mask, an impurity ion 106 serving as a donor or an acceptor is implanted, and a source / drain region 107 and a channel formation region 108 are formed in a self-aligned manner with respect to the gate electrode. In the first embodiment, the CMOS
A semiconductor device was manufactured. When fabricating an NMOS transistor, the PMOS transistor portion is made of aluminum (A
l) After covering with a thin film, 5%
Phosphine (PH 3 ) diluted at a concentration of 7 × 10 3
At a concentration of 15 cm -2 , the source of the NMOS transistor
Driven into the drain region. Conversely, when fabricating a PMOS transistor, after covering the NMOS transistor portion with an aluminum (Al) thin film, diborane (B 2 H 6 ) diluted in hydrogen at a concentration of 5% is selected as an impurity element and accelerated. 5x total ions containing hydrogen at a voltage of 80 kV
It was implanted into the source / drain region of the PMOS transistor at a concentration of 10 15 cm -2 . (FIG. 1-c) The substrate temperature at the time of ion implantation is 300 ° C.

【0020】次にPECVD法でTEOS(Si−(O
CHCH)と酸素を原料気体として、基板温度
300℃で層間絶縁膜109を堆積した。層間絶縁膜は
二酸化硅素膜から成り、その膜厚は凡そ500nmで有
った。層間絶縁膜堆積後、層間絶縁膜の焼き締めとソー
ス・ドレイン領域に添加された不純物元素の活性化を兼
ねて、窒素雰囲気下350℃にて2時間の熱処理を施し
た。最後にコンタクト・ホールを開穴し、スパッター法
で基板温度を180℃としてアルミニウムを堆積し、配
線110を作成して薄膜半導体装置が完成した。(図1
−d) この様にして作成した薄膜半導体装置の伝達特性を測定
した。測定した半導体装置のチャンネル形成領域の長さ
及び幅は其々10μmで、測定は室温にて行われた。N
MOSトランジスタのVds=8Vに於ける飽和領域よ
り求めた移動度は93.7cm・Vー1・s−1で有
り、閾値電圧は3.43V、サブスレーシュホールド・
スイングは0.486Vで有った。又、PMOSトラン
ジスタのVds=−8Vに於ける飽和領域より求めた移
動度は46.2cm・Vー1・s−1で有り、閾値電
圧は−3.89V、サブスレーシュホールド・スイング
は0.532Vで有った。此に対して本実施例1から第
三工程乃至第五工程を削除した比較例ではNMOSトラ
ンジスタの移動度が74.2cm・Vー1・s−1
閾値電圧が4.34V、サブスレーシュホールド・スイ
ングが0.651Vで、PMOSトランジスタの移動度
が32.6cm・Vー1・s−1、閾値電圧が−7.
00V、サブスレーシュホールド・スイングが0.63
3Vで有った。本願発明に依りN型とP型の両半導体装
置共に高移動度で低閾値電圧を有し、急峻なサブスレー
シュホールド特性を示す良好な薄膜半導体装置が安定的
に製造された。この例が示す様に本発明に依ると優れた
特性を有し、然も酸化膜の信頼性が高い薄膜半導体装置
を汎用ガラス基板を使用し得る低温工程にて、簡便且つ
容易に作成し出来るので有る。
Next, TEOS (Si- (O
Using CH 2 CH 3 ) 4 ) and oxygen as source gases, an interlayer insulating film 109 was deposited at a substrate temperature of 300 ° C. The interlayer insulating film was made of a silicon dioxide film, and its thickness was about 500 nm. After the deposition of the interlayer insulating film, a heat treatment was performed at 350 ° C. for 2 hours in a nitrogen atmosphere to bake the interlayer insulating film and activate the impurity element added to the source / drain regions. Finally, a contact hole was opened, aluminum was deposited at a substrate temperature of 180 ° C. by a sputtering method, and a wiring 110 was formed to complete a thin film semiconductor device. (Figure 1
-D) The transfer characteristics of the thin film semiconductor device thus prepared were measured. The length and width of the channel formation region of the semiconductor device measured were 10 μm each, and the measurement was performed at room temperature. N
The mobility of the MOS transistor obtained from the saturation region at Vds = 8 V is 93.7 cm 2 · V −1 · s −1 , the threshold voltage is 3.43 V, and the
The swing was 0.486V. In addition, the mobility of the PMOS transistor obtained from the saturation region at Vds = −8 V is 46.2 cm 2 · V −1 · s −1 , the threshold voltage is −3.89 V, and the sub-shake hold swing is It was 0.532V. On the other hand, in the comparative example in which the third to fifth steps are deleted from the first embodiment, the mobility of the NMOS transistor is 74.2 cm 2 · V −1 · s −1 ,
The threshold voltage is 4.34 V, the subthreshold hold swing is 0.651 V, the mobility of the PMOS transistor is 32.6 cm 2 · V −1 · s −1 , and the threshold voltage is −7.
00V, sub-leash hold swing 0.63
It was 3V. According to the present invention, both N-type and P-type semiconductor devices have a high mobility, a low threshold voltage, and a good thin-film semiconductor device showing a steep sub-threshold hold characteristic has been stably manufactured. As shown in this example, a thin film semiconductor device having excellent characteristics according to the present invention and having a highly reliable oxide film can be easily and easily formed in a low-temperature process that can use a general-purpose glass substrate. There is.

【0021】[0021]

【発明の効果】以上詳述してきた様に、従来低品質で有
った気相堆積法で形成された酸化膜と界面を簡単な熱処
理の組み合わせ等にて高品質な膜と界面へと本願発明は
改質出来るので有る。これに依り薄膜トランジスタに代
表される半導体装置の電気特性を著しく向上させ、同時
に半導体装置の動作安定性をも高めるとの効果が認めら
れる。
As described in detail above, an oxide film and an interface formed by a vapor deposition method, which were conventionally of low quality, are converted into a high-quality film and an interface by a combination of simple heat treatment and the like. The invention can be modified. This has the effect of significantly improving the electrical characteristics of a semiconductor device typified by a thin film transistor, and at the same time increasing the operational stability of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本願発明の製造工程を説明した図。FIG. 1 is a diagram illustrating a manufacturing process of the present invention.

【符号の説明】[Explanation of symbols]

101・・・基板 102・・・下地保護膜 103・・・半導体膜の島 104・・・酸化硅素膜 105・・・ゲート電極 106・・・不純物イオン 107・・・ソース・ドレイン領域 108・・・チャネル形成領域 109・・・層間絶縁膜 110・・・配線 DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Underlying protective film 103 ... Semiconductor film island 104 ... Silicon oxide film 105 ... Gate electrode 106 ... Impurity ions 107 ... Source / drain region 108 ...・ Channel forming region 109 ・ ・ ・ Interlayer insulating film 110 ・ ・ ・ Wiring

Claims (15)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性物質上に形成された半導体膜と、
該半導体膜上に形成された酸化膜を少なくとも構成要件
として有する半導体装置の製造方法に於いて、 半導体膜を形成する第一工程と、気相堆積法にて酸化膜
を堆積する第二工程と、該酸化膜を酸化性雰囲気下にて
第一熱処理を施す第三工程と、該半導体膜と該酸化膜に
第二熱処理を施す第四工程と、該半導体膜が有する不対
結合対に水素を結合させる第五工程とを含む事を特徴と
する半導体装置の製造方法。
A semiconductor film formed on an insulating material;
In a method of manufacturing a semiconductor device having an oxide film formed on the semiconductor film as at least a constituent feature, a first step of forming a semiconductor film and a second step of depositing an oxide film by a vapor deposition method A third step of performing a first heat treatment on the oxide film in an oxidizing atmosphere; a fourth step of performing a second heat treatment on the semiconductor film and the oxide film; And a fifth step of combining the two.
【請求項2】 前記半導体膜が多結晶膜で有る事を特徴
とする請求項1記載の半導体装置の製造方法。
2. The method according to claim 1, wherein the semiconductor film is a polycrystalline film.
【請求項3】 前記半導体膜が硅素(Si)を主体と成
して居る事を特徴とする請求項1または2記載の半導体
装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor film is mainly composed of silicon (Si).
【請求項4】 前記酸化膜が酸化硅素(SiO:0<
x≦2)を主体と成して居る事を特徴とする請求項1乃
至3のいずれかに記載の半導体装置の製造方法。
4. The method according to claim 1, wherein the oxide film is made of silicon oxide (SiO x : 0 <
4. The method for manufacturing a semiconductor device according to claim 1, wherein x ≦ 2 is mainly used.
【請求項5】 前記第三工程が前記半導体膜に対する酸
化促進物質を含む雰囲気下にて行われる事を特徴とする
請求項1乃至4のいずれかに記載の半導体装置の製造方
法。
5. The method according to claim 1, wherein the third step is performed in an atmosphere containing an oxidation promoting substance for the semiconductor film.
【請求項6】 前記酸化促進物質が水で有る事を特徴と
する請求項5記載の半導体装置の製造方法。
6. The method according to claim 5, wherein said oxidation promoting substance is water.
【請求項7】 前記酸化促進物質が酸で有る事を特徴と
する請求項6記載の半導体装置の製造方法。
7. The method according to claim 6, wherein the oxidation promoting substance is an acid.
【請求項8】 前記第三工程が前記酸化膜を構成する元
素間の結合を切断する物質を含む雰囲気下にて行われる
事を特徴とする請求項1乃至4のいずれかに記載の半導
体装置の製造方法。
8. The semiconductor device according to claim 1, wherein the third step is performed in an atmosphere containing a substance that cuts a bond between elements constituting the oxide film. Manufacturing method.
【請求項9】 前記第四工程が非酸化性雰囲気下にて行
われる事を特徴とする請求項1乃至8のいずれかに記載
の半導体装置の製造方法。
9. The method according to claim 1, wherein said fourth step is performed in a non-oxidizing atmosphere.
【請求項10】 前記第四工程が不活性雰囲気下にて行
われる事を特徴とする請求項1乃至8のいずれかに記載
の半導体装置の製造方法。
10. The method according to claim 1, wherein the fourth step is performed in an inert atmosphere.
【請求項11】 前記第四工程が水素含有雰囲気下にて
行われる事を特徴とする請求項1乃至8のいずれかに記
載の半導体装置の製造方法。
11. The method according to claim 1, wherein said fourth step is performed in a hydrogen-containing atmosphere.
【請求項12】 前記第四工程の熱処理温度が前記第三
工程の熱処理温度と略同じで有る事を特徴とする請求項
1乃至11のいずれかに記載の半導体装置の製造方法。
12. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment temperature in the fourth step is substantially the same as the heat treatment temperature in the third step.
【請求項13】 前記第四工程の熱処理温度が前記第三
工程の熱処理温度よりも高い事を特徴とする請求項1乃
至11のいずれかに記載の半導体装置の製造方法。
13. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment temperature in the fourth step is higher than the heat treatment temperature in the third step.
【請求項14】 前記第四工程の熱処理温度が前記第二
工程以降該半導体装置が完成する迄の全工程中の最高温
度で有る事を特徴とする請求項12または13記載の半
導体装置の製造方法。
14. The manufacturing of a semiconductor device according to claim 12, wherein the heat treatment temperature in the fourth step is the highest temperature in all the steps from the second step to the completion of the semiconductor device. Method.
【請求項15】 前記第五工程が水素を含有したプラズ
マ照射で有る事を特徴とする請求項1乃至14のいずれ
かに記載の半導体装置の製造方法。
15. The method of manufacturing a semiconductor device according to claim 1, wherein said fifth step is irradiation of a plasma containing hydrogen.
JP25013198A 1998-09-03 1998-09-03 Manufacturing method of semiconductor device Expired - Fee Related JP3648998B2 (en)

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007010921A1 (en) * 2005-07-19 2007-01-25 Osaka University Method for oxide film formation, semiconductor device comprising the oxide film, and process for producing the semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007010921A1 (en) * 2005-07-19 2007-01-25 Osaka University Method for oxide film formation, semiconductor device comprising the oxide film, and process for producing the semiconductor device

Also Published As

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