JP2000036620A - Multi-layer indium-contained nitride buffer layer for nitride epitaxy - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a cracking due to doping and composition fluctuation is prevented. SOLUTION: A semiconductor device comprising an active structure comprising a substrate, a buffer structure or nucleus generation structure, and a circuit element. The nucleus generation layer is manufactured at a relatively low temperature and comprises at least one layer of an III-V group nitride compound comprising indium. At least one layer (the one directly deposited on a substrate is preferred), of a multi-layer structure, is made of an indium-containing III-V group nitride compound, acting as a buffer layer 16. The indium-containing layer is relaxed with a succeeding AlInGaN epitaxy. As a stress and crack are reduced, the flexibility in composition and doping adjustment is improved. Since the electrical and optical characteristics of a device is decided by the stress and distortion condition in the active structure, the composition and layer-pressure of the nucleus generation layer are adjusted to design the characteristics to a target. An indium-containing nitride of high quality is effectively grown at a relatively low temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices and their fabrication, and more particularly to different substrates and / or devices.
Alternatively, it relates to depositing a layer in a thin film on a combination of existing layers. The invention is particularly applicable to light emitting diodes (LE
It is applicable to optoelectronic devices such as D).

[0002]

2. Description of the Related Art Semiconductor manufacturing processes generally involve starting with a substrate, such as a silicon wafer, and depositing a series of patterned layers on the wafer. Such a layer can include an insulating layer such as a doped semiconductor material, ie, an oxide. The pattern is formed using photoresist masking, etching or other techniques.

[0003] The patterned layers constitute the active structure with the circuit components and functions desired by the circuit designer. The pattern defines the circuit elements and the interconnections between the circuit elements such that the resulting semiconductor device has the function.

[0004] 1. Thin Film Composition Silicon (Si) and Germanium (Ge) (both elements of group IV of the periodic table) are common materials used in semiconductor manufacturing. In particular, many substrates are made from silicon. Other substrate materials include sapphire (Al
₂ O ₃ ), gallium arsenide (GaAs), and silicon carbide (SiC).

A material generally used for forming a layer of a semiconductor device (especially an optoelectronic device) is a compound obtained by combining elements of groups III and V of the periodic table (generally referred to as "III-V" compounds). . Group III elements include aluminum (Al), gallium (Ga), and indium (In). Group V elements include arsenic (As), phosphorus (P), and nitrogen (N). The most commonly used III-
The group V compound is probably gallium arsenide (GaAs).

[0006] III-V compounds, collectively referred to as nitrides, are used to make patterned layers. In particular, nitrides have proven useful for light emitting diode (LED) technology.

[0007] Nitriding compounds include group V nitrogen (N),
Contains one or more Group III elements. For example, when only group III gallium is used, the nitride compound is gallium nitride (GaN). However, it is also common to include mixtures of Group III elements. Such compounds are, for example, those obtained as In _x Ga _1-x N or Al _x Ga _1-x N. Here, the subscript (total 1) is used
It has a value that reflects the proportion of Group III elements.

[0008] Many of the materials described above have an active structure.
ructure). As one of many examples, Takeuchi et al.
thodof Fabricating a Gallium Nitride Based Semicon
ductor Device with an Aluminum and Nitrogen Contai
US Patent 5,389,5 entitled `` ning Intermediate Layer ''
No. 71 describes a device having a nitride material crystal (Ga _1-x Al _x ) _1-y In _y N as part of an active structure.

[0009] 2. Thin Film Lattice Properties In general, semiconductor materials take the form of crystal lattices. This indicates that the atoms constituting the material are arranged in a regular pattern such as a row, a plane, and a unit cell. A wide variety of lattice structures are possible. The particular grid formation in a given case is a property of the material making up the grid. Various factors such as the ionic radii of the elements constituting the material influence what kind of crystal lattice structure a given element or compound has.

In particular, when a thin film semiconductor material is deposited on a substrate, a substantially flat thin film substrate interface is formed. For nitrided compounds, the most commonly observed lattice structure is
Hexagonal, ie "hexagonal". FIG. 1 shows the simplest unit cell of a hexagonal crystal lattice. The unit cell has a hexagonal cross-section in a plane (designated "horizontal" for reference) and extends axially in a direction perpendicular to the horizontal plane (designated "vertical"); Take the form of a hexagonal prism.

[0011] Four axes are used to represent a particular location in hexagonal coordinate space. Three of the axes lie in a horizontal plane at an angle of 120 ° to each other, and a ₁ ,
_They are called a ₂ and a ₃ . The fourth axis, denoted by c, is in the vertical plane.

It is a general notation to represent a plane in the coordinate system using the symbol (a ′ ₁ a ′ ₂ a ′ ₃ a ′ ₄ ). In this case, the values a ′ ₁ , a ′ ₂ , a _'3, a' ₄ represents the inverse of the coordinates along the given axis that plane intersects (inverse). When the plane does not intersect the axis (ie when the plane is parallel to the axis)
, The value used is zero. For example, one of the easiest and most convenient planes to define is the upper plane that intersects the hexagon of the upper surface of the unit cell. The plane is commonly called the "base plane" and is parallel to all three a-axes. Therefore, the plane notation of the base surface is (0001).

The gratings that make up thin films in semiconductor devices are often described in terms of such grating parameters. The nitride thin film is generally formed in a hexagonal lattice structure, and its basal plane is oriented parallel to the substrate surface and the interface between the substrate surface and the thin film. Therefore, "a-axis"
Represents any one of three directions parallel to the thin film-substrate interface and 120 ° apart from each other. Also, "c
The "axis" represents the direction perpendicular to the thin film-substrate interface.

The crystal lattice of a thin film layer or the like described in this specification is expressed in terms of parameter values such as “lattice constant” and “coefficient of thermal expansion” (described in detail below). These parameter values are given in relation to the a-axis and c-axis of the hexagonal coordinate system.

However, since many thin film crystal lattice parameters do not differ in the respective a-axis directions, it is not necessary to use two or more axis parameters to represent them. Thus, one parameter is sufficient to describe the interface-parallel properties of the thin film lattice in the direction parallel to the interface. In the case of a hexagonal system such as nitride, only one a-axis parameter is used.

However, in general, the characteristics of the thin film grating in a direction perpendicular to the thin film substrate interface are different from the characteristics in a direction parallel to the interface. For this reason, the c-axis parameter generally has a different value than the corresponding a-axis parameter.

The parameters for the a-axis and c-axis of a thin film lattice are generally the spacing between adjacent atoms of the same type in the lattice structure (ie, Ga-Ga or N
−N separation distance).

One of the parameters is the lattice constant, a measure of the spacing between atoms.

Another parameter is the coefficient of thermal expansion, which relates to the expansion or contraction of the lattice constant as a function of temperature and is given in terms of the change in spacing per temperature change.

As mentioned above, the grating is formed according to the properties of the particular material forming the grating. In particular, the spacing is determined by the ionic radius of the atoms, and thus the values of the a-axis and c-axis parameters.

However, when a thin film is newly formed on a substrate or a previously deposited thin film, the a-axis parameter of the new thin film tends to follow the a-axis parameter of the underlying one. is there. Because of the underlying grid, the a-axis parameters of the new layer will be different from the a-axis parameters that the new layer would have if the underlying grid were not present. This places stress on the new thin film.

Furthermore, if the a-axis parameter of a newly deposited thin film is affected by the underlying lattice structure, the c-axis parameter of the thin film is also affected. This again imposes stress on the new thin film lattice.

A thin film layer is said to be "in registry" if its grid is laid out so that it can coexist with the grid below it. That is, the atomic plane (at
omicplane) is continuous through the interface between the two materials and is free of strain. If the lattices are different, the thin films cannot stay in alignment without stress.
That is, the atoms that make up the thin film lattice may be squeezed closer together or pulled farther apart, resulting in a loss of registry stress.

A lattice that has been stressed to such an extent that it cannot maintain a matching state tends to contain dislocations (a kind of lattice structural defect). If there is a sufficiently large a-axis lattice parameter difference between the substrate and the thin film, the thin film lattice will relieve stress due to dislocations (actually due to "row-out" or "extra-row insertion" of atoms). This causes the next row of atoms in the thin film lattice to be aligned with the substrate lattice. Dislocations are inevitable to some extent at the lattice interface in the mismatched state, but it is desirable to minimize them. Due to the large mismatch between the commonly used nitride material and the substrate, dislocations occur very frequently in the nitride thin film layer.

In some cases, randomly arranged point defects occur in the form of a lattice structure. The point defect may be such that the lattice position where the atom should exist is a vacancy or that the impurity atom occupies one of the lattice matrix elements.

3. Thin Film Fabrication Technique A common technique for depositing layers is called "epitaxy." That is, the layers are described as being "epitaxially" deposited, and the layers themselves are described as "epitaxial" layers. In this technique, a layer of material is deposited from the surrounding environment onto the substrate surface, essentially atomically. The material forming the epitaxial layer crystallizes in a lattice according to its own properties or the properties of the underlying layers as described above.

Examples of such techniques include metalorganic vapor phase epitaxy, molecular beam epitaxy, and hydride vapor phase epitaxy (in contrast, non-epitaxial techniques place a pellet of material on a substrate). Then, the device is heated to fuse the pellet to the substrate surface).

Generally, all epitaxy and other types of fabrication steps are performed at temperatures several hundred degrees Celsius (Celsius) above room temperature, but the temperature can be quite significant depending on the type of processing step and the type of material being deposited. It can fluctuate.

One of the problems in developing the fabrication process is to order the steps so that the temperatures required for subsequent steps do not compromise the results of the preceding steps.

Description of Problems to be Solved In developing a semiconductor fabrication process, there are various problems that must be addressed to ensure that the semiconductor devices produced by the fabrication process have adequate quality. In general, the term "quality" when used in semiconductor fabrication refers to the proper functioning and reliability of the fabricated semiconductor device.

In order to produce a high quality semiconductor, the various layers need to adhere to each other and to the substrate. This is necessary for both good electrical properties and good mechanical structure.

The quality of a semiconductor device is related to the state of a crystal lattice constituting the semiconductor device. Defects in the lattice structure can be detrimental to device quality. Thus, when stress of the lattice is applied to a thin film layer fabricated as described above, it is necessary to limit and at least control the effect of the stress on the thin film lattice.

A particular complication when dealing with nitride epitaxy is cracking. Cracks occur when the epitaxial thin film is pulled under tension, ie, when subjected to the stresses described above. Generally, the crack will be perpendicular to the thin film-substrate interface.

There are several possible reasons for such cracks, as follows.

(I) Mismatch of lattice between substrate and thin film due to difference in lattice structure between substances constituting substrate and thin film. (Ii) Mismatch of thermal expansion coefficient between materials constituting substrate and thin film. Matching (iii) High doping level of the material (iv) Intentional compositional adjustment, i.e. lattice mismatch, due to a change in the chemical composition of the fabrication material intentionally introduced during the growth of the nitride device.

For example, at typical growth temperatures above 1100 ° C., the growth of an AlInGaN layer without the benefit of a buffer layer results in a mosaic-assembled hexagonal nucleus.
lei). Such a layer will exhibit a very rough morphology and a very high background donor concentration. As a result, the layer has the properties (i) and (iii) described above and is susceptible to cracking.

Mismatch in Lattice and Coefficient of Thermal Expansion Semiconductor materials are characterized by the lattice constant, the mathematical characterization of the material's crystal structure. Also, like other materials, semiconductor materials have a coefficient of thermal expansion, a measure of how much the material expands or contracts in response to temperature changes.

It is desirable that the layers adjacent to each other have a lattice structure that is the same as each other or coexist with each other for good adhesion. When the lattice structures cannot coexist with each other, the adhesion becomes insufficient, the layers are peeled off, and the electrical characteristics are deteriorated.

Adjacent layers should also have the same thermal expansion as possible so that the expansion of one layer is not greater than the expansion of the other layer as a result of a temperature change and the layers do not delaminate. Should have a coefficient. This is especially important. This is because the fabrication of semiconductor devices is generally performed at much higher temperatures than their storage and use. When the completed semiconductor device is cooled to room temperature, it will undergo significant heat shrinkage.

Conventional LED Structures: Buffer Layer Nitride-based LEDs generally comprise (i) a substrate, (ii) a nucleation or buffer structure, and (iii) an active structure. The present invention relates to a buffer structure. Therefore, the drawings showing the device structure include both an overall view showing the buffer structure as a single layer and an “enlarged view” showing the details of the structural configuration of the buffer structure with the single-layer buffer structure as the center. It is included.

In the drawings of the prior art and the present invention, typical layer thicknesses are shown in Angstroms (). These values, or other values that would be implied to those skilled in the art, can be used.

Also, in the following description, the layers are described as being "disposed" with respect to each other. The term "arrangement" is not intended to impose any structural restrictions, except that one layer is fabricated or positioned on another layer. This term is used to refer to any fabrication technique based on this specification, either known to or deemed appropriate by one of skill in the art.
Encompasses the structure generated by The only limitation expressed or implied with respect to this specification is, as already mentioned, with respect to the relatively low and high temperatures for the buffer layer and the active layer epitaxy.

Since the present invention is applicable to LED technology, a somewhat more detailed description of the active LED structure is given as a typical example. The LED active structure includes an active layer and a contact between an n-type layer and a p-type layer. It will be understood, however, that these components are not essential to the invention and are merely exemplary.

FIG. 2: Conventional device FIG. 2 shows a conventional semiconductor device, that is, a general-purpose nitride LED.
The outline is shown. The substrate is designated by reference numeral 2 and the nucleation or buffer structure is designated by reference numeral 4. The substrate 2 can be made of sapphire (Al ₂ O ₃ ), silicon carbide (SiC), or the like. The active structure is indicated generally by the reference numeral 6.

In the active structure 6, circuit elements, interconnections and the like are formed. The details of the active structure are not essential to the present invention, and thus the active structure will not be described in further detail except for the example given here.

A typical LED active structure shown in this case 6
Has an active region between the p-type layer 10 and the n-type layer 12.
These layers 10, 12 include circuit elements, interconnect elements, etc., and have contacts 14, 16, respectively. "Active area"
The term is commonly used in the field of LEDs. As used herein, the term "active structure" can be included in layers 8, 10, 12 and contacts 14, 16, as well as other devices that use buffers conventionally or according to the invention described herein. And other circuit elements and structures.

One effective method conventionally used to control cracks, morphology, and background carrier conductivity is the insertion of a buffer structure 4. The buffer structure 4 includes a layer called a buffer layer or a nucleation layer (a term used as a synonym).

For devices made on sapphire substrates, the buffer layer is typically deposited at 400-900 ° C.
If the substrate is silicon carbide (SiC), the deposition of the buffer layer may be performed at a higher temperature (e.g., above 900C). Nevertheless, these temperatures are generally lower than those used for other types of deposition steps, such as epitaxy, but do not preclude deposition at temperatures above those used for other deposition steps.

A nucleation or buffer layer is deposited prior to the growth of additional layers such as active structure 6. The layers that make up the active structure 6 are often deposited at a much higher temperature than that used for the buffer layer. The quality of an additional layer, such as an epitaxial nitride thin film, improves dramatically when a buffer layer is created below the additional layer.

Conventionally, the buffer layer is composed of a binary compound AlN and GaN.
Or some AlGaN composition intermediate to these two binary compounds. More precisely, the intermediate composition is represented by AlGa _1-x N, where x is a value between 0 and ₁ .

The insertion of such a low temperature layer overcomes significant differences in (i) lattice parameters, (ii) thermal expansion, (iii) surface energy, and (iv) crystal structure between the sapphire substrate and the nitride epitaxial layer. Means are provided. However, such a conventional buffer layer has the following limitations.

Doping and composition adjustment (compositional m
odulations In typical nitride-based devices, the thin film layers are heavily doped. For a typical optoelectronic device, the dopant concentration often exceeds 10 ¹⁸ to 10 ¹⁹ .

Also, typical nitride-based devices will exhibit some compositional heterointerface. Nearly all electronic and optoelectronic devices are composed of layers of different compositions, one composition being deposited on top of another. The heterointerface is the interface between two such different composition layers. For example, layers of GaN, AlGaN, and InGaN having different compositions, conductivity types, and thicknesses are deposited to have direct contact surfaces with each other, resulting in optoelectronic devices such as LEDs.

Doping and heterointerfaces both affect lattice parameters. Nitride and common substrate (Si
FIG. 3 shows data on lattice parameters and expansion coefficients of the a-axis and c-axis for C and sapphire).

Cracking presents a significant problem when the GaN layer is doped n-type with silicon. Si atoms replace Ga atoms in the crystal lattice.
Si has an ionic radius 30% smaller than Ga. As a result, the Si atoms are `` too small '' relative to the space occupying the lattice, and the extra space around the Si atoms creates stress and strain fields in the crystal, which weakens the lattice. Become.

Cracks are also a problem when layers of different compositions are deposited on one another. Due to the extremely stiff elastic constants exhibited by the III-V nitrides, if the overlying layer has a smaller a-axis lattice parameter than the underlying layer on which it is grown, , Cracks are particularly troublesome.

Furthermore, a heterostructure composed of a nitride layer generally exhibits a matching state along the a-axis (that is, an axis parallel to the interface of the substrate thin film). Thus, if the associated a-axis parameter of one layer is smaller than the underlying layer on which the layer is to be grown, a tensile stress will be induced in the layer to keep the interface aligned. You.

Conclusions The problems associated with lattice and thermal mismatch can be adequately addressed by utilizing existing nucleation layer technology and controlling the heating and cooling conditions associated with growth,
Cracks due to doping and composition variations cannot be resolved by such methods.

Thus, there is still a need for a semiconductor device and a method of fabricating the same that overcomes the problem of cracking due to such doping and composition variations.

[0060]

Accordingly, it is an object of the present invention to provide a III-V nitride semiconductor device devised to achieve high quality layers and devices, and doping in the layers and devices. And the problem of cracks caused by compositional variations.

It is another object of the present invention to provide a semiconductor device designed to overcome all of the cracking problems described above.

[0062]

According to the present invention, there is provided a semiconductor device having a substrate, an active structure, and a buffer structure between the substrate and the active structure. Is done.

The cushioning structure has one or more layers. In particular, in a multilayer structure, at least one of the layers (preferably a layer directly deposited on the substrate) is composed of a III-V nitride compound, Is completely or partially composed of indium. According to the invention, the layer containing indium acts as a buffer layer.

Indium-Containing III-V According to the Invention
It has been found that the nitride buffer layer advantageously reduces cracking due to the adjustment of the strain present in its active structure.

The present invention is advantageous for use in AlInGaN epitaxy. By nucleating the nitride thin film on these buffer layers, stress and cracks are reduced due to relaxation by the layer containing InN, and therefore, it is possible to increase the flexibility of composition and doping adjustment. Become.

Since the electrical and optical properties of the nitride are determined by the stresses and strains present, it is possible to adjust these properties by controlling the composition and thickness of the nucleation layer.

It is also possible to make the group III material completely indium and the buffer layer compound to be InN. More generally, the buffer layer can be any suitable aluminum gallium indium nitride intermediate. Such intermediates are generally Al _x In _y Ga _{1 -xy} N (0 ≦ x ≦ 1 and 0 <
y ≦ 1).

Specific amounts of various Group III elements will be described below in connection with the description of various embodiments of the present invention. Experiments have demonstrated that these particular ratios result in an effectively functioning buffer structure.
However, the present invention has been widely considered to include other compositions and thicknesses.

In addition, high quality InGaN layers can be grown at temperatures much lower than those used for GaN, AlN, and AlGaN (at temperatures below 1000 ° C. and below 800 ° C.). , InN and InGaN-containing buffer layers exhibit advantageous high structural qualities that cannot be achieved with conventional fabrication techniques.

Further, according to the present invention, the buffer structure has a cap layer on the upper part. The cap layer is made of Ga
It can be N, AlN, or a suitable AlInGaN intermediate. In general, III containing a given proportion of indium
The -V nitride buffer layer can be covered with a III-V nitride cap layer containing a lower proportion of indium;
In this case, the ratio is selected to be suitable for the temperature of the subsequent epitaxy step.

The cap layer can be used to ensure that the cap holds the rest of the buffer structure in place during the fabrication process, where the step of depositing the active structure at a high temperature follows the deposition of the buffer structure, and the adverse effects caused by the high temperature. The additional advantage is that the remaining part is protected from

In addition, subsequent changes in the strain state caused by using a multi-step nucleation layer will also have a beneficial effect on the electrical properties and performance of the LED device according to the present invention.

[0073]

DETAILED DESCRIPTION OF THE INVENTION In accordance with the present invention, a low temperature nucleation layer is comprised of several distinct layers having different compositions. In particular, in a multilayer structure, at least one of the layers (preferably a layer deposited directly on the substrate)
AlInGaN composed of nitride containing indium
Serves as a buffer layer for use in epitaxy.

In general, the invention can be implemented in two ways. They both deposit a buffer layer of a nitride compound containing indium directly on the substrate. In contrast, conventional buffer layer compounds have only Group III aluminum or gallium. The difference between the two ways of practicing the invention is that the buffer layer, in one case,
It is InN (comprising only Group III indium), in the other case a compound containing indium and another Group III element (preferably gallium). For example, the compound can be represented by Ga _x In _1-x N (0 <x <1).

InN melts around 1100 ° C., which is close to the temperature used for GaN epitaxy. However, because the bonds between the indium and nitrogen atoms are relatively weak with respect to each other, the InN lattice may decompose at that temperature, or even at somewhat lower temperatures. For example, In
Consider the case where after the deposition of the N buffer layer, a subsequent step of GaN epitaxy is performed to form a layer of the active structure. Because the GaN epitaxy step is performed at a relatively high temperature, the underlying InN layer melts or “relaxes”. Relaxation of this underlying InN buffer layer reduces the tendency for cracking by providing some degree of compliance between the substrate and the thin film.

Because of the relatively low melting point of InN and other indium compounds used in accordance with the present invention, a cap layer (preferably a GaN
Layer) has been found to be desirable. As the layer containing indium relaxes during the high temperature epitaxy step, the InN layer is confined by a cap layer made of a material that remains solid in that temperature range. For simplicity, the structure described herein will be referred to as an InGaN / GaN buffer layer, with the understanding that the structure described is actually an InGaN buffer layer, for example, under a GaN cap layer. . The buffer layer and the cap layer are both part of the overall buffer structure between the substrate and the active structure.

Embodiments There are many possible embodiments of the present invention. Many of the embodiments can be well categorized into several types. First, a basic embodiment of the present invention will be described,
Next, other types of embodiments will be described as modifications of the basic embodiment or as refinements of the basic embodiment.

First Embodiment: Single Buffer Layer (FIG. 4) FIG. 4 shows the invention in its simplest embodiment, with a single buffer layer 16 similar to FIG. However, the difference is that the buffer layer 4 is made of a nitride compound containing indium.

In general, the indium-containing III-V nitrides used in accordance with the present invention are of the following type:

Al _x In _y Ga _1-xy (0 <y ≦ 1, 0 ≦ x ≦ 1) That is, this compound can contain aluminum and / or gallium in addition to indium.

In addition to this basic buffer structure, many embodiments of the present invention have a buffer structure that includes multiple layers, some or all of which function as a buffer layer. Some of such embodiments are categorized into types, and each type of embodiment will be illustrated and described.

Embodiment of the First Kind: Multilayer In the buffer structure shown in FIG. 5, a first buffer layer 18 is deposited directly on the substrate, on which a second buffer layer 20 is deposited. Is deposited. As shown in the chemical formula of FIG.
Although nitride compounds containing indium, the exact proportions of Group III elements for these two layers are different.
The first layer 18 can be InN without Al or Ga. On the other hand, the group III portion of the second layer 20 can be pure Al or pure Ga instead of pure indium. In any case, the second layer 20
Contains less indium than the first layer 18.

FIG. 6 shows a buffer structure similar to that of FIG. 5, but differs in that a third buffer layer 22 is deposited on the second buffer layer 20. As shown by the chemical formula in FIG.
The buffer layer 18 contains some indium, the second buffer layer 20 contains less indium than the first buffer layer 18, and the third buffer layer 22 contains less indium.

FIGS. 5 and 6 show the first embodiment of the present invention.
Can be considered as embodiments of this type. This first
Embodiments include a plurality of buffer layers containing indium. While embodiments of two and three layer buffer structures have been shown, more buffer layers can be used.

Embodiments of this type are common in that all layers are devised to act as buffer layers by relaxation at the temperature of subsequent fabrication steps such as epitaxy. Other types of embodiments described below will include yet another type of layer within the cushioning structure.

Second Embodiment: Cap Layer: FIG.
FIGS. 7 to 10 show a second embodiment of the present invention. In these embodiments, the buffer structure will include a cap layer deposited on one or more buffer layers.

In FIGS. 7 and 8, the buffer structure is given by a general chemical composition. The structures of FIGS. 9 and 10 correspond to FIGS. 7 and 8, respectively, but differ in that they show examples of devices already manufactured and used.

It is desirable to provide a cap layer when a high-temperature processing step such as an epitaxy step performed after manufacturing the buffer structure is included in the entire manufacturing process. The previously deposited indium-containing buffer layer relaxes at elevated temperatures. The cap layer advantageously confine the indium-containing material in place (see FIGS. 7 and 8). Thus, the cap layer is made from a III-V nitride material that is more resistant to high temperatures in subsequent fabrication steps. Gallium nitride (FIGS. 9 and 10) is a preferred cap layer material, but can also contain indium and other Group III elements, depending on the temperature of the epitaxy step.

Referring now to FIG. FIG. 1 shows a first embodiment of the type having a cap layer. The buffer layer 24 containing indium is the same as the general buffer layer used above.
It is covered by a cap layer 26 represented by the formula of III-V nitride. The buffer layer 24 containing indium can have any of the above chemical formulas. Generally, cap layer 26 will contain a smaller amount of indium, selected to reduce its tendency to relax at the temperature of subsequent fabrication steps.

However, in the particular embodiment of FIG.
The indium content in 24 is relatively low (maximum indium content: 20%), the remainder being gallium.
Although the applied thickness has been successfully utilized, the precise thickness provided is not critical to the invention and other thicknesses can be used. The thickness data described below provides a detailed indication of the performance of the structure thus produced. This formula is suitable for devices where an active structure will be created at a high enough temperature that the buffer layer will still relax even if the amount of indium is relatively modest.

FIG. 8 shows another embodiment of the cap layer, in which two buffer layers 28, 30 are deposited under the cap layer 32. Also in this case, the buffer layers 28 and 30 and the cap layer 32 are given by a general chemical composition formula. The first buffer layer 28 (which is located directly on the substrate) has a high indium content and produces good relaxation. The second buffer layer 30 includes a mixture of Group III elements having a lower indium content.

FIG. 10 shows a more detailed structure.
In this case, a pure InN layer 28 is provided to maximize relaxation and stress release, and an intermediate layer 30 with less indium is provided to obtain better stability at elevated temperatures. A GaN cap layer 32 is provided to confine the lower layers 28, 30 at high temperatures. The GaN cap layer has sufficient resistance to such a high temperature fabrication step. In the particular embodiment shown, the intermediate layer 30 is indium gallium nitride, where again the indium content provides a good balance between relaxation and structural stability at high fabrication temperatures of the active structure. As obtained, it is up to 20%.

FIG. 11 shows experimental data of the embodiment of FIG. 9 in the form of “SIMS depth profile”. The acronym SIMS stands for Secondary Ion Mass Spectrometry (Secondary I
on Mass Spectrometry). SIMS plots plot the number of secondary ions as a function of depth below the surface of the device.

This SIMS depth profile is based on a single n-type (Si doped) Ga grown on the nucleation layer shown in FIG.
FIG. 4 is a graph showing N and In traces from the SIMS profile of the N layer. The InGaN buffer layer is in contact with the sapphire substrate at a depth of about 0.8 μm.

For two elements, nitrogen and indium, the number of ions is indicated. The curve for nitrogen is constant over most of the area of the graph. This is intuitively relevant since most of the area corresponds to the nitride layer. The thin film contains about 50% nitrogen and the substrate does not contain any nitrogen. Therefore, the number of nitrogen drops sharply about 0.8
The μm depth is the interface between the substrate and the thin film.

Since the graph is prepared on a logarithmic scale, the peak of the indium curve at a depth of 0.00 μm to about 0.7 μm is merely noise, and the magnitude of the indium peak around 0.8 μm is approximately equal to that of the peak. 1/1000. The prominent peak for indium at 0.8 μm corresponds to the buffer layer and indicates that indium is incorporated and retained in the structure.

Since indium was supplied for thin film growth in the ambient environment only during the growth of the InGaN portion of the InGaN / GaN buffer structure, the indium signal was obtained at the position of the InGaN portion of the multilayered buffer layer. And presence. Also, the fact that the indium signal peaks at the same depth as the nitride signal drops,
The presence of indium at the substrate interface is further confirmed.

The peak of indium at the substrate-thin film interface is also due to the cap layer (GaN in this case)
This indicates that the buffer layer is held at a predetermined position.

FIG. 12 shows the measured values of Van der Pauw Hall,
That is, it is a table showing measured values of the conductive characteristics of the device layer related to the operation of the semiconductor device. The devices from which these results were obtained each comprise an active layer GaN: Si (ie a layer of Si-doped GaN) of similar thickness and doping level above each production layer. Two sets of values are shown, one set is for a conventional GaN nucleation layer as shown in FIG. 2 and the other set is as shown in FIG.
Values for a device according to the invention with an InGaN / GaN layer.

A notable difference is that the electron mobility, which is preferably as high as possible to achieve the highest conductivity and the lowest input drive current in the layer, is due to the InGaN / GaN buffer of FIG. This is about 5% higher in the case of the layer than in the case of the conventional sample (FIG. 2) grown on the GaN buffer layer.

The total resistivity, which is preferably as low as possible, is lower for devices according to the invention than for conventional devices. This advantageous difference may be due to either a beneficial change in the strain state or a reduction in the dislocation and / or point defect density of the GaN: Si overlayer, and according to the present invention, the InGaN / GaN composite nucleation. This is the result of using layers.

Third Type Embodiment: Buffer Substructure: FIGS. 13 to 15 The third type of embodiment is generally characterized as having a series of buffer structures. Each substructure is the same or similar to other substructures. As an example of a lower structure that is repeated in this type of embodiment, it is possible to use the buffer structure in the previously described embodiment.

FIG. 13 shows a buffer structure including two substructures 34 and 36, wherein the two substructures 34 and 36 are:
An indium nitride buffer layer (38 and 40) and a gallium nitride cap layer (42 and 44) are provided, respectively. That is, when the cap layer buffer structure of FIG. 9 is repeated twice, the structure of FIG. 13 is obtained as a result.

In an embodiment of this type, the invention will be described and claimed with reference to a buffer undercarriage. FIG.
Here, for example, the buffer substructures 34 and 36 are shown as a two-layer substructure.

Each layer in the lower structure will be described and claimed as a lower structure layer. Here, FIG.
See again. Two indium nitride buffer layers 38,4
0 is referred to as a lower structure buffer layer, and the two gallium nitride cap layers 42 and 44 are referred to as lower structure cap layers.

Next, reference is made to FIG. In this figure, a buffer structure including three lower structures 46, 48, 50 is shown. The three substructures 46,48,50 are composed of an indium gallium nitride buffer layer (52,54,56) and a gallium nitride cap layer (58,6,6).
0,62) respectively, and is a lower structure of the cap layer of the type of FIG. Although the buffer layers are shown as being identical (ie, having the same thickness and composition for a given value of x for all layers), the composition can vary from buffer layer to buffer layer.

Finally, FIG. 15 shows a buffer structure with an infinite number of substructures. The figure shows the lower structure at the bottom.
64 and an upper substructure 66 are shown. Between the bottom substructure 64 and the top substructure 66 represents any desired number of additional substructures.

Each of the lower structures of FIG. 15 has two lower structure buffer layers. The chemical structure of the lower structure buffer layer is represented by the above-described general indium-containing III-V nitride formula.

In each lower structure, the lower lower structure (70, 7
2) (including the lower layer of the first substructure immediately adjacent to the substrate), the first (relatively large) amount of indium is contained, the amount of index parameters y ₁ values Related to The amount can be 100% of the composition of the material by the group III element, that is, the material can be indium nitride. Second of each substructure
The lower structure layer (74, 76) has a smaller amount of indium.

Also in this case, the lower layer of each lower structure
The same formula and the same x ₁ , y ₁ parameters are used,
These equations can be different for each substructure. The same applies to the upper layers of the substructure.

Other Embodiments As will be apparent from the above description of the invention, it is also possible to employ various other configurations. For example, it is also possible to use several three-layer substructures, each with the three-layer buffer structure of FIG. In addition, the same lower structure as that shown in FIG. 8 can be used except that the chemical formulas of the lower structure buffer layers of the various lower structures are different and the thicknesses are also different.

In general, a layer having a given chemical composition
Depending in part on its chemical composition, it can act as a buffer or cap layer. One layer of material
The layer acts as a cap layer if it remains substantially rigid and rigid at the elevated temperatures of subsequent fabrication steps. This assumes, of course, that there is a layer of material that relaxes or melts at high temperatures below this layer. Also, the stronger the tendency of a given layer to relax, the better it acts as a buffer layer. Finally,
Just how high the high temperature reaches can determine whether a layer of a given composition acts as a buffer layer or a cap layer.

In most cases, the growth of the buffer layer is started at a much lower temperature than that used for nitride thin films by growing the buffer layer directly on the sapphire substrate. Typically, the buffer layer deposited on the sapphire layer is deposited at 400-900C, while the rest of the structure is deposited at 700-1200C. Also, a cap layer is formed on the composite nucleation layer to provide protection during higher temperatures for the remainder of the growth process. The overall nucleation layer thickness can be any value deemed appropriate by those skilled in the art. However, the desired thickness was about 250-300.

General Notes on Fabrication Techniques The buffer and cap layers should be at 200-1000 ° C., preferably 400-1000 ° C.
Grow in a temperature range of 600 ° C. Other layers need not be grown at this same temperature. It is also possible to change other conditions. For example, it is possible to change ambient conditions such as the growth atmosphere pressure.

The ambient growth atmosphere generally contains ambient gas that is non-reactive (otherwise does not directly contribute to the layer formation process). Such gases include Ar, He, H ₂ ,
A mixture of N ₂ , H _2, and N ₂ may be used. Such ambient gases and the like can be utilized in various ratios and combinations in a manner known to those skilled in the art.

Finally, the group III (and group V) to be deposited
If the elements are supplied in an ambient atmosphere, the ratios and amounts can be varied, including the ratio of group V to group III.

Experimental Data For certain embodiments of the several buffer structures illustrated and described above, LED device growth was also performed. FIG. 16 shows performance data of the LED according to each structure.

The light output values are standardized (s) using a prior art optoelectronic device such as the device of FIG.
It is shown as a gain factor for a tandardized run).
Standardized ones grown in the same time frame have an external quantum efficiency of 5-7% and emit light in the wavelength range of 485-505 nanometers (nm). The advantages of utilizing the invention described herein are apparent because it is desirable to produce LED devices that deliver the highest possible light output.

It should be noted that different embodiments produce light wavelengths that vary by more than about 15 nm (compared to wavelength differences between adjacent colors in the visible spectrum on the order of 50 nm). Those skilled in the LED art will understand fabrication techniques that can be utilized in connection with the present invention to precisely tune light wavelengths to desired values.

Depending on the amount of distortion generated in the device structure,
Previous studies have shown that the composition of the active or light emitting region of the device structure may be altered. Since the composition of the active layer determines the emission wavelength, the wavelength shift observed in this case indicates a change in the distortion state of the device structure.

In all cases, the light output and efficiency of the device are comparable to or even exceed conventional LED devices grown on GaN nucleation layers during the same period. In the specific case shown in FIG. 9, the nucleation layer In
Adjusting the mole fraction of InN in the GaN portion can also affect device performance.

As can be seen from the data shown in FIG. 17, for the LED device according to the present invention, the light output is increased compared to the prior art device (InN mole fraction of 0.00). The wavelength of the generated light is 100 InG of the buffer layer.
It is affected by the composition change in the aN part (FIG. 9). The “0.00” in the heading of FIG. 17 represents the performance of the prior art device of FIG. As with the data shown in FIG. 16, the data in FIG. 17 also shows the improvement in performance and the change in distortion state obtained according to the present invention.

When the thickness of the InGaN layer is changed, similar shifts in light output and wavelength are observed. As in the case above where the electrical transfer characteristics were measured, these results are:
It can directly correlate with the improved strain state or microstructure provided by employing a nucleation layer according to the present invention.

In the following, exemplary embodiments comprising combinations of various constituent elements of the present invention will be described.

[0125] 1. A semiconductor device, comprising: a substrate (2)
And a buffer structure (4) directly disposed on the substrate (2), wherein the first buffer layer (16) directly disposed on the substrate (2).
A buffer structure (4), wherein the first buffer layer (16) is formed from a first indium-containing nitride compound.
A semiconductor device comprising: an active structure (6) disposed on the buffer structure (4).

2. The first buffer layer (16) is made of Al _x In _y Ga
_2. The semiconductor device according to item 1, wherein the semiconductor device is formed from a first indium-containing nitride compound selected from the group consisting of _1-xy N (0 <y ≦ 1, 0 ≦ x ≦ 1).

[0127] 3. The buffer structure includes the first buffer layer (1).
8) further comprising a second buffer layer (20) disposed thereon;
2. The semiconductor device according to item 1, wherein the second buffer layer (20) is formed from a second indium-containing nitride compound.

4. The buffer structure further comprises a cap layer (26), wherein the second layer (26) comprises the first buffer layer (26).
(24) The semiconductor device according to (1) above, wherein the semiconductor device is formed from the second indium-containing nitride compound disposed thereon.

5. The semiconductor device according to claim 4, wherein the cap layer (26) is formed of gallium nitride.

6. 2. The semiconductor device according to claim 1, wherein said buffer structure further comprises a first buffer layer lower structure (34).

7. The first buffer layer substructure (34) is formed from an indium-containing nitride compound.
(38), wherein the first buffer layer is included in a substructure buffer layer of the first buffer layer substructure (34),
7. The semiconductor device according to the above item 6.

8. The first buffer layer substructure (34) is formed from an indium-containing nitride compound.
7. The semiconductor device according to claim 6, comprising: (38) and a lower structure cap layer (42) disposed on the lower structure buffer layer (38).

9. The semiconductor device according to claim 8, wherein the lower structure cap layer (42) is formed of gallium nitride.

10. The first buffer layer lower structure (64) is disposed on a first lower structure buffer layer (70) formed of a first indium-containing nitride compound and on the first lower structure buffer layer (70). 6. A second lower structure buffer layer (74) formed from a second indium-containing nitride compound provided.
A semiconductor device according to claim 1.

11. 7. The semiconductor device according to claim 6, wherein the buffer structure comprises a second buffer layer lower structure (36) disposed on the first buffer layer lower structure (34).

12. Each of the first and second buffer layer lower structures is disposed on the lower structure buffer layer (38, 40) formed of an indium-containing nitride compound and the lower structure buffer layer (38, 40). And a lower structure cap layer (42, 44).
12. The semiconductor device according to the above item 11.

13. The first and second buffer layer substructures (3
12. The semiconductor device according to item 11, wherein the lower structure cap layer (42, 44) in each of (4, 36) is formed of gallium nitride.

14. The first buffer layer lower structure (64) includes a lower structure buffer layer (70) formed of a first indium-containing nitride compound, and the second buffer layer lower structure (6).
12. The semiconductor device according to item 11, wherein 6) includes a lower structure buffer layer (72) formed from a second indium-containing nitride compound.

15. The first and second buffer layer lower structures (6
4,66) are respectively formed on the first lower structure buffer layer (74,76) and the first lower structure buffer layer (74,76) formed from the first indium-containing nitride compound. 12. The semiconductor device according to item 11, further comprising a second lower structure buffer layer formed of a second indium-containing nitride compound.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a crystal lattice and axes related to the lattice.

FIG. 2 is an explanatory view showing an outline of manufacturing a conventional nitride LED.

FIG. 3 is a table showing parameter values for nitrides and substrate materials.

FIG. 4 shows a nitride according to a first basic embodiment of the invention.
It is explanatory drawing which shows the outline | summary of manufacture of LED.

FIG. 5 is an explanatory view showing an outline of manufacturing a nitride LED according to a first type of embodiment of the present invention having a plurality of buffer layers.

FIG. 6 is an explanatory view showing an outline of manufacturing a nitride LED according to a first type of embodiment of the present invention having a plurality of buffer layers.

FIG. 7 is an explanatory view showing the outline of the fabrication of a nitride LED according to a second embodiment of the present invention having a cap layer.

FIG. 8 is an explanatory view showing an outline of manufacturing a nitride LED according to a second embodiment of the present invention having a cap layer.

FIG. 9 is an explanatory view showing the outline of the fabrication of a nitride LED according to a second embodiment of the present invention having a cap layer.

FIG. 10 is an explanatory view showing an outline of manufacturing a nitride LED according to a second embodiment of the present invention having a cap layer.

FIG. 11 is a graph called “SIMS depth profile” showing the characteristics of the device of FIG. 9;

FIG. 12 is a table showing measured values from the device of FIG. 9;

FIG. 13 is an illustration outlining the fabrication of a nitride LED according to a third type of embodiment of the present invention having a repeating (or nearly repeating) substructure in a buffer structure.

FIG. 14 is an illustration outlining the fabrication of a nitride LED according to a third type of embodiment of the present invention having a repeating (or nearly repeating) substructure in a buffer structure.

FIG. 15 is an illustration showing an overview of the fabrication of a nitride LED according to a third type of embodiment of the present invention having a repeating (or nearly repeating) substructure in a buffer structure.

FIG. 16 is a table showing performance data from some devices according to the present invention.

FIG. 17 is a table showing further performance data.

[Explanation of symbols]

 2 Substrate 4 Buffer structure 6 Active structure 16 First buffer layer 18 First buffer layer 20 Second buffer layer 24 First buffer layer 26 Cap layer 34 First buffer layer lower structure 36 Second buffer layer lower Structure 38 Lower Structure Buffer Layer 42 Lower Structure Cap Layer 44 Lower Structure Cap Layer 64 First Buffer Layer Lower Structure 66 Second Buffer Layer Lower Structure 70 First Lower Structure Buffer Layer 72 Lower Structure Buffer Layer 74 Second Lower Structure buffer layer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Changhua Chen 95129, California, United States of America, Albany Circle Number 102, 4865 (72) Inventor Warner Goetz 95303, Palo Alto, Gee, California 95303 United States of America Middlefield Road 3909 (72) Inventor Gina El Kristiansund California, United States 94086, Sunnyvale, Apartment 122, North Wolf Road 355 (72) Inventor Chipin Kuo, California, United States of America 95035, Milpitas, Meadowland Drive 185

Claims (1)

[Claims] A substrate (2) and a buffer structure (4) directly disposed on the substrate (2), wherein the first buffer layer (1) is disposed directly on the substrate (2). 16), wherein the first buffer layer (16) is formed from a first indium-containing nitride compound, and is disposed on the buffer structure (4). A semiconductor device comprising: an active structure (6).