TWI398016B - Photoelectric semiconductor device having buffer layer of iii-nitride based semiconductor and manufacturing method thereof - Google Patents
Photoelectric semiconductor device having buffer layer of iii-nitride based semiconductor and manufacturing method thereof Download PDFInfo
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本發明係關於一種具三族氮化合物半導體緩衝層之光電半導體元件及其製造方法,尤係關於一種以三族氮化合物半導體為緩衝層之光電半導體元件。 The present invention relates to an optoelectronic semiconductor component having a three-group nitrogen compound semiconductor buffer layer and a method of fabricating the same, and more particularly to an optoelectronic semiconductor component having a tri-group nitrogen compound semiconductor as a buffer layer.
隨著發光二極體元件之被廣泛應用於不同產品,近年來製作藍光發光二極體之材料,業已成為當前光電半導體材料業重要的研發對象。目前藍光發光二極體之材料有硒化鋅(ZnSe)、碳化矽(SiC)及氮化銦鎵(InGaN)等材料,這些材料都係寬能隙(band gap)之半導體材料,能隙大約在2.6eV以上。由於氮化鎵系列係直接能隙(direct gap)之發光材料,因此可以產生高亮度之照明光線,且相較於同為直接能隙之硒化鋅更有壽命長之優點。 As the light-emitting diode components are widely used in different products, the materials for blue light-emitting diodes have been produced in recent years, and have become an important research and development object of the current optoelectronic semiconductor materials industry. At present, materials for blue light-emitting diodes include zinc selenide (ZnSe), tantalum carbide (SiC), and indium gallium nitride (InGaN). These materials are wide band gap semiconductor materials with a gap of about Above 2.6eV. Since the gallium nitride series is a direct gap luminescent material, it can produce high-intensity illumination light, and has the advantage of longer life than zinc selenide which is also a direct energy gap.
早期針對三族氮化合物或氮化鎵之研發方向,係著重於如何去形成高品質的氮化鎵薄膜。但由於缺乏與氮化鎵在晶格常數(lattice constant)及膨脹係數匹配之基材材料,而且必須在極高溫度下形成薄膜,所以於此等條件下要成長高品質的氮化鎵晶體極為不易。 Early research and development for tri-family nitrogen compounds or gallium nitride focused on how to form high-quality gallium nitride thin films. However, due to the lack of a substrate material that matches the lattice constant and the expansion coefficient of gallium nitride, and the formation of a thin film at a very high temperature, it is necessary to grow high-quality gallium nitride crystal under such conditions. Not easy.
S.Yoshida等人於1983年以藍寶石(sapphire)為基材,先以高溫成長一層氮化鋁(AlN)為緩衝層,接著在上面成長氮化鎵膜層,如此才得到品質比較好之晶體。後來I.Akasa與H.Amano等人在1986年,首先利用有機金 屬氣相沉積法(MOCVD)來成長氮化鎵膜層,其係於低溫成長一氮化鋁作為緩衝層,接著同樣在高溫下形成氮化鎵膜層。 S.Yoshida et al. used sapphire as a substrate in 1983, first growing a layer of aluminum nitride (AlN) as a buffer layer at a high temperature, and then growing a gallium nitride film layer thereon, so that a crystal of better quality was obtained. . Later, in 1986, I. Akasa and H. Amano first used organic gold. It is a vapor deposition method (MOCVD) to grow a gallium nitride film layer which is grown at a low temperature by using aluminum nitride as a buffer layer, and then forms a gallium nitride film layer at a high temperature.
同年,日本的日亞化學公司(Nichia Chemical Industries)的中村修二投入氮化鎵材料的研究,先以二流式MOCVD反應器成長氮化鎵膜層,並且在氮化鎵磊晶技術上作了兩項重大改變,其中他捨棄了以鋁化鎵為緩衝層,而改用低溫成長的氮化鎵作為緩衝層,並就此一改善申請為美國第US 5,290,393號專利。圖1係美國第US 5,290,393號專利之發光二極體10之剖面示意圖。於藍寶石之基材11上形成一GaxAlxN(0<x≦1)層作為緩衝層12,形成之溫度係低於900℃,其膜層厚度約為0.001μm到0.5μm。然後在緩衝層12上繼續磊晶一GaxAlxN(0<x≦1)層作為產生光線之半導體層13,形成之溫度係介於900℃至1150℃。 In the same year, Nakamura Shuji of Japan's Nichia Chemical Industries invested in the research of gallium nitride materials, first growing a gallium nitride film layer in a two-flow MOCVD reactor, and two on the gallium nitride epitaxial technology. A major change, in which he abandoned the use of gallium arsenide as a buffer layer, and switched to low-temperature-grown gallium nitride as a buffer layer, and the application for this improvement is US Pat. No. 5,290,393. Figure 1 is a schematic cross-sectional view of a light-emitting diode 10 of U.S. Patent No. 5,290,393. A layer of Ga x Al x N (0 < x ≦ 1) is formed on the substrate 11 of sapphire as the buffer layer 12 at a temperature lower than 900 ° C and a film thickness of about 0.001 μm to 0.5 μm. A layer of Ga x Al x N (0 < x ≦ 1) is then epitaxially grown on the buffer layer 12 as a light-generating semiconductor layer 13 at a temperature between 900 ° C and 1150 ° C.
圖2係美國第US 6,847,046號專利之發光二極體20之剖面示意圖。於藍寶石之基材21上形成一SiN/Al1-x-yInxGayN超晶格(superlattice)層作為緩衝層22,然後在緩衝層22上繼續形成一未摻雜氮化鎵(GaN)層23。 Figure 2 is a schematic cross-sectional view of a light-emitting diode 20 of U.S. Patent No. 6,847,046. A SiN/Al 1-xy In x Ga y N superlattice layer is formed on the sapphire substrate 21 as the buffer layer 22, and then an undoped gallium nitride (GaN) is formed on the buffer layer 22. Layer 23.
圖3係美國第US 5,523,589號專利之發光二極體30之剖面示意圖。於具導電性碳化矽之基材32上形成一AlxGa1-xN或Al1-x-yInxGayN層作為緩衝層33,然後在緩衝層33上繼續形成一下異質結構層(lower heterostructure layer)34。又N型電極31係設於基材32之底部。 Figure 3 is a schematic cross-sectional view of a light-emitting diode 30 of U.S. Patent No. 5,523,589. A layer of Al x Ga 1-x N or Al 1-xy In x Ga y N is formed as a buffer layer 33 on the substrate 32 having conductive tantalum carbide, and then a lower heterostructure layer is formed on the buffer layer 33 (lower) Heterostructure layer)34. Further, the N-type electrode 31 is provided on the bottom of the substrate 32.
圖4係美國第US 5,122,845號專利之發光二極體40之剖面示意圖。於藍寶石之基材41上形成一氮化鋁(AlN)層作為緩衝層42,然後在緩衝層42上繼續形成一N型氮化鎵(GaN)層43。 Figure 4 is a schematic cross-sectional view of a light-emitting diode 40 of U.S. Patent No. 5,122,845. An aluminum nitride (AlN) layer is formed on the sapphire substrate 41 as the buffer layer 42, and then an N-type gallium nitride (GaN) layer 43 is formed on the buffer layer 42.
前述習知技術均採含有鋁之氮化物作為緩衝層,由於該類緩衝層硬度高,因此使得基板與發光磊晶結構間之晶格不匹配而無法調適。基板與發光磊 晶結構間之累積應力會因緩衝層硬度高而不易消除,甚至會造成磊晶結構產生亀裂現象。另外,晶格不匹配及應力無法釋放造成磊晶結構有差排缺陷,亦即磊晶結構會因此而品質劣化。 The above-mentioned prior art adopts a nitride containing aluminum as a buffer layer. Due to the high hardness of the buffer layer, the lattice between the substrate and the luminescent epitaxial structure is mismatched and cannot be adjusted. Substrate and illuminating The cumulative stress between the crystal structures is not easily eliminated due to the high hardness of the buffer layer, and even the epitaxial structure may be cleaved. In addition, the lattice mismatch and the inability to release the stress cause the epitaxial structure to have a poor discharge defect, that is, the epitaxial structure may deteriorate in quality.
綜上所述,市場上亟需要一種確保品質穩定之光電半導體元件,俾能改善上述習知技術之各種缺點。 In summary, there is a need in the market for an optoelectronic semiconductor component that ensures stable quality, which can alleviate various shortcomings of the above-mentioned prior art.
本發明之主要目的係提供一種具三族氮化合物半導體緩衝層之光電半導體元件及其製造方法,其係以硬度較低之三族氮化合物半導體為基板與發光磊晶結構間之緩衝層,可有效釋放累積之應力而避免亀裂現象之發生。 The main object of the present invention is to provide an optoelectronic semiconductor component having a three-group nitrogen compound semiconductor buffer layer and a method for fabricating the same, which is a buffer layer between a substrate and a luminescent epitaxial structure. Effectively release accumulated stress to avoid the occurrence of splitting.
本發明之另一目的係提供一種具三族氮化合物半導體緩衝層之光電半導體元件,因減少磊晶層之應力累積,所以能降低磊晶結構中差排缺陷之密度,從而提高光電半導體元件之品質。 Another object of the present invention is to provide an optoelectronic semiconductor component having a buffer group of a trivalent nitrogen compound semiconductor. Since the stress accumulation of the epitaxial layer is reduced, the density of the defective defect in the epitaxial structure can be reduced, thereby improving the optoelectronic semiconductor component. quality.
為達上述目的,本發明揭示一種具三族氮化合物半導體緩衝層之光電半導體元件,其包含一基板,以及至少二個InxGa1-xN層及至少二個InyGa1-yN層交錯疊置於該基板上而形成緩衝層,其中x不等於y,或且0<x,y≦1。一發光磊晶結構設於位於上層之該InyGa1-yN層表面,介於該基板及該發光磊晶結構間之該InxGa1-xN層及該InyGa1-yN層形成超晶格核層(superlattice nucleation layer)以降低應力。 To achieve the above object, the present invention discloses an optoelectronic semiconductor component having a tri-group nitrogen compound semiconductor buffer layer, comprising a substrate, and at least two In x Ga 1-x N layers and at least two In y Ga 1-y N The layers are interleaved on the substrate to form a buffer layer, where x is not equal to y, or 0 < x, y ≦ 1. An epitaxial light emission structure disposed on the upper layer of In y located on the surface of the Ga 1-y N layer interposed between the In of the substrate and the epitaxial emission structure x Ga 1-x N layer and said In y Ga 1-y The N layer forms a superlattice nucleation layer to reduce stress.
該InxGa1-xN層及該InyGa1-yN層之層數較佳地分別介於2至5之間,該疊層係超晶格核層,且疊層厚度為0.001μm到0.5μm。 The number of layers of the In x Ga 1-x N layer and the In y Ga 1-y N layer is preferably between 2 and 5, respectively, and the laminate is a superlattice core layer, and the laminate thickness is 0.001. Mm to 0.5 μm.
該基材之材料包含藍寶石、碳化矽(SiC)、矽、氧化鋅(ZnO)、氧化鎂(MgO)及砷化鎵(GaAs)。 The material of the substrate comprises sapphire, tantalum carbide (SiC), tantalum, zinc oxide (ZnO), magnesium oxide (MgO), and gallium arsenide (GaAs).
該光電半導體元件係一發光二極體、一雷射二極體或一光感測器。 The optoelectronic semiconductor component is a light emitting diode, a laser diode or a photo sensor.
本發明另揭示一種具三族氮化合物半導體緩衝層之光電半導體元件之製造方法。首先,進行基材表面之淨化處理。再通入氨氣與三族元素之有機金屬先驅物(precursor),從而成長複數個InxGa1-xN/InyGa1-yN(x≠y)疊層。若重複形成InxGa1-xN/InyGa1-yN(x≠y)疊層之數目等於設定值,則再成長發光磊晶結構於該複數個InxGa1-xN/InyGa1-yN(x≠y)疊層上,否則繼續重複產生該InxGa1-xN/InyGa1-yN(x≠y)疊層之步驟。 The present invention further discloses a method of fabricating an optoelectronic semiconductor component having a tri-group nitrogen compound semiconductor buffer layer. First, the purification treatment of the surface of the substrate is performed. An organic metal precursor of ammonia gas and a trivalent element is further introduced to grow a plurality of In x Ga 1-x N/In y Ga 1-y N (x≠y) laminates. If the number of repeatedly formed In x Ga 1-x N/In y Ga 1-y N(x≠y) stacks is equal to a set value, the luminescent epitaxial structure is further grown in the plurality of In x Ga 1-x N/ On y Ga 1-y N(x≠y) laminate, otherwise the step of producing the In x Ga 1-x N/In y Ga 1-y N(x≠y) stack is repeated.
該三族元素之有機金屬先驅物為鎵或銦之有機金屬化合物,例如:三甲基鎵、三乙基鎵、三甲基銦及三乙基銦。 The organometallic precursor of the tri-group element is an organometallic compound of gallium or indium, such as trimethylgallium, triethylgallium, trimethylindium, and triethylindium.
該三族元素之有機金屬先驅物之流量較佳地控制於每分鐘50~1000立方公分之間。 The flow rate of the organometallic precursor of the tri-group element is preferably controlled between 50 and 1000 cubic centimeters per minute.
10、20、30、40‧‧‧發光二極體 10, 20, 30, 40‧‧‧Lighting diodes
11、21、32、41‧‧‧基材 11, 21, 32, 41‧‧‧ substrates
12、22、33、42‧‧‧緩衝層 12, 22, 33, 42‧‧‧ buffer layer
13‧‧‧半導體層 13‧‧‧Semiconductor layer
23‧‧‧氮化鎵層 23‧‧‧GaN layer
31‧‧‧N型電極 31‧‧‧N type electrode
34‧‧‧下異質結構層 34‧‧‧ Lower heterostructure layer
43‧‧‧N型氮化鎵(GaN)層 43‧‧‧N-type gallium nitride (GaN) layer
50‧‧‧光電半導體元件 50‧‧‧Optoelectronic semiconductor components
51‧‧‧基材 51‧‧‧Substrate
52‧‧‧緩衝層 52‧‧‧buffer layer
53‧‧‧N型半導體材料層 53‧‧‧N type semiconductor material layer
54‧‧‧主動層 54‧‧‧ active layer
55‧‧‧P型半導體材料層 55‧‧‧P type semiconductor material layer
56‧‧‧N型電極 56‧‧‧N type electrode
57‧‧‧P型電極 57‧‧‧P type electrode
521‧‧‧InxGa1-xN層 521‧‧‧In x Ga 1-x N layer
522‧‧‧InyGa1-yN層 522‧‧‧In y Ga 1-y N layer
圖1係美國第US 5,290,393號專利係揭露之發光二極體10之剖面示意圖;圖2係美國第US 6,847,046號專利係揭露之發光二極體20之剖面示意圖;圖3係美國第US 5,523,589號專利係揭露之發光二極體30之剖面示意圖;圖4係美國第US 5,122,845號專利係揭露之發光二極體30之剖面示意圖;圖5係本發明具P型三族氮化合物半導體之光電半導體元件之結構圖;以及圖6係本發明具P型三族氮化合物半導體之光電半導體元件之製造流程圖。 1 is a schematic cross-sectional view of a light-emitting diode 10 disclosed in U.S. Patent No. 5,290,393; FIG. 2 is a schematic cross-sectional view of a light-emitting diode 20 disclosed in U.S. Patent No. 6,847,046; FIG. 3 is a U.S. Patent No. 5,523,589. FIG. 4 is a schematic cross-sectional view of a light-emitting diode 30 disclosed in US Pat. No. 5,122,845; FIG. 5 is an optoelectronic semiconductor of the present invention having a P-type three-group nitrogen compound semiconductor. FIG. 6 is a structural diagram of the manufacture of an optoelectronic semiconductor component having a P-type Group III nitrogen compound semiconductor according to the present invention.
圖5係本發明具P型三族氮化合物半導體之光電半導體元件之結構圖。一般而言,製作此光電半導體元件50係先提供一基材51,例如:藍寶石(亦即鋁氧化合物Al2O3)、碳化矽(SiC)、矽、氧化鋅(ZnO)、氧化鎂(MgO)及砷化鎵(GaAs)等,並於該基材51上形成不同之材料層。因為基材51與三族氮化 合物之晶格常數不匹配,因此需要在基材51上先形成由至少二個InxGa1-xN層521及至少二個InyGa1-yN層522交錯疊之一緩衝層52。然後於緩衝層52上成長一N型半導體材料層53,其可以利用磊晶之方式產生N型氮化鎵摻雜矽薄膜以作為N型半導體材料層53。然後於N型半導體材料層53上成長多層量子井結構之主動層54,例如:五層氮化銦鎵(InGaN)/氮化鎵(GaN)多層量子井結構,該主動層54為發光二極體50主要產生光線之部分。最後在主動層54上形成至少一P型半導體材料層55,該P型半導體材料層55可以為摻雜鎂之氮化鎵、摻雜鎂之氮化鎵與氮化銦鎵的疊層或摻雜鎂之氮化鋁鎵與氮化鎵超晶格(Superlattice)結構加上摻雜鎂之氮化鎵等不同結構。另外,於N型半導體材料層53及P型半導體材料層55分別形成N型電極56及P型電極57之圖型,藉此可連接外部之電力。 Fig. 5 is a structural view showing an optoelectronic semiconductor device having a P-type Group III nitrogen compound semiconductor according to the present invention. In general, the fabrication of the optoelectronic semiconductor component 50 provides a substrate 51 such as sapphire (i.e., aluminum oxide Al 2 O 3 ), niobium carbide (SiC), tantalum, zinc oxide (ZnO), or magnesium oxide ( MgO), gallium arsenide (GaAs), etc., and different material layers are formed on the substrate 51. Since the lattice constant of the substrate 51 and the group III nitrogen compound do not match, it is necessary to form at least two In x Ga 1-x N layers 521 and at least two In y Ga 1-y N layers on the substrate 51 first. 522 is interleaved with one of the buffer layers 52. An N-type semiconductor material layer 53 is then grown on the buffer layer 52, which can be used to form an N-type gallium nitride doped germanium film as an N-type semiconductor material layer 53 by epitaxy. Then, an active layer 54 of a multi-layer quantum well structure is grown on the N-type semiconductor material layer 53, for example, a five-layer indium gallium nitride (InGaN)/gallium nitride (GaN) multilayer quantum well structure, and the active layer 54 is a light-emitting diode. Body 50 primarily produces portions of light. Finally, at least one P-type semiconductor material layer 55 is formed on the active layer 54. The P-type semiconductor material layer 55 may be a lamination or doping of magnesium-doped gallium nitride, magnesium-doped gallium nitride and indium gallium nitride. The magnesium-alloyed aluminum gallium and the gallium nitride superlattice structure and the magnesium-doped gallium nitride have different structures. Further, a pattern of the N-type electrode 56 and the P-type electrode 57 is formed in each of the N-type semiconductor material layer 53 and the P-type semiconductor material layer 55, whereby external power can be connected.
該緩衝層52係一種硬度較習知含鋁元素緩衝層為低之超晶格核層,可以有效降低基板與發光磊晶結構間累積之應力,其總膜層厚度約為0.001μm到0.5μm。因減少晶格之應力累積,所以能降低磊晶層中差排缺陷之密度,從而提高光電半導體元件50之品質。又緩衝層52中x≠y,且0<x,y≦1,其中以0<x,y≦0.5為較佳。 The buffer layer 52 is a superlattice core layer having a lower hardness than the conventional aluminum-containing buffer layer, and can effectively reduce the stress accumulated between the substrate and the luminescent epitaxial structure, and the total film thickness is about 0.001 μm to 0.5 μm. . Since the stress accumulation of the crystal lattice is reduced, the density of the defective defects in the epitaxial layer can be lowered, thereby improving the quality of the optoelectronic semiconductor device 50. Further, in the buffer layer 52, x ≠ y, and 0 < x, y ≦ 1, wherein 0 < x, y ≦ 0.5 is preferable.
圖6係本發明具P型三族氮化合物半導體之光電半導體元件之製造流程圖。如步驟61所示,將基材表面進行清洗,例如:於充滿氫氣之環境中以1200℃溫度進行熱清洗(thermal cleaning)。再通入氨氣與三族元素之有機金屬先驅物(precursor),可以採用鎵或銦之有機金屬化合物作為該有機金屬先驅物,例如:三甲基鎵(trimethylgalliaum;TMGa)、三乙基鎵、及三甲基銦(trimethylindium;TMIn)及三乙基銦等,從而成長複數個InxGa1-xN/InyGa1-yN(x≠y)疊層,如步驟62所示。三甲基鎵及三甲基銦之流量可分別控制於每分鐘50~1000立方公分(standard cubic centimeter per minute;SCCM)之間,又氨氣之流量可控制於每分鐘0.5~200公升(standard cubic liter per minute;SCLM)。如步驟63所示,若重複形成InxGa1-xN/InyGa1-yN(x≠y)疊層之總數目等於設定值(2至5個疊層為較佳,亦即InxGa1-xN層及InyGa1-yN層分別為2至5層),則就依照步驟64之指示再成長發光磊晶結構於該複數個InxGa1-xN/InyGa1-yN(x≠y)疊層上,否則繼續重複產生該InxGa1-xN/InyGa1-yN(x≠y)疊層之步驟62。 Fig. 6 is a flow chart showing the manufacture of an optoelectronic semiconductor device having a P-type Group III nitrogen compound semiconductor according to the present invention. As shown in step 61, the surface of the substrate is cleaned, for example, in a hydrogen-filled environment at a temperature of 1200 ° C for thermal cleaning. An organometallic precursor of ammonia and a tri-group element can be introduced, and an organometallic compound of gallium or indium can be used as the organometallic precursor, for example, trimethylgalliaum (TMGa), triethylgallium. And trimethylindium (TMIn) and triethylindium, etc., thereby growing a plurality of In x Ga 1-x N/In y Ga 1-y N (x≠y) stacks, as shown in step 62 . The flow rate of trimethylgallium and trimethylindium can be controlled between 50~1000 cubic centimeters per minute (SCCM), and the flow rate of ammonia gas can be controlled at 0.5~200 liters per minute (standard Cubic liter per minute; SCLM). As shown in step 63, if the total number of over - formed In x Ga 1-x N/In y Ga 1-y N (x≠y) stacks is equal to the set value (2 to 5 stacks are preferred, that is, The In x Ga 1-x N layer and the In y Ga 1-y N layer are respectively 2 to 5 layers), and then the luminescent epitaxial structure is further grown in the plurality of In x Ga 1-x N/ according to the instruction of step 64. On y Ga 1-y N(x≠y) laminate, otherwise step 62 of generating the In x Ga 1-x N/In y Ga 1-y N(x≠y) stack is repeated.
本發明之應用不限於例示之發光二極體,相關光電半導體元件均可為申請專利範圍所涵蓋,例如:雷射二極體(laser diode)及光感測器(photo sensor)等。 The application of the present invention is not limited to the illustrated light emitting diodes, and the related optoelectronic semiconductor components may be covered by the scope of the patent application, for example, a laser diode and a photo sensor.
本發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為以下之申請專利範圍所涵蓋。 The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims
50‧‧‧光電半導體元件 50‧‧‧Optoelectronic semiconductor components
51‧‧‧基材 51‧‧‧Substrate
52‧‧‧緩衝層 52‧‧‧buffer layer
53‧‧‧N型半導體材料層 53‧‧‧N type semiconductor material layer
54‧‧‧主動層 54‧‧‧ active layer
55‧‧‧P型半導體材料層 55‧‧‧P type semiconductor material layer
56‧‧‧N型電極 56‧‧‧N type electrode
57‧‧‧P型電極 57‧‧‧P type electrode
521‧‧‧InxGa1-xN層 521‧‧‧In x Ga 1-x N layer
522‧‧‧InyGa1-yN層 522‧‧‧In y Ga 1-y N layer
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