JP2000022161A - Thin-film transistor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor and its manufacturing method, in which the thin-film transistor with a bottom gate structure can be formed self- alignedly, capable of reducing damages at injection. SOLUTION: In a manufacturing method, a PSG(phosphorus silicate glass) layer 12 and a BSG(boron silicate glass) layer 13 as base layers are formed selectively on a transparent insulating substrate 11. The PSG layer 12 and the BSG layer 13 contain impurity which determines the conductivity type of silicon. A gate electrode and a silicon layer are formed thereon. In a heat treatment step for making the silicon in a polysilicon state, the impurity such as phosphorous or boron included in the PSG layer 12 and the BSG layer 13 for determining the conductive type of the silicon is diffused to form a source/ drain region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display device and the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art At present, a liquid crystal display device for driving a thin film transistor (TFT) is used for a notebook computer, a car navigation, and the like, and further reduction in size, weight, and cost is desired in the future. The structure of the thin film transistor includes a top gate type TFT structure in which a gate insulating layer exists on the substrate side with respect to the gate electrode, and a bottom gate type structure in which a gate insulating layer exists on the side opposite to the substrate with respect to the gate electrode. Things exist.

An advantage of the conventional bottom gate type TFT structure is that the diffusion of impurities from the base substrate such as a glass substrate into the channel region can be almost completely prevented by the gate metal electrode. However, in this structure, since the impurity diffusion for forming the source drain is performed after the formation of the silicon layer, that is, from the silicon layer side, there is a disadvantage that the source drain diffusion for forming the channel region cannot be self-aligned. Therefore, there has been a problem that the transistor characteristics are deteriorated, for example, the gate capacitance is increased.

On the other hand, an advantage of the conventional top gate type TFT structure is that impurity diffusion for forming a source drain is performed from the gate electrode side via a gate metal pattern after a silicon layer is formed. In that the source drain diffusion can be self-aligned. However, in this structure, since there is no gate metal below the channel region, there is a major drawback that the diffusion of impurities from the base substrate such as a glass substrate into the channel region cannot be prevented by the gate metal electrode.

Therefore, in order to increase the reliability of the transistor, it is necessary to make the underlying insulating film layer relatively thick, which causes various problems in the manufacturing process such as warpage of the substrate.

Hereinafter, a conventional bottom gate thin film transistor having the above-mentioned disadvantages and a method for manufacturing the same will be described in detail with reference to the drawings.

FIG. 3 is a sectional view showing a manufacturing process of a conventional bottom gate thin film transistor. In FIG. 3, reference numeral 31 denotes a transparent insulating substrate such as a glass substrate, 32 denotes a gate electrode, and 33 denotes a SiO2 or the like. A gate insulating layer,
34c is a channel region in the silicon semiconductor layer, 34c
s is a source region in the silicon semiconductor layer, 34d is a drain region in the silicon semiconductor layer, 35 is a photoresist, 36 is an interlayer insulating layer, 37s is a source electrode, 37s
d indicates a drain electrode.

A conventional bottom-gate thin film transistor starts with a step of forming a gate electrode 32 on a transparent insulating substrate 31 and then forms a gate insulating film on the transparent insulating substrate 31 on which the gate electrode 32 is formed. The layer 32 is formed (FIG. 3A).

Next, a silicon semiconductor layer is selectively formed on the gate insulating layer. At this time, when polycrystalline silicon, which has recently been receiving attention, is used as a silicon semiconductor layer, for example, an amorphous silicon layer is formed in advance, and then this amorphous silicon layer is annealed by an excimer laser or the like. Thereafter, a photoresist 35 is selectively formed on the silicon semiconductor layer at a position above the gate electrode 32, and an impurity that determines the conductivity type of silicon is ion-implanted into the silicon semiconductor layer using the photoresist 35 as a mask. By selective introduction, a channel region 34c, a source region 34s, and a drain region 34d which form a thin film transistor are formed (FIG. 3B).

Finally, after forming an interlayer insulating layer 36 on the entire surface, contact holes are opened in the interlayer insulating layer 36 at positions corresponding to the source region 34s and the drain region 34d.
A thin film transistor is completed by burying a metal in the contact hole to form a source electrode 37s and a drain electrode 37d.

[0011]

However, the conventional bottom gate thin film transistor shown in FIG. 3 has two major problems as described below.

The first problem is a problem when impurities are implanted into a portion to be a source / drain region of a thin film transistor.

In the case of a thin film transistor having a top gate structure, since the silicon semiconductor layer forming the source / drain region is located below the gate electrode,
When an impurity that determines the conductivity type of silicon is introduced into a portion serving as a drain region, the gate electrode itself serves as a mask for introducing the impurity, so that the source / drain region can be formed in a self-aligned manner. is there.

On the other hand, in the case of a thin film transistor having a bottom gate structure as shown in FIG. 3, a silicon semiconductor layer serving as a source / drain region exists above a gate electrode. When introducing an impurity that determines the conductivity type, it is necessary to form a photoresist 35 at a position corresponding to a gate electrode that has already been formed, and it is necessary to align the photoresist. That is, it is impossible to form the source / drain regions in a self-aligned manner in the process shown in FIG.

In the future, there is a demand for a high-definition liquid crystal display device. In such a case, it is necessary to miniaturize a thin film transistor. Is an obstacle at that time, and at present, top gate type thin film transistors are becoming mainstream.

The second problem is related to the method of introducing impurities into the source / drain regions of the thin film transistor.

As described above, when impurities for determining the conductivity type of silicon are introduced into a silicon semiconductor layer in order to form source / drain regions of a thin film transistor,
A technique called ion implantation is used. Recently, a so-called “ion shower doping” method of introducing impurity ions into the silicon semiconductor layer in a shower shape has been used, but in any case, an impurity is forcibly implanted into the silicon semiconductor layer. At that time, the silicon semiconductor layer is more or less damaged. Therefore, it becomes necessary to recover the damage by a subsequent heat treatment or the like. However, when glass is used for the underwear substrate, the annealing temperature is limited by the heat resistance of the glass. (In practice, up to 600 ° C
It is about. Therefore, it cannot be said that the damage can be completely recovered by the heat treatment or the like, which is a serious problem particularly when polycrystalline silicon is used as an active layer (silicon semiconductor layer).

In view of the above two problems, the present invention employs a bottom gate type TFT structure and uses a method of self-aligning (self-alignment) thermal diffusion of source / drain impurity diffusion. It is a main object of the present invention to provide a transistor having high reliability and excellent characteristics by reducing damages caused by the above and eliminating defects of the bottom gate type TFT structure.

[0019]

To achieve the above object, a thin film transistor according to the present invention comprises a transparent insulating substrate, a base insulating layer selectively formed on the transparent insulating substrate, and a base insulating layer. A gate electrode formed on the insulating layer,
A gate sidewall insulating layer formed on the side surface of the gate electrode;
A thin film transistor including a gate insulating layer formed over the gate electrode, a base insulating layer, the gate sidewall insulating layer, and a silicon layer formed to cover the gate insulating layer, wherein the base layer is Impurities contained in the base insulating layer are diffused into the silicon layer that is in contact with the base layer and contains impurities that determine the conductivity type of silicon, so that source / drain regions are formed. The configuration is characterized by the following.

According to the method of manufacturing a thin film transistor of the present invention, a step of forming a base insulating layer containing an impurity that determines the conductivity type of silicon on a transparent insulating substrate, and forming a gate electrode on the base insulating layer are provided. Forming a gate insulating layer on the gate electrode, forming a gate sidewall insulating layer on the side surface of the gate electrode, covering the base insulating layer, the gate sidewall insulating layer, and the gate insulating layer. Thus, a step of forming a silicon layer and a step of forming a source / drain region by making the silicon layer contain the impurity by diffusion are provided.

According to the above structure, in the thin film transistor having the bottom gate structure, the formation of the source / drain region by introducing the impurity element into the silicon semiconductor can be performed by the diffusion without performing the implantation step such as ion implantation or ion doping. Therefore, damage to the silicon semiconductor layer forming the source / drain regions can be suppressed to a minimum. Further, the introduction of impurities into the silicon semiconductor for forming the source / drain regions can be performed in a self-aligned manner without using a photoresist.

In the above thin film transistor,
First and second base insulating layers are selectively formed on a transparent insulating substrate, and the first and second base layers contain impurities of one conductivity type and impurities of another conductivity type which determine the conductivity type of silicon. Then, a thin film transistor having a CMOS structure can be easily formed.

Further, in the above-described method for manufacturing a thin film transistor, an amorphous silicon layer is formed so as to cover the base insulating layer, the gate sidewall insulating layer, and the gate insulating layer, and then the amorphous silicon layer is irradiated with laser light. If the amorphous silicon layer is polycrystallized to form a polycrystalline silicon layer, polycrystallization of silicon and formation of source / drain regions by introducing impurities into the polycrystalline silicon layer can be performed simultaneously.

In the above thin film transistor,
The base insulating layer has a function of preventing diffusion of impurities contained in the transparent insulating substrate, thereby preventing impurities contained in the glass substrate and adversely affecting the silicon semiconductor layer from diffusing into the silicon semiconductor. Can be.
It is most preferable to use a BSG (boron silicate glass) layer or a PSG (phosphorus silicate glass) layer as such an underlayer.

Further, in a method of manufacturing a thin film transistor using a polycrystalline silicon semiconductor in which amorphous silicon is polycrystallized by irradiation with an excimer laser beam, the gate electrode material is instantaneously exposed to a considerably high temperature. It is preferable to use a high melting point metal, and it is preferable to use a high melting point metal containing Cr or Mo as a main component, because the gate side wall insulating layer can be easily formed by oxidation of the gate electrode.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings. In the following, the case where the silicon semiconductor layer constituting the active layer of the thin film transistor is made of polycrystalline silicon will be described as an example, but the present invention is not necessarily applicable only when polycrystalline silicon is used. Instead, the present invention can be applied to a case where amorphous silicon is used. Also, in the form shown below,
A case where an N-channel transistor and a P-channel transistor are formed simultaneously on a substrate will be described. However, the present invention is not necessarily applicable only to a case where an N-channel transistor and a P-channel transistor are formed simultaneously. Needless to say, it is also possible to form only one.

FIG. 1 is a sectional view showing the structure of a thin film transistor according to an embodiment of the present invention. In FIG.
Reference numeral 11 denotes a transparent insulating substrate such as a glass substrate. On the transparent insulating substrate 11, a PSG layer 12 as an underlayer that determines the conductivity type of silicon while containing a conductivity type impurity, and a conductivity type of silicon are provided. On the other hand, the BSG layer 13 is selectively formed as a base layer containing a conductive impurity. On the PSG layer 12 and the BSG layer 13, a gate electrode 14 made of, for example, chromium, a first polysilicon layer 15 into which impurities are introduced by diffusion of P from the PSG layer 12, and a B A second polysilicon layer 16 into which an impurity has been introduced by the diffusion of is formed. The first polysilicon layer 15 and the second polysilicon layer constitute source / drain regions of the thin film transistor.

On the side surface of the gate electrode 14, the gate electrode 14 and the first polysilicon layer 15 doped with impurities and the second polysilicon layer 16 doped with impurities are formed.
Side wall insulating layer 17 for electrically insulating between
Are formed. The gate side wall insulating layer 17
Is preferably an insulating layer obtained by oxidizing the gate electrode 14.

Further, a gate insulating layer 18 is formed on the gate electrode 14, and an impurity formed on both sides of the gate electrode while covering the gate insulating layer 18 and the gate side wall insulating layer 17 is formed thereon. The polysilicon layer 19 is formed so as to be in contact with the first polysilicon layer 15 into which the impurity has been introduced and the second polysilicon layer 16 into which the impurity has been introduced. This polysilicon layer 19 forms the channel region of the thin film transistor shown in FIG.

Further, an interlayer insulating layer 110 is formed on the device having the above-described structure.
A contact hole is selectively formed in 10, and a source / drain electrode 111 is formed by burying a metal in the contact hole.

According to the thin-film transistor of the present invention described above, when forming the source / drain regions of the thin-film transistor, the thin-film transistor is formed from a base layer containing impurities that determine the conductivity type of silicon, such as the PSG layer 12 and the BSG layer 13. Since thermal diffusion into the silicon semiconductor layer is used, there is no step of implanting impurities such as ion implantation.
Damage to the silicon semiconductor layer can be prevented. Although details will be described later, when the above-described method is used, since there is no step of introducing an impurity using a photoresist as a mask, the source / drain regions can be formed in a self-aligned manner.

In this embodiment, a PSG layer, a BSG layer, or the like is used as a base film containing an impurity that determines the conductivity type of silicon as described above. It also has a function of preventing impurities such as alkali metals existing in a glass substrate which is an insulating substrate from diffusing into the silicon semiconductor layer. And this PS
The G layer and the BSG layer are compared with a silicon nitride film or the like (known as an undercoat layer) conventionally used for preventing diffusion of impurities such as alkali metals from a glass substrate into a silicon semiconductor layer. Since the effect of preventing the diffusion of alkali metals and the like is high, it is possible to more reliably prevent the diffusion from the glass substrate at the time of heat treatment, for example, when manufacturing a thin film transistor. Therefore, contamination of the interface between the gate electrode and the gate insulating layer, which is a portion that greatly affects the characteristics of the thin film transistor, with alkali metal or the like can be prevented.

Although the thin film transistor shown in FIG. 1 does not have an undercoat layer conventionally used, after forming an undercoat layer such as a silicon nitride film, a PSG layer or a BSG layer is formed thereon. Can be formed, and in this case, diffusion of impurities from the glass substrate to the silicon semiconductor layer can be prevented more reliably.

Next, a method of manufacturing the thin film transistor according to the embodiment of the present invention shown in FIG.
This will be described with reference to FIG. In the following example, a case where an N-channel transistor and a P-channel transistor are simultaneously formed on a substrate will be described. However, the present invention is not necessarily limited to a case where an N-channel transistor and a P-channel transistor are simultaneously formed. It ’s not adaptable,
It goes without saying that only one of them may be formed.

First, a transparent insulating substrate 21 such as a glass substrate
The upper region for forming the N-channel transistor contains P, which is an N-type impurity, and can prevent diffusion of an element such as an alkali metal contained in the glass substrate, which adversely affects the interface between the gate electrode and the gate insulating film. P which is an insulating film
An SG film 22 is formed, while a region where a P-channel transistor is formed contains B which is a P-type impurity, and
A BSG film 23, which is a base insulating film capable of preventing diffusion of an element having a bad influence on an interface between a gate electrode such as an alkali metal and a gate insulating film contained in a glass substrate, is selectively formed.

The above-mentioned PSG film 22 and BSG film 2
On each of the gate electrodes 3, a gate electrode material layer 24 that will form a gate electrode later is formed. Although details will be described later, Cr is used as the material of the gate electrode material layer 24 in the present embodiment.

Thereafter, a gate insulating layer 25 of SiO 2 or the like is formed on the entire surface later, and a resist pattern 26 for forming a gate electrode pattern is further formed.
(A)).

Next, dry etching is performed using the resist pattern 26 formed as described above as a mask to form a gate electrode 27 (FIG. 2B). At this time, the gate insulating layer is simultaneously patterned.

Thereafter, the resist pattern 26 used in the etching step shown in FIG. 2B is removed, and the side surface of the gate electrode 27 is oxidized by heating to form the gate electrode 2.
A gate electrode side wall insulating layer 28 is formed on the seven side surfaces.
(C)). The gate electrode side wall insulating layer 28 has a function of electrically insulating a silicon semiconductor layer formed later and the gate electrode 27. In this embodiment mode, the gate electrode side wall insulating layer 28 is formed by oxidation by heating as described above, and therefore, as a metal material used for the gate electrode, the insulating layer can be formed by thermal oxidation. It is necessary to use Ti or Mo in addition to Cr as described above as a material.

Next, a semiconductor layer to be a channel region and a source / drain region of the thin film transistor is formed later. Specifically, an amorphous silicon layer 29 is deposited on the entire surface (FIG. 2D).

In this state, the above amorphous silicon layer 29
Is performed. Specifically, for example, by irradiating excimer laser light (arrows in FIG. 2E), amorphous silicon is instantaneously melted and recrystallized to form a polycrystalline silicon layer. When the annealing with the excimer laser light is performed, the region irradiated with the excimer laser light is heated to a very high temperature, albeit momentarily. However, in this embodiment, the material of the gate electrode 27 is Cr Since the high melting point metal material is used, the gate electrode 27 does not melt. For various reasons as described above, as a material of the gate electrode 27, it is preferable to use a high-melting-point metal that has an insulating oxide film and does not melt even when irradiated with excimer laser light. Although Cr is used in the embodiment, Ti, Mo, or the like may be used instead.

In the present embodiment, the source / drain regions (the first polysilicon layer and the second polysilicon layer in FIG. 1) are simultaneously diffused by impurities during the polycrystallization treatment using the excimer laser light. (Also serving as an activation process). That is, in this embodiment, P and B are diffused from the PSG film 22 and the BSG film 23 into the polycrystalline silicon layer by the heat generated by the irradiation of the excimer laser light, so that the source / drain regions 211 are formed. (FIG. 2E).

As described above, according to the present embodiment, the polycrystalline silicon semiconductor layer and the channel region 2 forming the thin film transistor are formed by the excimer laser light irradiation step.
10. The source / drain region 211 can be formed simultaneously. Therefore, for forming the source / drain regions,
The necessity of performing the impurity implantation step is eliminated, so that the source / drain regions can be formed in a self-aligned manner, and the occurrence of damage due to ion doping or the like can be prevented.

In the step of FIG. 2E, if the heat treatment conditions and the like are properly controlled, the gate electrode 27
Since the thickness of the polycrystalline silicon layer existing on the side surface of the region is thicker than that of the polycrystalline silicon layer in other regions, the impurity P
As a result, the LDD structure can be automatically formed.

Next, an interlayer insulating layer 212 made of, for example, SiO 2 is formed on the entire surface of the transparent insulating substrate 21 on which the gate electrode and the source / drain regions are formed as described above.
(F)) Thereafter, a contact hole is formed at a position corresponding to the source / drain region of the interlayer insulating layer, and a metal is buried in the contact hole, thereby forming a source / drain electrode 213 to complete a thin film transistor. (FIG. 2 (g)).

[0046]

As described above, according to the present invention, a source / drain electrode is formed by accidental diffusion from an underlayer containing an impurity that determines the conductivity type of a silicon semiconductor to a silicon semiconductor layer. Therefore, even in a bottom-gate type thin film transistor, a step of implanting an impurity element such as ion implantation is eliminated, so that damage to the silicon semiconductor layer can be reduced and source / drain regions can be formed in a self-aligned manner. Becomes possible.

When a PSG layer or a BSG layer is used as a base layer containing the above-described impurities, when a glass substrate is used as a transparent insulating substrate, an alkali metal or the like which adversely affects the characteristics of the thin film transistor is used. Diffusion of the impurity element from the glass substrate to the silicon semiconductor layer can be reliably prevented.

Therefore, a TFT having excellent reliability and transistor characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the thin film transistor according to the embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

 11, 21, 31 Transparent insulating substrate 12, 22 PSG layer 13, 23 BSG layer 14, 27, 32 Gate electrode 15 First polysilicon layer doped with impurities 16 Second polysilicon layer doped with impurities Reference Signs List 17 gate sidewall insulating layer 18, 25, 33 gate insulating layer 19 polysilicon layer having channel region 24 gate electrode material layer 26 resist pattern 28 gate electrode sidewall insulating layer 29 amorphous silicon layer 34c, 210 channel region 34d drain region 34s Source region 35 Photoresist 36,212 Interlayer insulating layer 37d Drain electrode 37s Source electrode 110 Insulating layer 111,213 Source / drain electrode 211 Source / drain region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 627F

Claims (18)

[Claims] A transparent insulating substrate, a base insulating layer formed on the transparent insulating substrate, a gate electrode formed on the base insulating layer, and a gate sidewall formed on a side surface of the gate electrode. A layer, a gate insulating layer formed on the gate electrode, the base insulating layer, the gate sidewall insulating layer,
And a silicon layer formed so as to cover the gate insulating layer, wherein the underlayer contains an impurity that determines the conductivity type of silicon, and the silicon layer is in contact with the underlayer. A source / drain region formed by diffusing impurities contained in the base insulating layer. 2. The thin film transistor according to claim 1, wherein the base insulating layer has a function of preventing diffusion of impurities contained in the transparent insulating substrate. 3. The thin film transistor according to claim 2, wherein the base insulating layer is a BSG layer or a PSG layer. 4. A transparent insulating substrate, first and second base insulating layers selectively formed on the transparent insulating substrate, and formed on the first and second base insulating layers, respectively. A gate electrode, a gate sidewall insulating layer formed on a side surface of the gate electrode, a gate insulating layer formed on the gate electrode, the first and second base insulating layers, the gate sidewall insulating layer, and A silicon layer formed so as to cover the gate insulating layer, wherein the first and second underlayers contain impurities of one conductivity type and impurities of the other conductivity type that determine the conductivity type of silicon. In addition, the impurities contained in the first and second base insulating layers are diffused into the silicon layer in contact with the first and second base layers to form source / drain regions. Characterized in that: Njisuta. 5. The thin film transistor according to claim 4, wherein the first and second base insulating layers have a function of preventing diffusion of impurities contained in the transparent insulating substrate. 6. The thin film transistor according to claim 5, wherein the first underlayer is a BSG layer, and the second underlayer is a PSG layer. 7. The thin film transistor according to claim 1, wherein the silicon layer is made of polycrystalline silicon. 8. A step of forming a base insulating layer containing impurities for determining the conductivity type of silicon on a transparent insulating substrate;
Forming a gate electrode on the base insulating layer, forming a gate insulating layer on the gate electrode, forming a gate sidewall insulating layer on a side surface of the gate electrode; A method for manufacturing a thin film transistor, comprising: forming a silicon layer so as to cover a sidewall insulating layer and the gate insulating layer; and forming a source / drain region by diffusing the impurity into the silicon layer. 9. A step of forming a base insulating layer containing impurities for determining the conductivity type of silicon on a transparent insulating substrate;
Forming a gate electrode on the base insulating layer, forming a gate insulating layer on the gate electrode, forming a gate sidewall insulating layer on a side surface of the gate electrode; Forming an amorphous silicon layer so as to cover the sidewall insulating layer and the gate insulating layer; and irradiating the amorphous silicon layer with a laser beam to polycrystallize the amorphous silicon layer. Forming a silicon layer and forming the source / drain region by diffusing the impurity into the polycrystalline silicon layer. 10. A first base insulating layer containing impurities of a conductivity type while determining the conductivity type of silicon and a second base containing impurities of the other conductivity type which determines the conductivity type of silicon on a transparent insulating substrate. Selectively forming an insulating layer; forming a gate electrode on the first and second base insulating layers; forming a gate insulating layer on the gate electrode; Forming a gate side wall insulating layer; forming a silicon layer so as to cover the first and second base insulating layers, the gate side wall insulating layer, and the gate insulating layer; Forming source / drain regions by diffusing a conductive impurity and the other conductive impurity by diffusion. 11. A first base insulating layer containing impurities of a conductivity type while determining the conductivity type of silicon and a second base containing impurities of the other conductivity type which determines the conductivity type of silicon on a transparent insulating substrate. Selectively forming an insulating layer; forming a gate electrode on the first and second base insulating layers; forming a gate insulating layer on the gate electrode; Forming a gate sidewall insulating layer, forming an amorphous silicon layer so as to cover the first and second base insulating layers, the gate sidewall insulating layer, and the gate insulating layer; The amorphous silicon layer is polycrystallized by irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer, and the one conductivity type impurity and the other conductivity type impurity are diffused into the polycrystalline silicon layer by diffusion. Manufacturing method of a thin film transistor and a step of chromatic are allowed to form a source-drain region. 12. The method of manufacturing a thin film transistor according to claim 8, wherein the base insulating layer has a function of preventing diffusion of impurities contained in the transparent insulating substrate. 13. The method according to claim 12, wherein the underlying insulating layer is a BSG layer or a PSG layer. 14. The method according to claim 10, wherein the first and second base insulating layers have a function of preventing diffusion of impurities contained in the transparent insulating substrate. . 15. The method according to claim 14, wherein the first underlayer is a BSG layer and the second underlayer is a PSG layer. 16. The method according to claim 9, wherein the gate electrode material is made of a high melting point metal. 17. The method according to claim 16, wherein the refractory metal is mainly composed of Cr, Ti, or Mo. 18. The method according to claim 8, wherein the gate side wall insulating layer is formed by oxidizing the gate electrode.