KR100941119B1 - Printed, self-aligned, top gate thin film transistor - Google Patents

Abstract

The present invention relates to a self-aligned top-gate thin film transistor (TFT) and a method of manufacturing such a thin film transistor, the method comprising the steps of: forming a semiconductor thin film layer; Printing thereon a doped glass pattern, a gap in said doped glass pattern defining a channel region of a TFT; Forming a gate electrode on the channel region, the gate electrode including a gate dielectric layer and a gate conductor over the gate dielectric layer; And diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

Top-Gate Thin Film Transistors, TFT, Glass Pattern, Gate, Drain, Source

Description

Printed, self-aligned, top-gate thin film transistors {PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR}

1A-1E illustrate cross-sectional views at various stages of an exemplary process flow of a manufacturing process of a printed self-aligned top-gate device.

2A-2E illustrate cross-sectional views of another exemplary process flow including post-printing oxide gate formation of doped silanes.

3A-3E illustrate cross-sectional views of a process flow that reduces potential false diffusion from doped glass during dielectric gate formation and (optional) further processing.

4A-4D illustrate cross-sectional views of a process flow for etching a doped glass pattern and forming source / drain contacts and wiring using a metal gate as a mask.

5A-5E illustrate cross-sectional views of alternative process flows for forming source / drain contacts and wiring.

6A-6C illustrate cross-sectional views of alternative process flows wherein a dielectric material is used as a mask over a metal gate in the formation of the etch and source / drain contacts and wiring of the doped glass pattern.

7A-7D show cross-sectional views of an alternative process flow that uses a printed interlayer dielectric as a mask to etch doped glass and expose doped polysilicon source / drain regions for sequential contact / wiring formation.

8A-8D are cross-sectional views of another alternative process flow that uses a printed interlayer dielectric as a mask to non-selectively etch the doped glass and expose the doped polysilicon source / drain regions for sequential contact / wiring formation.

<Description of main parts of drawing>

4, 14, 24, 130, 230, 330; Doped glass

8, 18, 28, 140, 240, 340; Gate metal

3, 13, 23, 120, 220, 320; Gate dielectric

16, 26, 112/114, 212/214, 312/314; Source / Drain Area

160, 245, 260/262/264, 350/352/354; Interlayer dielectric

222/224, 322/324; Thermal oxide

FIELD OF THE INVENTION The present invention relates to printed, self-aligned, top-gate thin film transistors (TFTs), wherein metal containing inks can be used for gate metal printing. In a preferred embodiment, the metal containing ink comprises metal nanoparticles. The present invention preferably requires little or no high temperature or laser activation treatment after printing the metal ink.

In a conventional top-gate TFT process, the alignment between the gate and source / drain regions is ensured by first patterning the metal material and using it as a mask for dopant implantation and / or activation. This method is compatible with reflection on UV laser irradiation (eg Al) or compatibility with thermal dopant activation at temperatures higher than 600 ° C. (eg doped polysilicon or refractory metals such as Mo, Pd or W). This necessitates the problem of gate metal selection.

Conventional printing techniques (eg ink-jetting) may be desirable for manufacturing electronic devices because of the high yield of the printing process compared to photolithography.

However, high resolution printing techniques generally limit the width of the printed line (about 10 micrometers or more) because of the relatively large volume of ink drops.

Thus, the use of printing techniques can produce TFTs that can form small line widths (eg less than 10 μm) such as gates, i.e., not limited to particular gate materials such as aluminum, refractory metals or doped polysilicon. Development of the process is preferred.

An object of the present invention is to form a semiconductor thin film layer; Printing a doped glass pattern having a gap defining a channel region of a TFT on the semiconductor thin film layer; Forming a gate electrode on the channel region, the gate electrode including a gate dielectric layer and a gate conductor over the gate dielectric layer; And to provide a method for forming a thin film transistor (TFT) comprising the step of diffusing a dopant (dopant) from the doped glass pattern to the semiconductor thin film layer.

Another object of the present invention is a semiconductor thin film layer; At least a portion of the doped glass pattern; A gate electrode on a channel region of the semiconductor thin film layer; And a dopant containing region in the semiconductor thin film layer on the opposite side of the channel region, at least two portions of the doped glass pattern defining a gap over the channel region of the thin film transistor, wherein the gate electrode is a gate dielectric film and a gate thereon It is an object of the present invention to provide a thin film transistor (TFT) comprising a conductor.

Another object of the present invention is to form a semiconductor thin film layer; Printing a doped glass pattern having a gap defining a channel region of a TFT on the semiconductor thin film layer; It is an object of the present invention to provide a method of forming a thin film structure comprising diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

Another object of the present invention is a semiconductor thin film layer; At least a portion of a doped glass pattern on the semiconductor thin film layer; And a dopant containing region in the semiconductor thin film layer on the opposite side of the channel region, wherein at least two portions of the doped glass pattern define a gap over the channel region of the thin film transistor. will be.

In one aspect, the present invention has found that the space between two lines may be less than the minimum width of an inkjet printed line because the space between the two lines is determined primarily by the ink position accuracy and the accuracy and adjustability of the printer's mechanical stage. . Thus, first printing a source / drain pattern that defines the location of subsequent deposition gate metals allows high performance printed top-gate TFTs to be manufactured with a channel width of less than 10 μm.

Thus, the present invention includes glass (eg, quartz) sheets or slips, plastic and / or metal sheets, sheets or slabs, silicon wafers, and the like, which may involve one or more buffer layers (silicon oxide and / or aluminum oxide). However, the present invention is for fabricating thin film transistors and circuits thereof on various substrates, but not limited thereto. The present invention may be applied to a display, an RF device, a sensor, and the like, but is not limited thereto.

The development of printed refractory materials or Al gates in self-aligned top-gate TFTs poses a significant problem, the present invention patterning the layer defining the source / drain regions and then activating the dopant (eg By annealing at high temperatures or by laser activation), and then by depositing a gate metal precursor ink. In a preferred embodiment, simple pure metal inks including gold or silver can be used to print metal gates since no high temperature or laser activation process steps are required afterwards. Current TFTs can operate at a kHz frequency and can be (1) narrow channel widths, (2) self-aligned source and drain terminals with respect to gates with a small amount of overlap between them, and / or (3) high carrier movement. It may have the advantage of FIG.

Reference will now be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that it is not intended to limit the invention to these embodiments. In other words, it is intended that the present invention include modifications, variations and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims. In addition, in the following description, numerous specific details are given to provide an understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits will not be described in detail in order to avoid unnecessarily obscuring aspects of the present invention.

For convenience and simplicity of description, the terms "coupled to," "connected to," and "communicating with" (and variations thereof) are directly or indirectly combined unless explicitly defined otherwise herein. Speak, connect or communicate. These terms may be used interchangeably herein, and whenever such terms are used they are to be construed to include other terms unless expressly defined otherwise herein. As used herein, the term "deposit" (and its grammatical variations) is intended to encompass all forms of deposition, including blanket deposition, coating, and printing, unless expressly defined otherwise herein. In addition, the term "consisting essentially of" for a particular material is intentional to impart certain (and potentially very different) physical and / or electrical properties to the material to which the dopant is added (or a component or structure formed from such material). It does not exclude dopants added with. The term "(poly) silane" refers to (1) silicon and / or germanium, and (2) a compound or mixture of compounds consisting essentially of hydrogen, having mainly at least 15 silicon and / or germanium atoms Includes kind. Such kind may include one or more rings. The term "(cyclo) silane" refers to (1) silicon and / germanium, and (2) a compound or mixture of compounds consisting essentially of hydrogen, with one or more rings and less than 15 silicon and / or germanium It may contain atoms. The term " hetero (cyclo) silane " refers to such as B, P, As or Pb, which can be replaced by (1) silicon and / germanium, (2) hydrogen, and (3) conventional hydrocarbons, silanes, or suitable substitutes. To refer to a compound or mixture of compounds that essentially comprises one or more dopant atoms, it may include one or more rings. Also, a "major surface" of a structure or feature is a surface defined in part by the largest axis of the structure or feature (eg, if the structure is round and has a radius greater than its thickness, the radial surface (s) Is the major surface of the structure; however, if the structure is square, rectangular or elliptical, then the major surface of the structure is typically a surface defined by two large axes of length and width).

Exemplary _cyclosilane compounds of formula (AH _z ) _zk and exemplary methods for preparing them are described in more detail in co-pending application No. 10 / 789,317, filed February 27, 2004 (Attoney Docket No. IDR0020). It is. Representative hetero (cyclo) silane compounds, doped silane intermediates, exemplary methods for their preparation and techniques for determining and / or controlling levels of dopants in precursor inks, active membranes, September 24, 2004, September 2004 Co-pending applications Nos. 10 / 950,373, 10 / 949,013 and 10 / 956,714, filed 24 October, 1 October 2004, respectively, are described in more detail and described in more detail: (AH _z ) _n (DR ¹ ) _m , wherein n is 2 to 12, m is 1 to 2, and each n examples of A are independently Si or Ge, and each n of z Examples are independently 1 or 2, each m example of D is Sb, As, P or B and an example of each m of R ¹ is alkyl, aryl, aralkyl, or AR ² ₃ , where R ² is hydrogen , Alkyl, aryl, aralkyl, or A _y H _{2y +1} , where y is an integer from 1 to 4, and (A _n H _z ) _m (DR ¹ _{3 -m} ) _q Wherein n is an integer of 3 to 12, z is (nq) to (2n + 2-q), m is an integer of 1 to 3, and each n × m of A is Si or Ge, D is Sb, As, P or B, q is generally 1 or 2 and examples of each (3-m) × q of R ¹ are independently H, alkyl, aryl, aralkyl, or AR ³ Where R ² is hydrogen, alkyl, aryl, aralkyl, or A _p H _{2p +1} ( ₁ ≦ _P ≦ 4). Oligo- and polysilane compounds are disclosed in U.S. provisional applications 60 / 850,094 and 60 / 905,403 (Attoney Docket Nos. IDR0881 and IDR 0883), filed October 6, 2006 and May 5, 2007, respectively. Polysilanes of H-[(AHR) _n (cA _m R ¹ _2m-2 ) _q ] -H, wherein each example of A is independently Si or Ge; Each example of R and R ¹ is independently H, —A _b H _{b +1} R ² _b , wherein R is H or aryl, or aryl, but if q = 0 and A is Si, then R is not phenyl ; If q = 0, (n + b) ≧ 10, if n = 0 q ≧ 2, and if n and q are not both ndl, then (n + q) ≧ 2; Each example of m is independently an oligosilane or polysilane having from 4 to 6 and necessarily comprising (i) hydrogen and (ii) silicon and / or germanium having a molecular weight of 450 to about 2300 g / mol and a composite of less than 2.5 Having a dispersion index, cured to form an amorphous hydrogenated semiconductor, and then annealing and / or irradiating enough to reduce and at least partially crystallize the hydrogen content of at least that amorphous hydrogenated semiconductor, A film with a carbon content not greater than 0.1 at% is formed.

Typically, although not always necessary, the liquid semiconductor ink further comprises a solvent, preferably cycloalkane. Thus, when using an ink that necessarily includes a Group IVA component source (silane based precursor for Si or doped Si), forming the semiconductor layer 30 may further include drying the liquid precursor ink after deposition. Can be. United States applications 10 / 616,147, 10 / 789,317 and 10 / 789,274, filed July 8, 2003, February 27, 2004, and February 27, 4002, respectively (Attorney Docket Nos. KOV-004, IDR0020 and IDR0080).

After deposition (and generally at least partial drying), the semiconductor layer is pending for pending US patent applications 10 / 789,274 and 10 / to form an amorphous, hydrogenated (doped) silicon (a-Si: H) layer. It is generally cured by heating as described above in 949,013 (Attoney Docket Nos. IDR0080 and IDR 0302, filed Jan. 27, 2004 and Sep. 24, 2004, respectively). When the semiconductor layer occurs or is formed from (cyclo) silanes and / or hetero (cyclo) silanes, the curing / heating step may remove by-products such as undesired precursor / ink components or volatile carbon containing species or a The hydrogen content of the -si layer can be reduced (this is particularly desirable if laser crystallization is to be used after semiconductor film formation). When the semiconductor layer occurs or is formed from hetero (cyclo) silane, the curing / heating step may also activate some of the dopants in the hetero (cyclo) silane, but in many embodiments dopant activation is likely to occur during laser crystallization.

In addition, the doped semiconductor layer may be deposited on the gate metal and the semiconductor layer directly by partially printing the liquid semiconductor precursor ink (e.g., filed September 24, 2004 and August 11, 2005). See pending US patent applications 1 / 949,013 and 11 / 203,563 (Attorney Docket Nos. IDR0302 and IDR0213). The latter approach to forming MOS TFT structures can be cost effective by (i) effective use of semiconductor precursor materials and (ii) semiconductor deposition and patterning combinations in one printing step.

Blanket deposition may include, for example, evaporation, physical vapor deposition, sputtering, or chemical vapor deposition as is known in the art. Optionally, blanket deposition includes, for example, spin-coating an ink comprising (cyclo) silane, polysilane or metal nanoparticles (which may be passivated) and a solvent and curing the ink (eg See, for example, US Patent No. 6,878,184 and US Patent Application No. 10 / 749,876, filed Dec. 31, 2003). Metals that can be deposited by such methods include elemental metals such as aluminum, titanium, vanadium, chromium, molybdenum, tungsten, iron, nickel, palladium, platinum, copper, zinc, silver, gold, and the like; General alloys of such elements such as aluminum-copper alloy, aluminum-silicon alloy, aluminum-copper-silicon alloy, titanium-tungsten alloy, Mo-W alloy, aluminum-titanium alloy, and the like; And electrically conductive metal compounds such as nitrides and silicides of elemental metals (eg, titanium nitrides, titanium silicides, tantalum nitrides, cobalt silicides, molybdenum silicides, tungsten silicides, platinum silicides, and the like). In another embodiment, the blanket deposition step may comprise spin-coating an ink comprising a metal containing material, the metal containing material comprising one or more of the metal nanoparticles and / or organometallic precursors of the metals described above. Wherein the method may further comprise curing or annealing the metal, organometallic precursor (s) and / or metal nanoparticles prior to the laser patterning step.

This application describes a design and several process flows for manufacturing printed self-aligned tom gate TFTs. The process flow affects the doped glass printed in at least one of three ways:

Printed doped glass provides a dopant source for source / drain doping;

Printed doped glass defines space for the gate metal and ensures close alignment (eg reasonably acceptable) to the source / drain regions / terminals;

Printed doped glass functions as an interlayer dielectric; Other interlayer dielectrics may be formed over the doped glass pattern and the gate electrode. (In one embodiment, removing a portion of the doped glass pattern leaves portions of the doped glass pattern under the interlayer dielectric film).

The present invention generally allows the formation of gate line widths smaller than 10 μm by forming transistor gates in the spaces between the printed structures. However, as the volume of the drop is expected to decrease later in widely used printing techniques such as inkjetting, gravure lithography and offset lithography, the space between such printed structures is also expected to decrease, and the present invention It will be possible to form a gate width smaller than the corresponding minimum width of the printed structure.

The invention will, in various aspects, be described in greater detail below with reference to exemplary embodiments.

Self-aligned source / drain  Formation of gate structure

1A-1E, an exemplary process flow is shown. The example process of FIGS. 1A-1E first forms a gate dielectric before printing the doped glass substrate. The transistor channel (eg, essentially comprising or consisting of amorphous or polycrystalline silicon) is thus protected from contamination by dopants from the doped glass deposited next.

Referring to FIG. 1A, a physically isolated silicon film generally prints or coats molecular and / or nanoparticle-based silicon inks on a substrate 1 and then (eg, heats) a (poly) silicon thin film 2. Or by curing). Optionally, it is deposited by conventional silicon films (e.g., by PECVD, LPCVD, sputtering, etc.) and by UV laser exposure, heating or RTA annealing (optionally in the presence of crystal catalysts such as Au, Ni, Al, etc.). After crystallization, the polycrystalline film can be patterned by low-resolution photolithography and / or selective etching. When the silicon film is crystallized by laser annealing, it is possible to simply remove the unexposed, amorphous portion of the deposited silicon film by selective etching according to known techniques. The substrate preferably comprises a silicon substrate, a glass slip or sheet, or a plastic or metal substrate (one of which may optionally be rigid or flexible, and in the case of metal, may have a thin oxide layer thereon).

Substrate 1 generally comprises a conventional mechanical support structure. Suitable electrically inert or inert substrates may include glass plates, glass disks, glass sheets, ceramics, dielectrics and / or plastics. Optionally, suitable electrically conductive substrates may include semiconductor (eg, silicon) wafers, semiconductor disks, semiconductor sheets, semiconductor thin films and / or metals. If the substrate comprises a metal sheet and / or a thin film, the device may further comprise an inductor and / or a capacitor, and the method may further comprise forming an inductor and / or capacitance from the metal substrate. Such electrically conductive substrates, however, may include a structure formed in a metal substrate where the electrical contact is made with the device on the insulating material (eg, one or more metal pads of an insert, an inductor and / or capacitor for an EAS or RFID tag; respectively 2004 US Patent Application Nos. 10 / 885,283 filed July 6, July 31, 2004, October 8, 2004 (Attorney Docket No. IDR0121) and / or US Provisional Application Nos. 60 / 592,596 and 60 / Except for 617,617 (Attorney Docket Nos. IDR0311 and IDR0271), it must have an insulating layer between it and another electrically active layer or substrate (eg, semiconductor layer 2). Preferably, the substrate comprises a member selected from the group consisting of semiconductor wafers, glass plates, ceramic plates or disks, plastic sheets or disks, metal sheets, metal sheets or disks and their thinned or stacked combinations, wherein the electrically conductive member is It generally has an insulating layer (e.g. a corresponding oxide layer) thereon.

Forming the semiconductor thin film layer 2 includes printing a semiconductor precursor ink on the substrate 1 to form a pattern, drying the ink, curing the ink (generally across the ink, By low polymerization and / or polymerization of silanes, increasing the average molecular weight, increasing the viscosity, and heating and annealing the dried ink for a time sufficient to reduce the volatility of the mixture), to form a polycrystalline film. And partially or substantially completely crystallizing the semiconductor film pattern. The semiconductor thin film layer 2 generally contains one or more Group IV elements, preferably polysilicon, silicon-germanium. A typical semiconductor layer 2 may have a thickness of about 30, 75, 100 nm to about 200, 500 or 1000 nm or any range in between. The film thickness can be selected to optimize the electrical properties of the transistor.

In various embodiments, the semiconductor layer 1 may include one or more Group IVA elements (eg, silicon and / or germanium), so-called "III-V" materials (eg, GaAs), II-VI (or Carl). A dopant (B, P, As or Sb) consisting essentially of or consisting of a lightly doped inorganic semiconductor material, such as a cogenide semiconductor, and at a concentration of ˜10 ¹⁶ to 5 × 10 ¹⁸ atoms / cm 3 It further includes. Exemplary lightly doped semiconductor films are disclosed in U.S. Application No. 10 / 949,013, filed on September 24, 1004, filed at Attorney Docket No. IDR0302. In one embodiment, the semiconductor (transistor channel) layer 2 may be lightly doped (eg having ^a dopant concentration of about about 10 ¹⁶ to about 5 × 10 ¹⁸ ). When formed from silane-based inks, the lightly doped semiconductor layer 2 may have a concentration profile in the amorphous state (eg dopant concentration as a function of semiconductor layer thickness). That is, it may have a uniform concentration through substantially the entire thickness of the semiconductor layer. For example, the semiconductor layer 2 may comprise a substantially uniform layer of semiconductor material doped on the substrate, the doped semiconductor material comprising (a) hydrogenated, comprising at least one of silicon or germanium, Amorphous or partially polycrystalline Group IVA elements, and (b) dopants. In a particular embodiment, the group IVA element of the thin film structure may essentially comprise or consist of silicon, and the dopant (which may be B, P, As or Sb, preferably B or P) is described herein. May have a concentration.

Referring to FIG. 1B, the gate dielectric 3 is thermally oxidized in the semiconductor layer 2 or, optionally, prints or coats an appropriate dielectric precursor and converts it to a dielectric film (eg, tetraalkylsiloxane or tetraalkyl). Liquid phase deposition of a SiO ₂ precursor such as silane) or deposition of other metal oxide (s) (eg, TiO ₂ , ZrO ₂ , HfO _2, etc.) or conventional CVD, PECVD, LPCVD or silicon oxide or nitride It can be formed on the semiconductor (for example (poly) silicon) film 2 by sputter deposition of the layer. As shown in Fig. 1C, a doped glass film 4 is then printed onto the gate dielectric 3 (e.g., by ink jetting, gravure printing, or the like). In one embodiment, a gate dielectric film 3 is formed on the entire surface of the semiconductor thin film layer 2, and then the doped glass pattern 4 is printed thereon. The layout of the doped glass pattern is necessarily the same as the layout intended for the source-drain structure of the TFT.

The gap 5 between the printed doped glass regions defines the position of the gate metal. The width of the gap may range from 1-100 μm (preferably 1-10 μm, and in some embodiments 1-5 μm). During high temperature annealing, the dopant of the doped glass moves through the gate dielectric to the polysilicon film defining the source / drain regions 5. The temperature at which the dopant of the doped glass diffuses through the gate dielectric is sufficient for doping the source / drain terminals, but leaving the channel region 7 undoped, preferably higher than at least 700 ° C. and 1100. Lower than ℃.

Preferably, the process of printing the doped glass utilizes a tool capable of simultaneously depositing N-type and P-type doped glass in different regions of the circuit. One embodiment is at least separated by a distance (eg, a plurality of such distances) corresponding to or matching the distance between the regions of the N-type and P-type transistors of the circuit, for example, on the same gantry. An ink jet printer with two ink jet heads is used. These two inkjet (IJ) heads provide storage space for N-type and P-type doped glass precursors (e.g., inks comprising doped spin-on glass precursors or other formulations). Can be connected correspondingly, and can distribute N-type and P-type doped glass to different regions of the circuit with the same printing path.

Examples of precursors for doped glass include conventional spin-on-dopant (SOD) formulations, custom versions with increased viscosity (eg, replacing or diluting solvents of conventional formulations with similar or compatible solvents of high viscosity). Circulating with dopant substituents such as " customized &quot;), and doped molecular silicon ink formulations (e.g., cyclo-Si ₅ H ₉ PR ₂ ) that can be oxidized to low temperatures (e.g. up to 400 ° C) after deposition. , Linear or branched silane oligomers or polymers, wherein R is lower [C 1 -C 4] alkyl, phenyl or C 1 -C 4 -alkyl substituted phenyl), or dopant precursors in the formulation (eg, tert ( tert) -butylphosphine), oxidized and doped molecular silicon ink with dopant precursors or dopant substituents thereon in the formulation (mono-, di-, or tri-tert-butylphosphine or oxidized analogs thereof) Formulations (e.g., net Ring, linear or branched silane oligomers or polymers (eg cyclo-Si ₅ O ₅ H ₁₀ ), and phosphorous and boron components (eg di-n-butyl Organophosphorous compounds such as phosphate and the like) and glass forming formulations (eg, so-called sol-gel formulations) comprising a borate component (eg, tri-t-butylborate, etc.). . Suitable dielectrics can also include phosphorus and oxygen (which may further include silicon, carbon, hydrogen and / or nitrogen), boron (which may further include silicon, carbon, hydrogen, oxygen and / or nitrogen), arsenic and / or antimony One of which may further comprise silicon, carbon, hydrogen and / or oxygen) and / or the like. Exemplary phosphorus-containing dielectrics include:

Organic oxophosphorus compounds and acids (eg, P ₂ O ₃ , P ₂ O ₅ , POCl _3, etc.);

Phosphosilicates;

Monomolecular, bimolecular, and / or low polymerizable phosphates (eg meta- and / or polyphosphates);

Phosphonates, phosphinates, phosphines;

Organic oxophosphorus compounds and acids (eg, alkyl (aryl) phosphates, phosphonates, phosphinates and their condensates; and

Alkyl and / or arylphosphonic and / or phosphonic acids.

Exemplary boron containing dielectrics include:

Organoboron compounds and acids (eg boric acid, B ₂ O ₃ );

Borosilicates, borazoles and polymers thereof;

Boron halides (eg BBr ₃ );

Borane (eg B ₁₀ H ₁₀ ), and sila- and / or azaborane; And

Organoboron compounds and acids (eg, allyl / aryl boronic acids, borates, boroxines and boraxoles, borane complexes, etc.) /

Exemplary arsenic and / or antimony-containing dielectrics include:

As ₂ O and Sb ₂ O ₃ Oxo- and / or aza-like compounds of the above compounds; And

Asinosilanes such as cyclo-As ₅ (SiH ₃ ) ₅ .

Thus, the source and drain terminals may comprise (i) a Group IVA element, a III-V compound semiconductor such as GaAs, or a II-VI (or chalcogenide compound) semiconductor such as ZnO or ZnS, and (ii) a dopant component. Can be. Preferably, the semiconductor comprises a group IV element (eg Si and / or Ge) and a dopant selected from the group consisting of B, P, As and Sb.

In various embodiments the gate has a width of at least 0.1 micron, 0.5 micron, 1 micron or 2 microns. In one embodiment, the minimum gate width is about 5 microns. The gate may have a length of about 1 μm to about 1000 μm or any value therein (eg, about 2 μm to about 200 μm, or about 5 μm to about 100 μm, etc.), and about 50 nm to It can have a thickness of about 10,000 nm or any range of values therein (eg, about 100 nm to about 5000 nm, or about 200 nm to about 2000 nm, etc.). The source and drain terminals may have a thickness of 10 to 1000 nm or any range of values therein (eg, 100, 200 or 250 Hz to 10,000, 1,000 or 500 Hz).

Referring to FIG. 1E, gate metal 8 is a suitable gate metal precursor (eg, ink or organometallic compound (s) including metal nanoparticles, doped molecules and / or nanoparticle based silicon ink (s), Silicide precursor ink (s), etc.) can be printed by depositing at least in a gap defined by the printed doped glass pattern, and then converting it to a gate metal. The use of doped silicon inks may further require high temperature annealing or laser radiation to activate the dopant or to form polycrystalline silicon to achieve sufficient conductivity. Optionally, the precursor of the seed layer may be printed in the gap defined by the printed doped glass pattern, and gate metals (eg, Ag, Au, Cu, Pd, Pt, etc.) may be printed on the seed layer. It may be electroplated or non-electrically plated. The seed layer may require an activation step before the plating process.

Printing of the gate metal precursor may include ink-jetting, gravure printing, offset lithography, and the like. In addition (or optionally) printing the gate metal may coat or print the gate metal precursor and partially expose it to laser radiation to alter its dissolution properties in the exposed area (eg December 2003). US patent application Ser. No. 10 / 749,876, filed 21. Upon washing the unexposed areas, the gate metal precursors that have been irradiated remain on the back side (so-called "negative" patterning or development) to form gate metals, optionally after further curing or annealing steps. Optionally, "positive" patterning or development where the areas exposed to radiation are cleaned may be employed. This embodiment (including the positive patterning embodiment) may provide an advantage in the patterning of high resolution metal gates that cannot be achieved directly by the direct printing method. However, for the gate "metal" includes doped polysilicon.

Metal-containing inks (and any other printable inks disclosed herein) can be originally printed by any prior art. For example, printing may include inkjet printing ("inkjetting"), screen printing, gravure printing, offset printing, flexography (flexo printing), spray coating, slit coating, extrusion coating, uneven coating, microspotting , Stencil, stamping, syringe dispensing and / or pump dispensing of the metal containing ink in a predefined pattern. This ink necessarily includes or consists of a metal precursor material or solvent. In general, metal precursors suitable for printing or (optionally) plating include metal mixtures or nanoparticles of metals such as titanium, copper, silver, chromium, molybdenum, tungsten, cobalt, nickel, gold, palladium, platinum, zinc, iron, etc. Nanocrystals), or their metal alloys, preferably silver or gold (or their metal alloys). Such nanoparticles or nanocrystals are generally not passivated (with one or more surfactants), are provided with one or more surface ligands (eg, H atoms adsorbed thereon), or are not passivated. May remain. Plating is, for example, laser recording of a metal (eg platinum) seed layer using nanoparticles or organometallic compounds of the metal, and then bulk conductor (eg, bulk) on the laser recorded seed layer. , Co, Ni, Cu, etc.) or a semiconductor (eg, Si and / or Ge) may optionally be deposited (eg, by non-electrical or electroplating). Optionally, the ink may necessarily comprise or consist of a conventional paste comprising a powder of one or more such metals or an alloy thereof in a conventional binder.

The metal containing ink may be dried by conventional and / or other known processes. For example, the metal precursor ink may be dried by heating a substrate comprising the printed metal precursor ink for a temperature and time effective to remove the solvent and / or binder. Suitable temperatures for removing the solvent from the printed ink can be in the range of about 80 ° C. to about 150 ° C., or any range therein (eg, about 100 ° C. to about 120 ° C.). Suitable times for removing the solvent from the printed ink can be from about 10 seconds to about 10 minutes or any range therein (eg, about 30 seconds to about 5 minutes, or about 1 minute to 3 minutes, etc.) have. Such heating can occur in a conventional hotplate, conventional furnace or oven, optionally in an inert atmosphere (as described above).

The metal-containing material dried from the ink may also have its electrical and / or physical properties (eg, conductivity, form, electrophoretic and / or etch resistance, stress and / or surface deformation, etc.), and / or underlying gates. It may be annealed at a temperature and time sufficient to enhance its adhesion to the oxide. When metal-containing inks are generally deposited (blanket) or printed, annealing is generally performed to form a metal film to which a resist is applied for subsequent laser patterning. In addition, when laser recording the metal precursor ink directly results in the patterned metal and / or metal precursor, annealing is generally performed to form a metal layer with improved conductivity, adhesion, and the like. Such annealing can include annealing already dissolved metal nanoparticles or converting the patterned metal precursor layer into a patterned metal. Suitable annealing temperatures may generally be in the range of about 100 ° C. to about 500 ° C. or in any range therein (eg, about 150 ° C. to about 400 ° C.). Suitable times for annealing can range from about 1 minute to about 2 hours, preferably from about 10 minutes to about 1 hour, or any range of time therein (eg, from about 10 minutes to 30 minutes). Annealing can be carried out in conventional furnaces or ovens, optionally in an inert or reducing atmosphere (as described above). Thus, the method may further comprise annealing the patterned metal gate sufficiently to enhance the electrical, physical and / or adhesive properties of the laser patterned metal gate.

In one embodiment, the gate metal precursor ink can remove moisture from the printed doped glass pattern, which effectively defines the precursor ink into the gap defined by the doped glass pattern. The doped glass pattern may be processed prior to deposition of the gate metal precursor ink to ensure moisture removal (eg, by coating with a plasma exposure, a fluorate layer or other material having similar moisture removal properties, and the like). Similarly, the gate metal precursor ink and / or the doped glass precursor may include additives to ensure moisture removal of the gate metal precursor ink from the doped glass pattern. In an alternative embodiment, the gate metal precursor wets the printed doped glass pattern such that the gate metal precursor extends beyond the cap region between the portions of the doped glass pattern and at least partially covers the doped glass pattern. This embodiment is desirable to reduce gate-induced drain leakage in the device.

Thus, an exemplary process flow for manufacturing a thin film transistor according to the present invention may include the following steps:

Applying lightly undoped silane to form an amorphous Si thin film;

(Optional) removing hydrogen of amorphous Si;

Depositing, growing or forming gate oxides (eg by thermal oxidation);

Crystallizing lightly doped or undoped amorphous Si (eg by excimer laser treatment or furnace treatment);

Printing or patterning the source and drain regions by depositing doped glass;

Activating or diffusing the dopant into the source and drain regions (eg by heat treatment);

(Optional) depositing a metal seed layer;

Depositing a gate metal;

(Optional) conventional gate metal annealing step;

A passivation (eg oxide or nitride) step.

Oxide Formation After Doping Glass Printing

2A-2E show an optional process flow diagram that preferably couples gate dielectric formation by thermal oxidation of polysilicon with driving of the dopant from doped glass in situ or in one process step. However, the most important aspect of the second exemplary process is that gate oxide growth is achieved before significant dopant diffusion occurs.

Silicon film 12 is generally by the same process as in FIG. 1A, ie by printing or coating molecular and / or nanoparticle based silicon ink on substrate 1 and converting it to silicon thin film 2, or The silicon film is formed by vapor deposition (for example, by PECVD, LPCVD, sputtering, etc.) as conventionally. In either case, the silicon film is generally crystallized by UV laser exposure, heating or RTA annealing (optionally in the presence of crystal catalysts such as Au, Ni, Al, etc.). Next, referring to FIG. 2B, doped glass 14 is printed on the (poly) silicon film (eg, inkjetting, gravure or offset lithography printing, etc.). The layout of the doped glass pattern is necessarily the same as the intended layout of the source-drain region. The optionally printed doped glass pattern may correspond to lightly doped extended regions (eg, lightly doped drain) in the TFT, in which case the next doped glass pattern is relatively high doped source / drain Can be printed to form areas. The gap between the printed doped glass regions generally defines the location of the gate metal and gate dielectric. The width of the gap may be in the range of 1-100 μm, as described above (preferably 1-10 μm, or 1-5 μm). After printing, the doped glass pattern is selectively cured to a temperature sufficient to substantially ensure that the dopant does not diffuse into the silicon film or from the doped glass into the gaps defining the gate metal and dielectric. In one embodiment, a plurality of openings are made in the doped glass pattern and expose the surface of the dopant containing (eg lightly doped) region of the semiconductor thin film layer.

Referring to FIG. 2C, SiO 2 or other metal oxides (eg, may be formed by thermal silicon oxidation of the exposed poly-Si layer, printing or coating of a suitable dielectric precursor, and converting it into a dielectric film). Liquid phase deposition of TiO ₂ , ZrO ₂ , HfO _2, etc., or conventional silicon oxide and / or nitride deposition methods (eg, sputtering of a primary target to a PECVD, LPCVD, oxygen and / or nitrogen source, etc.). have. Preferably, silicon oxide is employed.

Silicon oxidation of the exposed gate region of the poly-Si film can be achieved by heating the film to a temperature higher than 600 ° C. in a suitable atmosphere (air, O ₂ , ozone, N ₂ O, wet or dry steam, or a combination thereof). Can be. The maximum temperature is preferably lower than 1000 ° C., more preferably lower than 900 ° C. to reduce, suppress or prevent dopant diffusion from the doped glass into the channel region.

The gate dielectric film 13 in the present electronic device can include any of the materials for the gate dielectric film described herein. The gate dielectric film 13 may have a smaller width and length than the corresponding regions of the gate metal layer to be formed next when it is wet etched, but the two layers have substantially the same width and length when dry etched. will be. The gate dielectric film 13 may have a thickness of 20 kV to 400 kV or any range therein (eg, 30 to 300 kV, or 50 to 200 kV, etc.). Optionally, a thicker gate dielectric layer (e.g., in the range of 500 to 2000 GPa, in some embodiments, about 1500 GPa) may be used, preferably a metal having a higher dielectric constant than silicon oxide or aluminum oxide. . In one embodiment, the gate dielectric film 13 has a thickness greater than the thickness of the highly doped source and drain terminals to minimize the possibility of the source and drain terminals forming an electrical connection to the gate metal layer. However, in high-speed transistors, thin film dielectric films are generally preferred. Typically, referring now to FIG. 2D, after the gate oxide 13 is formed, the temperature may diffuse (or “drive”) the dopant into the semiconductor film 12 to form the source / drain regions 16. Raised sufficiently (eg, above 800 ° C.). Also, at elevated temperatures, silicon oxidation can occur simultaneously with the driving of the dopant. The annealing temperature of the doped glass required to induce significant dopant diffusion is preferably higher than the temperature for forming a dielectrically efficient dielectric, but should not be higher than the maximum process temperature of the substrate (e.g., such as aluminum Temperature for metal sheets of relatively low melting point materials, ie temperatures not higher than 600 ° C. [and assuming laser use], temperatures not higher than 1100 ° C. for stainless steel sheets).

Next, referring to FIG. 2E, the gate metal 18 is formed in substantially the same manner as the gate metal 8 of FIG. 1E.

Doping Glassy  passivation( passivation )

3A-3C further reduce potential false diffusion problems from doped glass during gate dielectric formation by depositing barrier and / or passivation layer 25 or generating similar inert layers 25 on the doped glass. Another process flow is shown. Thus, in another embodiment, a thin dopant-depleting layer 25 is formed over the printed doped glass pattern 24. This layer is intended to prevent dopant diffusion into the channel region 27 during dopant activation. Formation of this layer can be accomplished in a variety of ways (eg, by depositing an original undoped glass or silicon nitride film [acting as a buffer]). Membranes that effectively remove typical dopants (eg, phosphorus or boron) may also be used. Optionally, hot water leaving the dopant depleted surface layer evident a portion of the dopant from the exposed surface but leaving sufficient dopant in the glass bulk (especially adjacent to the interface with the underlying silicon 22) useful for source / drain doping, or By steam exposing the patterned doped glass film. In addition, the thin passivation and / or dopant depletion layer 25 may be exposed by exposing the patterned glass film to conditions that change its surface properties to prevent significant dopant diffusion into the channel, eg, ozone, N ₂ O. It can be formed by exposing it to a back.

Referring to FIG. 3A, a passivation or barrier layer 25 (which may be a dopant depletion layer or an undoped passivation layer) may be applied or formed prior to dopant driving at a temperature much lower than the temperature employed to induce dopant diffusion. . Such barrier layers may be formed of dopants from the doped glass into adjacent structures (e.g., on top of the poly-Si channel 27 [see FIG. 3B] or then formed gate dielectric 23 and / or interlayer dielectric). Effectively prevents spread. Preferably, passivation / barrier layer 25 necessarily comprises undoped silicon oxide free of barriers for subsequent gate dielectric formation. The process to produce the barrier layer involves the liquid phase deposition of SiO ₂ from suitable precursor (s) (eg, an aqueous mixture of hydrofluorosilicic and boric acid) capable of forming a thin layer of high quality gate dielectric at room temperature. It includes. Alternatively, passivation layer 25 may be formed by filtering the dopant from the surface layer of doped glass layer 24 according to known methods.

Referring to FIG. 3B, when the gate dielectric is formed by printing or coating a suitable gate dielectric precursor and then curing / annealing (eg, using liquid deposition or conventional methods), the side of the layer is a doped glass pattern. There is no need to be limited to the gap between the structures 24. Indeed, in some examples, it may be desirable for at least a portion of the gate dielectric layer 23 to completely or at least partially cover the surface of the doped glass pattern (eg, as shown in FIG. 3B). In such a case, the gate dielectric layer may provide the barrier / passivation layer 25 by itself and may reduce, suppress or prevent false diffusion of dopants from the doped glass layer 24 and the source / drain patterns 26. . The formation of the source / drain regions 26 is substantially the same as the formation of the source / drain regions 16 of FIG. 1D.

In some cases, incorrect diffusion of the dopant into the pre-oxidation channel region 27 may be desirable due to improved oxidation rates of the doped material. This improved oxidation rate will form a thick gate oxide 23 at the edge of the channel 27. This thick dielectric reduces the electric field at the edge of the drain 26, thereby reducing the gate induced drain leakage (GIDL).

Referring now to FIG. 3C, gate metal 28 is an appropriate gate metal precursor (eg, metal nanoparticles or organometallic compounds) with a gap 25 defined by a doped glass pattern 24 printed as described above. (S), doped molecules and / or nanoparticle-based silicon ink (s), silicide precursor ink (s), etc.) and are printed by converting it to a metal material, such as the gate metal of FIG.

Source / drain contacts and wiring formation

The following process flows for forming source / drain contacts and wiring can be used for any device structure and / or processes described above.

Gate as a mask for source / drain contact etching

4A-4D illustrate exemplary embodiments of processes for forming source / drain contacts and interlayer dielectric (ILD) on the basic TFT structures of FIGS. Referring to FIG. 4A, this exemplary process flow is a mask for etching the doped glass pattern 130 to expose the contact regions of the source / drain regions 112 and 114, partially removing the doped glass pattern 130. Use a printed metal gate 140 to switch. This embodiment ensures a relatively close distance (and thereby reduces resistance) of the source / drain contacts, since no organic ILD (interlayer dielectric) is present over the source / drain regions 112/114, and the source / drain contacts Enable selective silicide on the phase. In addition, extending the gate metal 140 over the region of the gate dielectric 120 and leaving a portion of the doped glass 130 under the gate metal 140 can reduce gate induced drain leakage.

Source / drain regions 112/114 and channel 116 are formed on substrate 100 similar to source / drain regions 6 and channels 7 of FIG. 1D. The undoped semiconductor layer portion 110 remains after dopant driving from the doped glass substrate 130. The gate dielectric 120 is formed similar to the gate dielectric 3 of FIG. 1C or similar to the gate dielectric 13 of FIG. 2C. An oxide layer 122 is formed during the oxidation of the exposed surface of the semiconductor layer (eg, 110) that is not covered by the doped glass layer 130.

As shown in FIG. 4bd, the etching of the doped glass pattern 130 and the exposed dielectric layer 122 may include HF-based etchant (eg, buffered etch (BOE)), NOE, conventional pad etching. Conventional pyridine: HF etchant solution, etc.), exposure to one or more suitable etchant including, but not limited to, HF-based or product vapor or gases, or plasma etching. The etchant may be used in the silicon and metal gate layer 140 underneath the etch rate of the gate dielectric 122 and the doped glass 130 to enable substantially complete removal of the doped glass without any substantial removal of the silicon or gate metal. It is selected to be sufficiently larger than the etch rate.

Referring now to FIG. 4C, after the etching and optional cleaning steps (not described), the wiring metals 150 and 152 are printed on the exposed source / drain contacts. Although not shown in FIG. 4C, the wiring metal may also be printed on the exposed metal, but as is known in the art, is within the “pad” area of the page rather than in the plane. In one embodiment, the wiring metal form 150 or 152 may also contact the gate metal 140 to form a diode-configured transistor (not shown). Printed wiring metal is used to contact transistors in the same layer and provide a small contact area through the through structure. The resistance of the wiring metal is preferably lower than 10 Ohms / square.

In order to ensure good contact, the structure of FIG. 4C also provides a contact area at the interface of the wiring metal 150/152 with silicon or between the wiring metal 150/152 and the underlying silicon 112/114. It can be annealed to form silicides through the entire film thickness of. Suitable silicide forming metals include, but are not limited to, Al, Ni, Pd, Pt, Mo, W, Ti, Co, and the like. The wiring metal is selected from such silicide forming metals. Optionally, the wiring metal precursor ink forms silicides and additives (eg, Ni organic) that are observed to lower the contact resistance between the wiring 150/152 and the doped silicon source / drain regions 112/114. Silver inks doped with metal). However, additives (eg Ni) may be separated from the silicon interface to form silicides.

After printing the wiring metal 150/152 (which may be formed by conventional processes such as sputtering and photolithography, but printing is preferred), referring to FIG. 4D, the interlayer dielectric 160 may be exposed to any exposed activity. Printed to cover the regions (eg gate 140 and source / drain regions 112/114), but via holes 162 / over appropriate regions (eg, over wiring 150/152). 164). The interlayer dielectric precursors may be glass forming formulations (eg, spin-on-glass formulations such as conventional organosilicates or organosiloxanes), organic dielectrics (eg, polyimide, poly (benzocyclobutyne) [BCB], etc.), Silicon oxide precursors (eg silane oxides such as Si ₅ H ₅ (OH) ₅ , etc.), or molecules and / or nanoparticle based silicone formulations (eg silane inks) that are oxidized after printing. .

Printing the interlayer dielectric 160 includes ink jetting, gravure, offset printing, and the like similar to other printable inks described herein. Optionally, patterning the interlayer dielectric may print or deposit an interlayer dielectric (eg, UV- and / or IR-photosensitive polyimide) and light it to change its dissolution property (s) in the irradiation area. (Eg, IR light, visible light or UV light). Exposing this layer to a suitable etchant or solvent (eg developer) will remove the exposed (positive) or unexposed (negative) regions of the interlayer dielectric forming the via holes.

In an alternative embodiment, the sacrificial material may first be printed at a location corresponding to the location of later formed via holes in the interlayer dielectric. The interlayer dielectric precursor is then printed or generally (blanket) deposited as described above. Upon curing the interlayer dielectric precursor, the sacrificial material of the via regions can decompose while forming via holes. Other means for removing the sacrificial material from the via holes are possible (eg, selective etching, etc.). The circuit is completed by printing interconnect metal connecting the respective contact pads with open via holes (see FIGS. 7B-7C and 8A-8C). The same techniques and materials as described above can be used.

Conductors in communication with one of the source / drain terminals or the gate terminal may also be coupled or coupled with another of the conductors. For example, in a diode-configured transistor, the conductor may be in electrical communication with one source / drain terminal and gate. In a capacitor-configured transistor, the conductor may be in electrical communication with both source / drain terminals. Optionally, a thin dielectric layer can be formed over the source / drain terminals, and a conductor can be formed thereon capacitively coupled to the underlying source / drain terminals.

ILD as mask for source / drain contact etching

5A to 5E show the structure formed during the alternative process for manufacturing the present TFT. Referring to FIG. 5A, a channel 210, a first source / drain region 212, a second source / drain region 214, and an undoped semiconductor (eg, Si) region 216 are described herein. It is formed on the substrate 200 as shown. Doped glass 230 and conductive gate metal 240 are printed over substrate 200 as described herein, and gate dielectric 220 and thermal oxides 222/224 are formed as described herein. do.

Similar to the process of FIGS. 4A-4D, the process of FIGS. 5A-5E is limited to the region between printed doped glass regions 230 (such as gate dielectric 210) and does not cover the doped glass pattern 230. (240) is used. However, in this embodiment, the first interlayer dielectric 240 is exposed during the etching of the doped glass pattern 230 to expose the source / drain regions 212/214 or contacts thereon (not shown). 240 and gate dielectric 220 are deposited to protect.

In FIG. 5B, the first interlayer dielectric 245 is printed to completely cover the gate metal and dielectric 220 and at least partially but not completely cover the doped glass pattern 230. Precursor inks for the first interlayer dielectric 245 include glass forming formulations (eg, spin-on-glass formulations [eg, silicates or organosiloxanes), organic dielectrics [eg, polyimide, BCB, etc.), Silicon oxide precursors (eg, silane oxides such as Si ₅ O ₅ H ₅ ), or molecules and / or nanoparticle based silicone formulations that are oxidized after printing as described herein.

Inkjetting, gravure, offset printing, and the like, for printing the first interlayer dielectric 245. Optionally, patterning the interlayer dielectric may print or deposit a long layer dielectric (eg, UV- and / or IR-photosensitive polyimide) and light it to change its dissolution property (s) in the irradiation area. (Eg, IR light, visible light or UV light). Exposing this layer to a suitable etchant or solvent (eg developer) will remove the exposed (positive) or unexposed (negative) regions of the interlayer dielectric forming the via holes.

Next, as shown in FIG. 5C, the doped glass pattern 230 and thermal oxide regions 222 and 224 remove the thermal oxide regions 222 and 224 and doped source / drain regions 212/214. Etch enough to expose. Etching the exposed doped glass pattern 230 and the exposed thermal oxide 222/224 generally removes the thermal oxide regions 222 and 224 and removes a portion of the first interlayer dielectric 245 from the gate metal 240. For a time sufficient to remain in the stomach, including HF-based wet etchant (e.g., BOE, NOE, pad etch, pyridine: HF, etc.), HF-based or HF-generated vapor or glass, plasma etch, etc. This is achieved by exposure to a suitable etchant, without being limited thereto. In many embodiments, some of the doped glass pattern 230 also remains over the doped source / drain regions 212/214. The etchant may be between the doped glass pattern 230 and the first interlayer dielectric 245, between the doped glass pattern 230 and the thermal oxide regions 222/224 or all three materials (ie, the doped glass pattern 230, the first). Although not selective in interlayer dielectric 245 and thermal oxides 222/224, the etchant may be doped glass to enable substantially complete removal of thermal oxides 222/224 without substantial removal of underlying semiconductors. The etch rate of 230 and thermal oxides 222/224 are selected to be sufficiently greater than the etch rate of the semiconductors raised below.

Thus, depending on the etching time, the etchant will remove only the relatively narrow portion of the doped glass pattern 230 while exposing only a small border or portion of the source / drain regions 212/214. In this case, all of the materials described above will be appropriate for the first interlayer dielectric 245 as long as its thickness is sufficient to protect the gate metal and dielectric given a selective potentially low etching for the doped glass 230.

Optionally, referring to FIG. 6A, the etching time is such that most of the doped glass pattern is removed and a small portion of the doped glass (or other insulator) 232 adjacent the gate metal 240 and the gate dielectric 220 remain. Can be selected. In this case, the interlayer dielectric 245 is selected to have a very small etch rate relative to the etch rate of the doped glass pattern. For example, organic insulators (eg, polyimide, BCB, etc.) can be selected in this embodiment. In these embodiments employing a passivation and / or dopant depletion layer on a printed doped glass pattern (see, eg, FIGS. 3A-3C), the undoped passivation / dopant-depletion layer is incorporated into the doped glass etchant. Can be chosen to have a very small etch rate relative to the etch rate of the doped glass pattern.

Next, the doped glass pattern 230 (see FIG. 5B) is etched to expose the source / drain regions 212/214 and leave the doped glass “rest” 232 (see FIG. 6A). Etching of the doped glass pattern and exposed thermal oxide regions 222/224 may generally be accomplished as described herein, but etchant has a high etch rate of the doped glass and thermal oxides 222/224. 245. For example, the etch rate of the doped glass and thermal oxides 222/224 with respect to the interlayer dielectric 245 is substantially dependent on the exposed doped glass without substantial removal of the interlayer dielectric layer 245. Large enough to enable complete removal). In embodiments in which the doped glass pattern 230 comprises or is based on doped silicon oxide and the undoped silicon region 216 comprises silicon or consists essentially of silicon, the interlayer dielectric layer 245 comprises silicon nitride. can do.

Referring now to FIGS. 5D and 6B, after etching the doped glass 230 and thermal oxide 222/224, the substrate may be (optionally) cleaned and the source / exposed wiring metal 250/252 exposed / Printed in the drain regions 212/214, respectively. As described elsewhere herein, the wiring metal 250/252 may also contact the gate metal 240 (not shown). Printed wiring metal 250/252 is used to connect transistors within the same layer or to provide low-resistance contact regions for overlapping via structures. If the interlayer dielectric 245 is selected to be suitable for subsequent high temperature processes (eg, silicate, silicon nitride, etc.), the metal silicide may be a source / source on one side of the wiring metal 250/252 and the gate metal 240. It may be formed at an interface between the drain region 212 and the source / drain region 214 on the other side. The resistance of the wiring metal is preferably 10 ohms / square or less.

The printing and forming of the wiring metal may include printing a suitable wiring metal precursor (eg, metal nanoparticles or organometallic compound (s), silicide precursor ink (s), etc.) and wiring it as described herein. It may include the step of switching to. Optionally, a precursor for the seed layer can be printed in the contact area and converted to the seed layer, and the wiring metal can then be electroplated or plated on the seed layer in a non-electrical manner. The seed layer may require an activation step before the printing process.

Optionally, patterning the wiring metal includes coating or printing the wiring metal precursor and partially exposing it to the laser beam so that the dissolution properties of the exposed printed wiring metal precursor change. When cleaning the exposed or unexposed areas (preferably unexposed areas), the irradiated wiring metal precursor is optionally left behind to form the wiring metal, after a further curing or annealing step. This embodiment can provide an advantage in the patterning of high resolution metal wiring that cannot be achieved with direct printing methods.

To ensure good contact, the structure can also be annealed to form silicide at the interface through the entire film thickness of the contact region between the wiring metal and silicon. Thus, in such an embodiment, the interlayer dielectric protecting the gate metal 240 during the etching of the doped glass pattern 230 may be compatible with the silicidation temperature.

5E and 6C, after wiring metal printing, a first interlayer dielectric 260/262/624 is over the gate 245 and the source / drain regions 212/214, but with the overlap level of metallization. It is printed to leave via holes 280 in the appropriate area for contact. Precursors of the interlayer dielectrics 260-264 are the same or similar glass forming formulations as those for the first interlayer dielectric 245 (eg, spin-on-glass formulations such as silicates or siloxanes, organic such as polyimide, BCB, etc.). Dielectric, silicon oxide precursors such as silane oxide, etc.), or molecules and / or nanoparticle based silicon or aluminum formulations that are oxidized after printing.

Printed as a mask for doping glass etching ILD

The process flows of FIGS. 7A-7D and 8A-8D use an interlayer dielectric 350/352/354 printed as a mask for etching doped glass 330 to expose source / drain regions 312 and 2314. do. The process flows of FIGS. 7A-7D and 8A-8D are primarily the first interlayer dielectric 350/352/354 (or the first interlayer dielectric 350 '/ 352' / 354 ', as shown in FIGS. 8A-8D). It is different in that it is a selective etching of the doped glass pattern 330 with respect to. In the processes of FIGS. 7A-7D, etching is optional, thereby enabling thinner printed interlayer dielectric patterns 350/352/354 as compared to the processes of FIGS. 8A-8D. In the processes of FIGS. 8A-8D, etching is not optional, thereby greatly widening the range of possible materials for printed interlayer dielectric patterns 350 '/ 352' / 354 'compared to the processes of FIGS. 7A-7D.

7A and 8A, a first interlayer dielectric 350/352/354 (or 350 '/ 352' / 354 ') completely covers the gate metal 240 and the exposed substrate region 300 and the semiconductor It may be printed to partially (but not completely) cover the island edge (eg, 316) as well as the doped glass pattern 330. Precursors of the first interlayer dielectrics 350 / 350'-354 / 354 'may include nitrides or oxides of silicon and / or aluminum, as well as any of the glass-forming formulations described herein. The interlayer dielectric can be printed or patterned as described herein.

Next, as shown in FIGS. 7B and 8B, the exposed doped glass pattern 330 and thermal oxide 322/324 may be formed of a first interlayer dielectric 350/352/354 (or 350 '' / 352 '' / 354). Etched to expose source / drain regions 312/314 in an area that is not substantially covered by '). Doped glass pattern 330 is etched as described elsewhere herein. In the process of FIG. 7B, the etchant typically has an etch rate of the doped glass 330 and the thermal oxide 322/324 of the first interlayer dielectric 350/352/354 or the source / drain regions 312/314. It is selected to be sufficiently larger than the etch rate of the first interlayer dielectric 350/352/354 and underlying source / drain regions 312/314 to allow substantially complete removal of the doped glass 330 without substantial removal. . In the process of FIG. 8B, the etchant generally has an etch rate of the doped glass 330 and thermal oxide 322/324 that is close to or substantially the same as that of the first interlayer dielectric 350 '/ 352' / 354 '. However, it is selected to be relatively higher than the etch rate of the underlying source / drain regions 312/314. Depending on the choice of interlayer dielectric and its thickness, the removal of the doped glass pattern can result in an undercut structure 332 (FIG. 7B) or 332 ′ (FIG. 8B). However, when the etch selectivity of the doped glass relative to the first interlayer dielectric is low (as shown in FIG. 8B), the first interlayer dielectric may be significantly thinner (etched first interlayer dielectric of FIG. 8B (356/357). / 358) with the first interlayer dielectric 350 '/ 352' / 354 'printed / patterned in FIG. 8A). In such a case, the printed / patterned first interlayer dielectric 350 '/ 352' / 354 'is greater than the thickness of the doped glass 330 (e.g., at least 1.5 times, at least 2 times, at least 3 times, at least 5 times). , Or more than 10 times). As shown in FIG. 8B, this arrangement can prevent the formation of the undercut structure 332.

In any case, the etch time is chosen such that most (but not all) doped glass layers are removed from above the source / drain regions 312/314. In particular, a small amount of doped glass 332 is left adjacent to the gate metal 340 and the gate dielectric film 320 covered by the first interlayer dielectric 350 or 350 '.

After the etching and optional cleaning steps (not shown), the wiring metal 360/362 may be printed on the exposed source / drain regions 312/314 as shown in FIGS. 7C and 8C. In addition, this wiring metal may also contact the gate metal (not shown). The printed wiring metal can be used to connect transistors in the same layer or to provide a low contact area for the via structure. If the interlayer dielectric is suitable for subsequent high temperature processes (eg, silicate, silicon, nitride, etc.), silicification of the source / drain contacts may be possible after deposition of the wiring metal 360/362. The resistance of the wiring metal is preferably lower than 10 ohms / square. Printing and forming of the wiring metal can be performed as described elsewhere herein.

After printing of the wiring metal 360/362, as shown in FIGS. 7D and 8D, the second interlayer dielectric 370 covers the exposed active regions (eg, gate and source / drain regions), but is a suitable region. Printed to leave via holes 380 in. The precursor of interlayer dielectric 370 may include the same glass-forming formulation and other materials as described herein for the interlayer dielectric.

In any embodiment of the present process (not necessarily limited to FIGS. 7A-8D), laser patterning may comprise depositing a resist material on a blanket deposited metal containing layer, (i) a predetermined width and / or (ii) a resist. Selectively irradiating portions of the resist material with light from a laser having a predetermined wavelength or wavelength band absorbed by (or by absorbing dye in the resist), the structure to be formed (in the case of FIGS. 7A-8D, the gate Developing the selectively irradiated resist with a developer to leave a pattern corresponding to metal 340 and / or wiring 360/362; note that these steps apply to both positive and negative resists), desired or Removing portions of the blanket deposited material that do not correspond to the predetermined pattern (generally by dry or wet etching), and remaining And substeps of removing the resist materials. The light may comprise a wavelength or wavelength band in the ultraviolet (UV) and / or visible light spectral band, but preferably has a wavelength in the infrared (IR) band. In such a case, the resist (or dye) absorbs or responds to the wavelength or band of the light, and the rays focus or direct to the desired or predetermined portion of the resist. Exemplary embodiments are disclosed in US Patent Application No. 11 / 203,563 (Attorney Docket No. IDR0213) filed August 11, 2005.

Optionally, the semiconductor layer (having characteristics of transistor channel 7, 17, 26, 116, 210 or 310, such as dopant level or concentration, for example) may print the substrate with doped or undoped semiconductor ink. By coating and irradiating the ink / substrate at the same time. In one embodiment, the process includes spin-coating an ink comprising a semiconductor precursor on a substrate and irradiating the ink with ultraviolet light during a substantial portion of the spin-coating step. This technique (also known as "UV spin-coating" in the following implementation) is described in more detail in pending US patent application Ser. No. 10 / 789,274, filed February 27, 2004 (Attorney Docket No. IDR0080). do. In another implementation, printing (which may include UV irradiation at the same time or immediately following) inkjet or gravure, flexographic, screen or Offset printing (or other deposition techniques for depositing material in selective areas of the substrate). In either case, the semiconductor layer generally has the next deposition in amorphous form in substantially simultaneous irradiation and is crystallized before further processing (eg, by heating or laser irradiation; US patent filed Sep. 24, 2004). See applications 10 / 950,373 and 10 / 949,013 (Attorney Docket No. IDR0301, IDR 0302). In many cases, such crystallization will activate at least a portion of the dopant.

The present invention preferably produces a printed self-aligned top-gate TFT having reliable and commercially acceptable electrical properties (eg, on / off rate, on / off rate, carrier mobility, V _t, etc.). Provides a low cost method for Printed and / or luminescence-defined semiconductor structures (and optionally, printed and / or radiation defined conductor structures) have (1) similar results to structures formed by the previous method, but compared to conventional process techniques. Have much lower unit costs and much higher yields (in hours or days rather than weeks or months), and (2) higher resolution patterning possibilities and similar or higher yields compared to conventional graphics printing techniques (e.g. inkjetting). Gives results.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations will be possible in light of the above teaching. The embodiments are various embodiments with various modifications as best suited for describing the gist of the present invention and its practical application, and whereby those skilled in the art to which the present invention pertains will be contemplated use. Have been selected and described as possible. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (10)

Forming a semiconductor thin film layer; Printing a doped glass pattern having a gap defining a channel region of a TFT on the semiconductor thin film layer; Forming a gate electrode comprising a gate dielectric film and a gate conductor over the gate dielectric film in the gap on the channel region or over the channel region; And Diffusing a dopant from the doped glass pattern into the semiconductor thin film layer. The method of claim 1, Forming the semiconductor thin film layer comprises printing a liquid ink including a semiconductor-containing precursor on a substrate. The method of claim 1, Forming the gap in the printing of the doped glass pattern, wherein the dopant is diffused into the semiconductor thin film layer regions to form source and drain terminals of the TFT. The method of claim 1, Forming the gate dielectric film on the entire surface of the semiconductor thin film layer, and then printing a doped glass pattern thereon; And Forming a gate conductor on at least said gate dielectric film in said gap, Forming the gate conductor comprises printing an ink comprising a gate conductor precursor on the gate dielectric layer. The method of claim 1, Removing at least a portion of the doped glass pattern to sufficiently expose the surface of the semiconductor thin film layer including the diffused dopant; And And forming a conductive wiring structure on the exposed surface of the semiconductor thin film layer including the diffused dopant. A semiconductor thin film layer; At least a portion of a printed doped glass pattern on the semiconductor thin film layer; A gate electrode in a gap on a channel region or over a channel region of the semiconductor thin film layer; And A dopant containing region in the semiconductor thin film layer on both sides of the channel region, At least two portions of the doped glass pattern define the gap above the channel region of the thin film transistor, And the gate electrode includes a gate dielectric layer and a gate conductor thereon. The method of claim 6, The dopant containing region includes a source and a drain region, and the doped glass pattern is on or over the source and drain regions of the semiconductor thin film layer. TFT). The method of claim 6, And the gate electrode fills the gap. The method of claim 6, The dopant of the dopant containing region is the same as the dopant of the doped glass pattern TFT. The method of claim 6, A plurality of openings exposing a surface of a dopant containing region of the semiconductor thin film layer in the doped glass pattern; And And a conductive wiring structure on the exposed surface of the dopant containing region of the semiconductor thin film layer.

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