JP2007335870A - Printed, self-aligned, top gate thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor capable of manufacturing a high-performance printed top gate TFT. <P>SOLUTION: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor have steps: forming a semiconductor thin film layer 2; printing a doped glass pattern 4 thereon, a gap 5 in the doped glass pattern 4 defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor 3 thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

Related applications

  [0001] This application is related to US Provisional Application No. 60 / 813,161 filed June 12, 2006, and US Patent Application No. 11 / 809,737 filed May 31, 2007. That insists on the benefits of

Field of Invention

  [0002] The present invention relates to a printable self-aligned top-gate thin film transistor in which metal-containing inks can be used to print gate metal. In a preferred embodiment, the metal-containing ink includes metal nanoparticles. The present invention advantageously requires little or no high temperature processing or laser activation processing after printing the metal ink.

Background of the Invention

  [0003] In conventional top-gate TFT processes, alignment between the gate and source / drain regions is achieved by first patterning the gate electrode and using it as a mask for dopant implantation and / or activation. It was. This approach poses challenges in gate metal selection. This is because it is necessary to reflect UV laser radiation (eg Al) or adapt to thermal dopant activation at temperatures above 600 ° C. (eg doped polysilicon or Mo, Pd, W etc. Refractory metal).

  [0004] Conventional printing techniques (eg, ink jet) are advantageous for manufacturing electronic devices because of the higher throughput of the printing process compared to photolithography. However, high resolution printing techniques are generally limited in terms of printed line width (about 10 μm or more) due to the relatively large number of defects.

  [0005] For this reason, a structure such as a gate having a narrow line width (for example, less than 10 μm) can be formed by using a printing technique, and / or such as aluminum, a refractory metal, or doped polysilicon. It is desirable to develop a TFT fabrication process that is not limited to any particular gate metal.

Summary of the Invention

  [0006] An object of the present invention is to form a semiconductor thin film layer and to print a doped glass pattern on the semiconductor thin film layer, wherein the glass pattern defines a channel region of the TFT. Forming a gap to be formed; forming a gate electrode having a gate dielectric film and a gate conductor thereon on or above the channel region; and from the doped glass pattern to the semiconductor thin film layer. And a method of forming a thin film transistor (TFT) including a step of diffusing a dopant.

  [0007] Another object of the present invention is a semiconductor thin film layer and a doped glass pattern formed on at least a portion of the semiconductor thin film layer, wherein at least two portions of the doped glass pattern are A glass pattern defining a gap above or above the channel region; and a gate electrode formed above or above the channel region of the semiconductor thin film layer and having a gate dielectric film and a gate conductor thereon Another object of the present invention is to provide a thin film transistor (TFT) including a dopant-containing region formed on both sides of a channel region in a semiconductor thin film layer.

  [0008] Another object of the present invention is a step of forming a semiconductor thin film layer and printing a doped glass pattern on the semiconductor thin film layer, wherein the glass pattern defines a channel region of the TFT. It is an object of the present invention to provide a method for forming a thin film structure, including a step in which a gap is formed, and a step of diffusing a dopant from a doped glass pattern into a semiconductor thin film layer.

  [0009] Another object of the present invention is a semiconductor thin film layer and a doped glass pattern formed on at least a portion of the semiconductor thin film layer, wherein at least two portions of the doped glass pattern are An object of the present invention is to provide a thin film structure comprising a glass pattern defining a gap above or above a channel region, and a dopant-containing region formed on both sides of the channel region in a semiconductor thin film layer.

  [0010] In one aspect of the present invention, the gap between two lines can be smaller than the minimum width of lines formed by inkjet printing. This is because the gap between the lines is mainly determined by the accuracy of the mechanical stage of the printer and the accuracy of the address in addition to the accuracy of the ink placement. Therefore, it is possible to manufacture a high-performance printed top-gate TFT having a channel width of less than 10 μm by first printing a source / drain pattern that defines the position of a gate metal to be deposited later.

  [0011] Accordingly, the present invention provides thin film transistors on various substrates including, but not limited to, glass (eg, quartz) sheets or pieces, plastic and / or metal flakes, sheets or planks, silicon wafers, and the like. And a technique for manufacturing a circuit using the same. In any type of substrate, one or more buffer layers (such as silicon and / or aluminum oxide) may be provided. Applications include, but are not limited to, displays, RF devices, sensors, and the like.

Detailed Description of the Preferred Embodiment

  [0020] In self-aligned top gate TFTs, the development of printed refractory metal or Al gates has significant problems. In the present invention, the layer that defines the source / drain regions is first patterned, then the dopant is activated (eg, by high temperature annealing or laser activation), followed by the deposition of the gate metal precursor ink. Therefore, this problem can be avoided. In a preferred embodiment, a single noble metal, such as silver or gold, can be used to print the gate metal since no subsequent high temperature or laser activation treatment is required. The TFT can also operate at a frequency of GHz, (1) a narrow channel width, (2) a self-aligned source and drain terminal with a slight overlap on the gate, and / or (3 ) Can have advantages in high carrier mobility.

  [0021] Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be clear that it is not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the claims. Furthermore, in the following disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other situations, well-known methods, procedures, elements, and circuits have not been described in detail to avoid obscuring unnecessary to the present invention.

  [0022] For convenience and convenience, the terms “coupled to”, “connected to” and “in communication with” (and variations thereof) are clearly contrary to the text. Unless otherwise indicated, it shall mean direct or indirect coupling, connection, and communication. These terms are generally interchangeable, and whenever one of the terms is used, it also includes the meaning of the other term unless the text clearly indicates otherwise. In this disclosure, the term “deposition” (and variations thereof) is intended to encompass all forms of deposition, including blanket deposition, coating, and printing, unless the text clearly indicates otherwise. Furthermore, for certain materials, the phrase “consisting essentially of” does not intentionally exclude added dopants. Such dopants have certain desired (and potentially completely different) physical and / or electrical properties in the materials to which they are added (or devices or structures formed from such materials). Can give. The term “(poly) silane” includes, for the most part, species composed essentially of (1) silicon and / or germanium and (2) hydrogen and having at least 15 silicon and / or germanium elements. It means a compound or a mixture of compounds. Such species may include one or more rings. The term “(cyclo) silane” consists essentially of (1) silicon and / or germanium and (2) hydrogen and includes one or more tubular rings and at least 15 silicon and / or germanium elements. Means a compound or a mixture of compounds. The term “hetero (cyclo) silane” can be replaced by (1) silicon and / or germanium, (2) hydrogen, and (3) conventional hydrocarbons, silanes, or closely related substituents and Means a compound or mixture of compounds substantially composed of one or more dopant elements, such as B, P, As or Sb, which may contain one or more rings, and one or more rings . The “principal surface” of a structure or mechanism means a surface defined at least in part by the longest axis of the structure or mechanism (for example, when the structure is round and has a radius larger than its thickness). The radial surface is the major surface of the structure, however, if the structure is square, rectangular, or elliptical, the major surface typically has two major axes, typically length and width. The surface defined by the axis of direction.)

[0023] Representative cyclosilanes of formula (AH _z ) _k (A is Si, z is 1 or 2 (preferably 2), k is 3-12 (preferably 4-8)) and their typical preparation The method is disclosed in copending US patent application Ser. No. 10 / 789,317, filed Feb. 27, 2004. Representative hetero (cyclo) silane compounds, doped silane intermediates, their typical methods of making, and techniques for determining and / or controlling the precursor ink and dopant levels of the activated film are each September 24, 2004. , September 24, 2004, and co-pending US patent application Ser. Nos. 10/950373, 10/94903, and 10/95714, filed Oct. 1, 2004. Yes. Such materials include (AH _z ) n (DR ¹ ) m, where n is 2 to 12, m is 1 or 2, and each A according to each value of n is independently Si or Ge, n Z for each value of 1 is independently 1 or 2, D for each value of m is Sb, As, P, or B, R ¹ for each value of m is alkyl, aryl, aralkyl, or AR ² ₃ (wherein R ² is hydrogen, alkyl, aryl, aralkyl or A _y H _{2y + 1} (y is an integer of 1 to 4)) and (A _n H _z ) _m (DR ¹ _3-m ) _q (where n is from 3 to 12, z is from (n-q) to (2n + 2-q), m is an integer from 1 to 3, and each A according to each value of n * m is independently Si or Ge, D is Sb, as, P, or B, q is generally 1 or 2, (3-m) * q each ^{R 1} by the values of Germany Hydrogen, alkyl, aryl, aralkyl, or, ^AR _{2 3} (wherein, ^{R 2} is hydrogen, alkyl, aryl, aralkyl, or _{A p H 2p + 1 (1} ≦ p ≦ 4)) including. Oligo- and polysilane The compounds are disclosed in US Provisional Application Nos. 60 / 850,094 and 60 / 905,403, filed October 6, 2006 and March 5, 2007, respectively, and have the chemical formula H-[(AHR ) _N (c-A _m R ¹ _2m-2 ) _q ] —H (wherein each of A is independently Si or Ge, each of R and R ¹ is independently H, -A _b H _{b + 1} R ² _b (where R ² is H or aryl) or aryl, provided that when q = 0 and A = Si, R is not phenyl, when q = 0, (n + b) When ≧ 10 and n = 0, q ≧ 2 When both n and q are not 0, (n + q) ≧ 2. Each value of m is independently 4 to 6. Oligosilane or polysilane has a molecular weight of 450 g / mol to about 2300 g / mol. (I) having hydrogen, and (ii) substantially consisting of silicon and / or germanium, having a polydispersity index of 2.5 or less, and / or after forming the hydrogenated amorphous semiconductor, the hydrogenated amorphous semiconductor Is annealed and / or irradiated at least partially to crystallize and / or reduce the amount of hydrogen to form a film containing a carbon amount of 0.1 at% or less.

  [0024] In general, but not always, liquid phase semiconductor inks further comprise a solvent, preferably a cycloalkane. When the semiconductor layer 30 is formed using an ink containing an element source of group IVA (a silane-based precursor to Si or doped Si) or an ink substantially composed of this element source, the liquid phase is further added after deposition. Including the step of drying the precursor. Co-pending U.S. Patent Application Nos. 10 / 616,147, 10 / 789,317 and 10 filed on July 8, 2003, February 27, 2004, and February 27, 2004, respectively. No. 789,274.

  [0025] After deposition (and generally after at least some drying), co-pending US patent applications 10 / 789,274 and 10 / 949,013 (February 27, 2004, respectively) And filed September 24, 2004) to form a hydrogenated amorphous (doped) semiconductor (a-Si: H) layer by heat treatment. When the semiconductor layer is derived from or formed from cyclosilane and / or hetero (cyclo) silane, the curing / heating step is a by-product such as unnecessary precursor / ink compounds or volatile carbon-containing species. Either the material is removed or the amount of hydrogen in the a-Si: H layer is reduced (especially effective when laser crystallization is used after semiconductor film formation). If the semiconductor layer is derived from or formed from hetero (cyclo) silane, the curing / heating step may also activate the dopant portion of the hetero (cyclo) silane. However, in many forms, dopant activation is likely to occur during laser crystallization.

  [0026] Alternatively, doped semiconductor layers (doped semiconductor layers) can be deposited by locally printing a liquid phase semiconductor precursor ink directly onto the gate metal and semiconductor layer (September 2004). (See co-pending U.S. patent application Ser. Nos. 10 / 949,013 and 11 / 203,563 filed on Aug. 24 and Aug. 11, 2005, respectively). The approach to forming this latter MOSTFT structure is (i) efficient use of semiconductor precursor materials, and (ii) high cost efficiency by combining semiconductor deposition and patterning in one step. can do.

  [0027] Blanket deposition includes known techniques such as vapor deposition, PVD, sputtering, CVD, and the like. The blanket deposition may also include spin coating an ink containing (cyclo) silane, polysilane, or metal nanoparticles (which may be passivated) and a solvent, and curing the ink. (See US Patent No. 6,878,184 and US Patent Application No. 10 / 749,876 filed December 31, 2003). Examples of metals that can be deposited by such a method include atomic metals (aluminum, titanium, vanadium, chromium, molybdenum, tungsten, iron, nickel, palladium, platinum, copper, zinc, silver, gold, etc.), such atoms. General alloys (aluminum-copper alloy, aluminum-silicon alloy, aluminum-copper-silicon alloy, titanium-tungsten alloy, Mo-W alloy, aluminum-titanium alloy, etc.), and atomic metal nitrides and silicides Conductive metal compounds such as titanium nitride, titanium silicide, tantalum nitride, cobalt silicide, molybdenum silicide, tungsten silicide, and platinum silicide. In other embodiments, the blanket deposition step includes spin coating an ink comprising a metal-containing material, the metal-containing material comprising one or more metal nanoparticles and / or an organometallic precursor of the metal described above. And / or the method may further include a step of curing or heat treating the metal, organometallic precursor, and / or metal nanoparticles prior to the laser patterning step.

[0028] This application discloses several process flows for the design and manufacture of printed self-aligned top gate TFTs. The process flow utilizes doped glass (hereinafter also referred to as “doped”) printed by at least one of three methods.
The printed doped glass provides a dopant source for source / drain doping;
The printed doped glass defines the space for the gate metal, ensures close (eg reasonably acceptable) alignment of the gate to the source / drain regions / terminals, and / or Or
The printed doped glass functions as an interlayer dielectric, and additional interlayer dielectric is formed across the doped glass pattern and the gate electrode (in some embodiments, the interlayer is partially removed when the doped glass pattern is partially removed). Leave part of the doped glass pattern under the dielectric film).

  [0029] The present invention allows for the formation of gate line widths narrower than 10 μm, which is generally achieved by forming transistor gates in the spaces between printed structures. However, in the future, the drop amount is expected to decrease in widely used printing technologies such as inkjet, gravure lithography, offset lithography, etc., so the space between such printed structures may also decrease. As expected, the present invention continues to allow the formation of gate widths that are narrower than the corresponding minimum width of the printed structure.

Hereinafter, the present invention will be described in detail based on exemplary embodiments from various viewpoints.
Self-aligned source / drain gate structure Dopant drive-in through gate dielectric

  [0031] A typical process flow will be described with reference to FIGS. The exemplary process of FIGS. 1 (a)-(e) first forms a gate dielectric before printing a doped glass pattern. Thus, transistor channels (eg, comprising or consisting essentially of amorphous or polycrystalline silicon) are protected from contamination by dopants from subsequently deposited doped glass.

  [0032] As shown in FIG. 1 (a), a physically insulated silicon film is typically formed by printing or coating a molecular or nanoparticle-based silicon ink on a substrate 1, which Is changed to the (poly) silicon thin film 2 (for example, by heat treatment and / or curing treatment). Alternatively, as in the past, a silicon film is deposited (eg, by PECVD, LPCVD, sputtering, etc.), UV laser exposure, heating furnace, or RTA annealing (optionally, crystallization promotion such as Au, Ni, Al, etc.) Crystallize it (by an agent) and then pattern the polycrystal film by low resolution photolithography and / or selective etching. When the silicon film is crystallized by laser annealing, the non-irradiated amorphous part of the deposited silicon film may be removed by selective etching using a known technique. The substrate preferably comprises a silicon wafer, a piece or sheet of glass, or a plastic or metal sheet (both can optionally be rigid or flexible, in the case of metal having a thin oxide layer thereon. May be)

  [0033] The substrate 1 generally includes a conventional mechanical support structure. Suitable electrically inert or insulating substrates include, for example, glass, ceramic, dielectric, and / or plastic plates, disks, and / or sheets. Alternatively, suitable electrically conductive substrates include semiconductor (eg, silicon) and / or metal wafers, disks, sheets, and / or pieces. If the substrate includes a sheet and / or piece of metal, the device includes an inductor and / or capacitor, and the method may further include forming the inductor and / or capacitor from the metal substrate. However, an insulating layer should be provided between any such electrically conductive substrate and any electrically active layer or structure (eg, semiconductor layer 2) thereon. The exception is where electrical contact is made from a device on an insulator to a structure formed on a metal substrate (eg, one or more metal pads of an interposer, inductor, and / or capacitor, eg, US patent application 10 / 885,283 and / or US provisional applications 60 / 592,596 and 60 / 617,617, which were filed on July 6, 2004 and July 2004, respectively. 31st, October 8, 2004). Preferably, the substrate is from the group consisting of silicon wafers, glass plates, ceramic plates or disks, plastic sheets or disks, metal pieces, metal sheets or disks, and laminates or laminated combinations thereof. The electrically conductive member, including selected members, generally comprises an insulating layer (eg, a corresponding oxide layer) thereon.

  [0034] The process of forming the semiconductor thin film layer 2 includes a step of printing a semiconductor precursor ink on the substrate 1 to form a pattern, a step of drying the ink, and a step of curing the ink (generally, crosslinking). In order to oligomerize and / or polymerize silane and / or increase the average molecular weight, increase the viscosity and / or decrease the volatility properties of the compound) and then the semiconductor film pattern Partially or substantially completely crystallized to form a polycrystalline film. The semiconductor thin film 2 generally contains one or more group IV elements, preferably polysilicon or silicon germanium. Typical thickness of the semiconductor layer 2 is from about 30,75 or 100 nm to about 200,500 or 1000 nm, and can be any range between these values. The film thickness can be selected to optimize the electrical characteristics of the transistor.

[0035] In various embodiments, the semiconductor layer 1 comprises or consists essentially of a lightly doped inorganic semiconductor material. Examples of such materials include one or more IVA group elements (such as silicon and / or germanium), so-called “III-V” materials (such as GaAs), II-VI (or chalcogenide) semiconductors, and the like. May include a dopant (B, P, As, Sb, or the like) at a concentration of 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . A typical lightly doped semiconductor film is disclosed, for example, in copending US patent application Ser. No. 10 / 949,013 filed on Sep. 24, 2004. In some embodiments, the semiconductor (transistor channel) layer 2 may be slightly doped (eg, a dopant concentration of 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). When formed from a silicon-based ink, the lightly doped semiconductor layer 2 has a substantially uniform concentration profile (eg, the thickness of the semiconductor layer) over a substantially entire thickness of the semiconductor layer in a uniform amorphous state. (Dopant concentration as a function of thickness). For example, the semiconductor layer 2 may comprise a substantially uniform layer of doped semiconductor material on the substrate, the doped semiconductor comprising (a) at least one of silicon and / or germanium, hydrogenated and amorphous Or at least partially polycrystallized Group IVA element and (b) a dopant. In some embodiments, the Group IVA element in the thin film structure comprises or consists essentially of silicon, and can be a dopant (B, P, As, or Sb, etc., preferably B or P) as described above. You may make it become the density | concentration of.

As shown in FIG. 1 (b), the gate dielectric 3 is formed on the semiconductor (eg, (poly) silicon) film 2 by, for example, thermal oxidation of the semiconductor layer 2. Alternatively, the gate dielectric 3 can alternatively be printed or coated with a suitable dielectric precursor to change it to a dielectric film (eg tetraalkylsiloxane, tetraalkoxysilane), or other one or more Of metal oxides (eg, TiO ₂ , ZrO ₂ , HfO _2, etc.), conventional CVD, PECVD, LPCVD, or sputter deposition of silicon oxide and / or nitride layers. As shown in FIG. 1 (c), a doped glass film 4 is then printed on the gate dielectric 3 (eg, by ink jet, gravure printing). In one embodiment, the gate dielectric film 3 is formed over the entire surface of the semiconductor thin film layer 2 and the doped glass pattern 4 is printed thereon. The layout of the doped glass pattern is substantially equal to the layout intended for the TFT source-drain structure.

  [0037] A gap 5 between regions of the printed doped glass film defines the position of the gate metal. The width of the gap can be in the range of 1-100 μm (preferably 1-10 μm, in some embodiments 1-5 μm). Due to the high temperature annealing process, the dopant from the doped glass migrates through the gate dielectric to the polysilicon film to define the source / drain regions 6. The temperature at which the dopant is diffused from the doped glass through the gate dielectric is preferably less than 1100 ° C., but at least about 700 ° C. or more, and for a sufficient time to dope the source / drain terminals, but the doping A channel region 7 that is not yet left is left.

  [0038] Preferably, the process of printing doped glass uses a tool that can simultaneously deposit N-type doped glass and P-type doped glass in different regions of the circuit. In some embodiments, for example, at least two matching distances between the N-type transistor region and the P-type transistor region of the circuit or a distance corresponding to such a distance (eg, a multiple of such a distance). An inkjet printer having an inkjet head in the same mechanism is used. Two inkjet (IJ) heads are correspondingly connected to each reservoir of N-type and P-type doped glass precursors (eg, inks containing doped spin-on glass precursors or other compositions) and the same printing path. N-type and P-type doped glasses are distributed to different areas of the circuit.

[0039] Examples of doped glass precursors include conventional spin-on-dopant (SOD) compositions and customized versions with increased viscosity (eg, high viscosity solvents similar or compatible with conventional product solvents) A doped molecular silicon ink composition (a cyclic linear or branched silane oligomer having a dopant substituent or oxidizable at a low temperature (eg, 400 ° C. or lower) after deposition). A polymer, for example a cyclo-Si ₅ H ₉ PR ₂ (where R is a low [C ₁ -C ₄ ] alkyl group), phenyl, or a C ₁ -C ₄ -alkyl substituted phenyl) or dopant precursor (eg, , Butylphosphine), oxidized doped molecular silicon ink composition (eg, cyclo, dopant precursor in the composition) Linear or branched silane oligomers or polymers having oxidized versions of (cyclo -Si 5 _O 5 _{H 10)} (e.g., mono-, di-, or tri-butyl phosphine or oxide similar thereto), or the Dopant forming substitutes), and glass forming compositions (eg, so-called phosphines and boron compounds (eg, organic phosphoric acids such as di-n-butylphosphine) and borates (eg, tri-t-butyl boric acid) Sol-gel composition). Suitable dielectrics include phosphorus and oxygen containing compounds and / or polymers (which may further include silicon, carbon, hydrogen, and / or nitrogen), bromine (further silicon, carbon, hydrogen, oxygen, and / or nitrogen). Arsenic and / or antimony (which may further include silicon, carbon, hydrogen, and / or oxygen, respectively). Typical phosphorus-containing dielectrics include the following.
Inorganic oxoline compounds and acids (eg P ₂ O ₃ , P ₂ O ₅ , POCl ₃ etc.)
Phosphosilicates Monomer, dimer and / or oligomer phosphates (eg meta- and / or polyphosphates)
-Phosphonates, phosphine hydrochlorides, and phosphines-Organic oxoline compounds and acids (eg alkyl (aryl) phosphates, phosphonates, phosphine hydrochlorides and their condensation products), and
Alkyl- and / or arylphosphones and / or phosphinic acids.

[0040] Typical boron-containing dielectrics include the following.
Inorganic boron compounds and acids (for example, boric acid, B ₂ O ₃ )
• borosilicates, borazoles, and their polymers • boron halides (eg BBr ₃ )
Borane (eg B ₁₀ H ₁₀ ) and sila and / or azaborane, and
・ Organic boron compounds and acids (eg, alkyl / aryl boronic acids, borates, boroxines, borazoles, borane-added compounds)

[0041] Typical arsenic and / or antimony containing dielectrics include the following.
Oxo- and / or aza-analogues of the above compounds (eg As ₂ O ₃ , Sb ₂ O ₃ )
Arsinosilane (eg, cyclo-As ₅ (SiH ₃ ) ₅ )

  [0042] Thus, each of the source and drain terminals includes (i) a group IVA element, a group III-V compound semiconductor such as GaAs, or a group II-VI semiconductor (or chalcogenide) such as ZnO or ZnS, And (ii) a dopant element may be included. Preferably, the semiconductor comprises a group IV element (eg, Si and / or Ge) and / or a dopant selected from the group consisting of B, P, As, or Sb.

  [0043] In various embodiments, the gate has a width of at least 0.1 microns, 0.5 microns, 1 micron, or 2 microns. In some embodiments, the minimum gate width is about 5 microns. The gate may have a length of about 1 μm to about 1000 μm, or any range between values therein (eg, about 2 μm to about 200 μm, or about 5 μm to about 100 μm, etc.). Also, the gate thickness may be about 50 nm to about 10,000 nm, or any range between values (eg, about 100 nm to about 5000 nm, about 200 to about 2000 nm, etc.). The source and drain terminals can have a thickness of 10 to 1000 nm, or any range between values therein (eg, about 100, 200, or 250 angstroms to about 10,000, 1000, or 500 angstroms). .

  [0044] Referring to FIG. 1 (e), suitable gate metal precursors (eg, metal nanoparticles, or organometallic compounds, doped molecules and / or nanoparticle-based silicon ink, silicide precursor inks, etc.) The gate metal 8 is printed by depositing in a gap defined with at least a printed doped glass pattern and then changing it to a gate metal. The use of doped silicon ink may further require high temperature annealing or laser irradiation to form polycrystalline silicon and / or to activate the dopant to obtain sufficient conductivity. Alternatively, a precursor for the seed layer may be printed in a gap defined by the printed doped glass pattern, and a gate metal may be formed on the seed layer by electroplating or electroless plating. The seed layer may require an activation process prior to the plating process.

  [0045] Techniques for printing the gate metal precursor include, for example, inkjet, gravure printing, offset lithography, and the like. In addition (or alternatively), techniques for patterning the gate metal include coating or printing the gate metal precursor and exposing it locally to laser irradiation to change the dissolution characteristics of the exposed area. (See US patent application Ser. No. 10/749876, filed Dec. 31, 2003). After washing away the unexposed areas, the irradiated gate metal precursor is left to form the gate metal, optionally after additional curing or annealing steps (so-called “negative” patterning and development). Alternatively, “positive” patterning and development may be used, in which case the irradiated areas are washed away. These embodiments (including positive patterning forms) are useful for patterning high resolution metal gates that cannot be achieved directly by direct printing. Generally, the gate conductor includes a metal. However, with respect to the gate, the term “metal” is intended to include doped polysilicon.

  [0046] The metal-containing ink (and, in addition, any other printable ink disclosed herein) may be printed by essentially any conventional printing technique. For example, printing methods include metal-containing ink in a predetermined pattern, inkjet printing (“inkjet”), screen printing, gravure printing, offset printing, flexographic printing, spray coating, slit coating, extrusion coating, meniscus coating. , Microspotting, pen coating, stencil, stamp, syringe, and / or those that print with pump dispense. The ink comprises or substantially consists of a metal precursor material and a solvent. Metal precursors that are generally compatible with printing or (optionally) plating methods include metals such as titanium, copper, silver, chromium, molybdenum, tungsten, cobalt, nickel, gold, palladium, platinum, zinc, iron, or An organometallic composition of these metal alloys (preferably silver or gold (or these metal alloys)) or nanoparticles (for example, nanocrystals) may be included. Such nanoparticles or nanocrystals are conventionally passivated (by one or more surfactants), given one or more surface ligands, or remain unpassivated. Plating, in one example, laser-writes a metal (such as Pd) seed layer with metal nanoparticles or organometallic compounds, and then bulk conductors (Co, Ni, Cu, etc.) or semiconductors (Si and / or Ge etc.) are deposited (for example, by electroless or electroplating). Alternatively, the ink may comprise or consist essentially of a conventional paste comprising a powder of one or more such metals or their alloys contained in a conventional binder.

  [0047] The metal-containing ink can be dried by conventional and / or otherwise known processes. For example, the metal precursor ink can be dried by heating the substrate having the printed metal precursor ink thereon for a temperature and time effective to remove the solvent and / or binder. Suitable temperatures for removing the solvent from the printed ink may range from about 80 ° C. to about 150 ° C., or any range therein (eg, about 100 ° C. to about 120 ° C.). A suitable time to remove the solvent from the ink printed at such temperatures is from about 10 seconds to about 10 minutes, or any range therein (eg, from about 30 seconds to about 5 minutes, or About 1 minute to about 3 minutes, etc.). Such heat treatment can be performed in a selectively inert atmosphere (as described above) on a conventional hot plate or in a heating furnace or oven.

  [0048] The dried metal-containing material from the ink has its electrical and / or physical properties (eg, electrical conductivity, morphology, electromigration, and / or etching resistance, stress, and / or surface strain, etc. ) And a temperature and time sufficient to improve adhesion to the underlying gate electrode may be further annealed. When the metal-containing ink is deposited (printed blanket) entirely or printed, it is typically annealed to form a metal film on which resist can be deposited for later laser patterning. In addition, when a directly patterned metal and / or metal precursor can be obtained by laser writing the metal precursor ink, annealing is generally performed to form a metal layer having excellent conductivity and adhesion. Is called. Such annealing may include annealing already dissolved metal nanoparticles or converting the patterned metal precursor layer to patterned metal. Suitable annealing temperatures are generally from about 100 ° C. to about 500 ° C., and any temperature range may be taken (eg, from about 150 ° C. to about 400 ° C.). Suitable time for annealing ranges from about 1 minute to about 2 hours, preferably from about 10 minutes to about 1 hour, or any time range therein (eg, from about 10 minutes to about 1 hour). 30 minutes). Annealing can be performed in a conventional furnace or oven, optionally in an inert or reduced atmosphere (as described above). Thus, the method further includes annealing the gate so that the electrical, physical and / or adhesion properties of the laser patterned metal gate can be sufficiently improved.

  [0049] In certain embodiments, the gate metal precursor ink can be de-wet from the printed doped glass pattern, which effectively inks the gap defined by the doped glass pattern. Confine. The doped glass pattern is processed prior to the deposition of the gate metal precursor ink to ensure dowetting (eg, plasma irradiation, fluorinated layer or other material layer with similar dowetting properties) Coating etc.). Similarly, the gate metal precursor ink and / or doped glass precursor may include an additive that ensures the wetness of the gate metal precursor from the doped glass pattern. In an alternative embodiment, the gate metal precursor wets the printed doped glass pattern, extends beyond the gap region between each portion of the doped glass pattern, and at least partially covers the doped glass pattern. This embodiment is effective in reducing gate induced drain leakage in the device.

[0050] A typical manufacturing process flow of a thin film transistor according to the present invention may therefore include the following steps.
Deposit lightly doped or undoped silane to form amorphous Si thin films.
(Optional) Dehydrogenate amorphous Si. Gate oxide is deposited, grown, or otherwise formed (eg, by thermal oxidation).
Crystallize lightly doped or undoped amorphous Si (eg by excimer laser treatment or furnace treatment)
Patterning the source and drain regions by printing or otherwise by depositing doped glass; (optional) depositing a metal seed layer; depositing gate metal; (optional) conventional gate metal annealing; Deposition (eg oxides, nitrides)
Oxide formation after printing doped glass

  [0051] FIGS. 2 (a)-(e) advantageously combined polysilicon gate thermal dielectric formation with dopant implantation from doped glass either in situ or in one process step. Is. However, one important aspect of this second exemplary process is to achieve gate oxide growth before significant dopant diffusion begins.

  [0052] The silicon film 12 is typically printed or coated with molecular and / or nanoparticle-based silicon ink in the same process as shown in FIG. 1 (a), which is then applied to the silicon film. Or by depositing a silicon film as in the prior art (for example, PECVD, LPCVD, sputtering, etc.). In any case, the silicon film is generally crystallized by UV laser irradiation, a heating furnace, or RTA annealing (optionally with a crystallization accelerator such as Au, Ni, Al, etc.). Thereafter, as shown in FIG. 2B, a doped glass 14 is printed on the (poly) silicon film (for example, inkjet, gravure, offset litho printing, or the like). The layout of the printed doped glass pattern is generally substantially equal to the layout intended for the source-drain regions. Alternatively, the printed doped glass pattern may correspond to a lightly doped extended region of the TFT (eg, a lightly doped drain), in which case subsequently a relatively heavily doped source / drain A second doped glass pattern may be formed to form the region. The gap between the printed doped glass pattern regions 14 generally defines the location of the gate metal and gate dielectric. As described above, the gap width can be in the range of 1 to 100 μm (preferably 1 to 10 or 1 to 5 μm). After printing, optionally, the doped glass pattern is cured at a sufficiently low temperature to prevent substantial diffusion of dopant from the doped glass into the gap defining the silicon film or gate metal and dielectric. In one embodiment, a plurality of openings are formed in the doped glass pattern from which the surface of the dopant-containing (lightly doped) region of the semiconductor thin film layer is exposed.

[0053] As shown in FIG. 2 (c), the gate dielectric 13 is printed or coated with a suitable dielectric precursor by heating silicon oxidation of the exposed poly-Si layer to turn it into a dielectric film. Or by liquid phase deposition of SiO 2 or other metal oxides (eg TiO ₂ , ZrO ₂ , HfO ₂ etc.) or conventional silicon oxide or nitride deposition methods (eg PECVD, LPCVD, For example, sputtering of an element target in the presence of an oxygen and / or nitrogen source. Preferably, silicon oxidation is used.

[0054] Silicon oxidation in the exposed gate region of the poly-Si film 12 is higher than 600 ° C. under a suitable atmosphere (air, O ₂ , ozone, N ₂ O, wet or dry steam, or combinations thereof). This is accomplished by heating the membrane to temperature. In order to reduce, block or prevent dopant diffusion from the doped glass into the channel region, the maximum temperature is preferably below 1000 ° C., more preferably below 900 ° C.

  [0055] The gate dielectric film 13 of the electronic device may comprise any material for the gate dielectric film described herein. The gate dielectric film 13 can have a width and length slightly smaller than the corresponding dimensions of the gate metal that will be formed later when wet etched, but the two layers were dry etched. Sometimes with substantially equal width and length. The gate dielectric film 13 can have a thickness between 20 angstroms and 400 angstroms, or any range between these values (eg, 30-300 angstroms, 50-200 angstroms, etc.). Alternatively, a thick gate dielectric layer (eg, in the range of 500-2000 Angstroms, in some embodiments on the order of about 1500 Angstroms) can be used, preferably with a higher dielectric constant than silicon dioxide or aluminum oxide. Use the material you have. In some embodiments, the gate dielectric film 13 has a thickness that is greater than the thickness of the heavily doped source and drain terminals, which is mainly due to the electrical connection of the source and drain terminals to the gate metal layer. This is for minimizing the possibility of forming. However, thin gate dielectric films are generally preferred for high speed transistors. Typically, as shown in FIG. 2D, after the gate oxide 13 is formed, the temperature is sufficiently increased (for example, 800 ° C. or more) to diffuse the dopant into the semiconductor film 12 (ie, “drive”). Source / drain region 16 is formed. Further silicon oxidation can occur simultaneously with dopant diffusion at elevated temperatures. The annealing temperature of the doped glass required to cause effective dopant diffusion is preferably higher than that for forming a dielectrically effective gate dielectric but not higher than the maximum process temperature of the substrate. Yes (for example, for metal pieces of relatively low melting point materials such as aluminum, temperatures below 600 ° C. (lasers can be used for dopant diffusion), and for stainless steel pieces at temperatures below 1100 ° C. is there).

[0056] Thereafter, as shown in FIG. 2 (e), a gate metal 18 is formed in substantially the same manner as the gate metal 8 of FIG. 1 (e).
Passivation of doped glass layers

[0057] FIGS. 3 (a)-(c) show the gate dielectric by depositing a barrier and / or passivation layer 25 on the doped glass, or by forming a similar passivation layer 25. FIG. FIG. 5 is a further alternative process flow that reduces potential out-diffusion problems from doped glass when forming. Thus, in a further embodiment, a thin dopant blocking layer 25 is formed on the printed doped glass pattern 24. This layer is intended to prevent the dopant from diffusing into the channel region 27 during dopant activation. The formation of this layer can be accomplished in a variety of ways (eg, substantially undoped glass (acting as a buffer) or silicon nitride film deposition). Films that efficiently getter typical dopants (eg, phosphorus or boron) can also be used. Alternatively, a surface layer that drastically reduces or prevents dopants is formed by exposing the patterned doped glass film to hot water or water vapor, which provides some dopant from the exposed surface to be effective for source / drain doping. But leaves enough dopant in the bulk of the glass (especially near the boundary with the underlying silicon 22). Further, the thin passivation and / or dopant blocking layer 25 is used to prevent effective dopant diffusion by exposing the patterned glass film to conditions that alter its surface properties (eg, ozone, N ₂ O, etc.). ).

[0058] Referring now to FIG. 3 (a), the passivation or barrier layer 25 (which can be a dopant blocking layer or an undoped passivation layer) is much more than the temperature typically used to cause dopant diffusion. It is applied or formed before implanting the dopant at a low temperature. Such a barrier layer may be a gate dielectric 23 and / or an interlayer formed at an elevated temperature from the doped glass 24 where the dopant is adjacent to the adjacent portion (eg, on top of the poly-Si channel 27 (see FIG. 3 (b)) or later. It effectively prevents diffusion to the dielectric). Preferably, the passivation / barrier layer 25 consists essentially of undoped silicon oxide that does not provide a barrier for subsequent gate dielectric formation. The process by which the barrier layer can be formed includes depositing a liquid phase of SiO ₂ from a suitable precursor (eg, a hydrous mixture of silicic acid and boric acid), thereby producing a good quality gate dielectric thin film at a suitable temperature. Can be formed. Alternatively, the passivation layer 25 may be formed by a conventional method in which a dopant is leached from the surface layer of the doped glass layer 24 by a known method.

  [0059] Referring now to FIG. 3 (b), formed by printing or coating a suitable gate dielectric precursor followed by curing / annealing (eg, using liquid deposition or conventional methods). In the case of a gate dielectric, the lateral extent of the layer need not be limited to the gap between the doped glass pattern / structure 24. In fact, it is preferred that at least a portion of the gate dielectric layer 23 completely or at least partially covers the surface of the doped glass pattern (eg, as shown in FIG. 3 (b)). In such cases, the gate dielectric layer itself also provides a barrier / passivation layer 25 to reduce, block, and prevent dopant diffusion out of the doped glass layer 24 and / or source / drain pattern 26. . The formation of the source / drain region 26 is substantially the same as the formation of the source / drain region 16 in FIG.

  [0060] In some cases, diffusing the dopant into the channel region 27 prior to oxidation is preferred to increase the oxidation rate of the doped material. With this increased oxidation rate, a thicker gate oxide 23 can be formed at the end of the channel 27. This thick dielectric can reduce the electric field at the end of the drain 26, thereby reducing gate induced drain leakage (GIDL).

[0061] Referring now to FIG. 3 (c), suitable gate metal precursors (eg, metal nanoparticles or organometallic compounds, doped molecules and / or particle-based silicon ink, silicide precursor ink, etc.) are described above. As shown in FIG. 1 (e), the gate metal 28 is formed by depositing into the gap 25 defined by the doped glass pattern 24 printed as shown in FIG. It is formed.
Source / drain contact and interconnection formation

[0062] The following process flow for the formation of source / drain contacts and interconnections can be applied to any device structure and / or process described above.
Using the gate as a mask for source / drain contact etching

  [0063] FIGS. 4 (a)-(d) are exemplary processes for forming source / drain contacts and interlayer dielectric (ILD) in the underlying TFT structure shown in FIGS. 1-3. Various forms. Referring to FIG. 4 (a), this exemplary process flow illustrates a printed metal gate 140 partially covering the doped glass pattern 130 to expose the contact regions of the source / drain regions 112,114. The doped glass pattern 130 is used as a mask for etching. In this configuration, since there is no organic ILD (interlayer dielectric) on the source / drain regions 112/114, the distance between the source / drain contacts can be made relatively small (thus reducing the resistance). Arbitrary silicide can be formed on the source / drain contacts. Further, gate induced drain leakage can be reduced by spreading the gate metal 140 beyond the region of the gate dielectric 120 and leaving some doped glass 130 below the gate metal 140.

  [0064] Source / drain regions 112/114 and channel 116 are formed on substrate 100, similar to source / drain regions 6 and channel 7 of FIG. The andopto semiconductor layer portion 110 remains after the dopant is injected from the doped glass layer 130. The doped glass layer 130 remains after the formation of the source / drain regions 112/114. The gate dielectric 120 is formed in the same manner as the gate dielectric 3 in FIG. 1C or the gate dielectric 13 in FIG. The oxide layer 122 is formed during oxidation of the exposed surface of the semiconductor layer (ie, region 110) that is not covered by the doped glass layer 130.

  [0065] As shown in FIG. 4 (b), etching of the doped glass pattern 130 and the exposed dielectric layer 122 is accomplished by exposure to one or more etchants. Etchants include, for example, HF-based wet etchants (eg, buffered oxide etch (BOE)), NOE, conventional pad etch, conventional pyridine: HF etchant solution), HF-based or manufactured vapor or gas, plasma etch However, it is not limited to these. The etchant is selected such that the etch rate of the gate dielectric 122 and doped glass 130 is sufficiently greater than the etch rate of the underlying silicon (eg, layers 110, 112, 114) and the metal gate layer 140, thereby Allows the doped glass to be substantially completely removed without substantially removing silicon or gate metal.

  [0066] Referring now to FIG. 4 (c), after etching and optional cleaning steps, interconnect metal 150/152 is printed on each exposed source / drain contact. Although not shown in FIG. 4 (c), the interconnect metal is also printed on the exposed metal, but, as is known, in the “pad” region rather than the plane of the page. In some embodiments, interconnect metal structure 150 or 152 also contacts gate metal 140 (not shown) to form a diode-configured transistor. The printed interconnect metal is used to connect to the transistor in the same layer and / or to provide a via structure in the lower contact area. The interconnect metal resistance is preferably lower than 10 ohms per square.

  [0067] In order to ensure good contact, the structure of FIG. 4 (c) may further include an interface between the interconnect metal 150/152 and the silicon or between the interconnect metal 150/152 and the underlying silicon 112/114. Annealing is performed to form silicide over the entire thickness of the contact region between. Suitable metals for forming silicide include, but are not limited to, Al, Ni, Pd, Pt, Mo, W, Ti, Co, and the like. The interconnect metal can be selected from such silicide-forming metals. Alternatively, interconnect metal precursor inks are known to reduce the contact resistance between interconnect 150/152 and doped silicon source / drain regions 112/114 (eg, doped with Ni organic nanometals). In addition, an additive for forming a silver ink) may be included. However, the additive (eg, Ni) may separate from the silicon interface and / or form a silicide.

[0068] Referring to FIG. 4 (d), after interconnect metal 150/152 is printed (it may be formed by other conventional processes, such as sputtering or photolithography, although printing techniques are preferred. ), Interlayer dielectric 160 is printed to cover the exposed activation regions (eg, gate 140 and source / drain regions 112/114), but appropriate regions (eg, regions covering interconnect 150/152). Leave the via hole 162/164. Interlayer dielectric precursors include glass-forming compositions (eg, conventional spin-on glass compositions such as organic silicates or organosiloxanes), organic dielectrics (eg, polyimide, poly (benzocyclobutene) [BCB], etc.) , Silicon oxide precursors (eg, silane oxides such as Si ₅ H ₅ (OH) ₅ ), or molecular and / or nanoparticle-based silicon compositions (eg, silane inks) that are oxidized after printing. .

  [0069] Similar to other printable inks disclosed herein, for example, inkjet, gravure, offset printing, etc. can be used for the printing process of the interlayer dielectric 160. Alternatively, the process of patterning the interlayer dielectric includes printing or depositing an interlayer dielectric (eg, UV- and / or IR-photosensitive polyimide), which is irradiated (IR, visible, or UV irradiation). To change the solubility characteristics in the irradiated region. By exposing this layer to an appropriate etchant or solvent (for example, a developer), the irradiated region (positive) or non-irradiated region (negative) of the interlayer dielectric forming the via hole can be removed.

  [0070] In an alternative embodiment, a sacrificial material is first formed at a location corresponding to the location where a via hole is to be formed after the interlayer dielectric. The interlayer dielectric precursor, outlined above, is then printed or deposited over a wide area (blanket). After curing the interlayer dielectric precursor, the sacrificial material in the via region corrodes and forms a via hole. Other means of removing the sacrificial material from the via hole are also apparent (eg, selective etching). The circuit is completed by printing the interconnect metal that connects each contact pad of the open via hole (see FIGS. 7B and 7C). The same techniques and / or materials as described above can be utilized.

[0071] One communicating conductor at the source / drain terminal or gate terminal may be connected or continuous with another conductor. For example, in a diode-configured transistor, the conductor can be in electrical communication with the source / drain terminal and the gate. In a capacitor-configured transistor, the conductor can be in electrical communication with both the source / drain terminals. Alternatively, a thin dielectric layer can be formed over the source / drain terminals and a conductor capacitively coupled to the underlying source / drain terminals can be formed thereon.
Using ILD as a mask for source / drain contact etching

  [0072] FIGS. 5 (a)-(e) show structures formed during an alternative process for fabricating the present TFT. Referring to FIG. 5 (a), a channel 210, a first source / drain region 212, a second source / drain region 214, and an undoped semiconductor (eg, Si) region 216 are formed on the substrate 200 as described herein. The Doped glass 230 and conductive gate metal 240 are printed on or over substrate 200 as described herein, and gate dielectric 230 and / or thermal oxide 222/224 are formed as described herein.

  [0073] Similar to the process of FIGS. 4 (a)-(e), the process of FIGS. 5 (a)-(e) is substantially limited to the area between each printed doped glass region 230 (gates). A gate 240 that does not cover the doped glass pattern 230 is used (as in the dielectric 220). However, in this embodiment, during the etching of doped glass pattern 230 to expose the source / drain regions 212/214 or contacts (not shown) thereon, the first interlayer dielectric 245 becomes the gate metal 240 and the gate. Deposited to protect the dielectric 220.

[0074] As shown in FIG. 5 (b), the first interlayer dielectric 245 completely covers the gate metal and dielectric 220 and at least partially but not completely the doped glass pattern 230. Printed. As described above, the precursor ink for the first interlayer dielectric 245 includes a glass forming composition (for example, a spin-on glass composition such as organic silicate or organic siloxane), an organic dielectric (for example, polyimide, BCB). Etc.), silicon oxide precursors (eg, silane oxides such as Si ₅ O ₅ H ₁₀ ), or molecular and / or nanoparticle-based silicon compositions (eg, silane inks) that are oxidized after printing. .

  [0075] The first interlayer dielectric 245 may be printed using, for example, inkjet, gravure, offset printing, or the like. Alternatively, the process of patterning the interlayer dielectric includes printing or depositing an interlayer dielectric (eg, UV- and / or IR-photosensitive polyimide), which is irradiated (IR, visible, or UV irradiation). To change the solubility characteristics in the irradiated region. By exposing this layer to an appropriate etchant or solvent (for example, a developer), the irradiated region (positive) or non-irradiated region (negative) of the interlayer dielectric forming the via hole can be removed.

  [0076] Subsequently, as shown in FIG. 5 (c), the doped glass pattern 230 and the thermally oxidized regions 222, 224 remove the thermally oxidized regions 222, 224 to expose the doped source / drain regions 212/214. Is sufficiently etched. Etching the exposed doped glass pattern 230 and the exposed thermal oxide 222/224 is sufficient to remove the thermal oxidation regions 222, 224, but only for the time to leave the first interlayer dielectric 245 on the gate metal 240. Achieved by exposure to an appropriate etchant. Etchant includes, but is not limited to, for example, HF-based wet etchants (eg, BOE, NOE, pad etch, pyridine: HF, etc.), HF-based or manufactured steam or gas, plasma etching, etc. is not. In many embodiments, some portions of the doped glass pattern 230 also remain on the doped source / drain regions 212/214. The etchant may be doped between the doped glass pattern 230 and the first interlayer dielectric 245, the doped glass pattern 230 and the thermally oxidized region 222/224, or all three materials (ie, the doped glass pattern 230, the first interlayer dielectric 245). , And thermal oxidation regions 222/224). However, etchants generally have etch rates for doped glass 230 and thermally oxidized regions 222/224 that are sufficiently higher than etch rates for underlying semiconductors (eg, doped source / drain regions 212/214 and undoped semiconductor regions 216). So that the thermally oxidized regions 222/224 can be substantially completely removed without substantially removing the underlying semiconductor.

  [0077] Thus, depending on the etch time, the etchant can remove only a relatively narrow portion of the doped glass pattern 230 and expose only small boundaries and regions of the source / drain regions 214/216. In this case, as long as the thickness of the first interlayer dielectric 245 is sufficient to protect the gate metal and dielectric with potentially low etch selectivity compared to the doped glass 230, all of the above materials Suitable for first interlayer dielectric 245.

  [0078] Alternatively, referring to FIG. 6 (a), the etch time is such that substantially most of the doped glass pattern is removed and a small portion of the doped glass is removed from the gate metal 240 and the gate dielectric 220. Selected to remain in the vicinity. In this case, the interlayer dielectric 245 can be selected to have a negligible etch rate compared to the etch rate of the doped glass pattern. For example, an organic insulator (eg, polyimide, BCB, etc.) can be selected in this embodiment. In embodiments having a passivation or dopant blocking layer on a printed doped glass pattern (see FIGS. 3 (a)-(c)), the undoped passivation / dopant blocking layer is doped glass in the presence of a doped glass etchant. The etching rate is selected so as to have a negligible etching rate compared to the etching rate of the pattern.

  [0079] Subsequently, the doped glass pattern 230 (see FIG. 5 (b)) is etched, exposing the source / drain regions 212/214, leaving a “residue” 232 of the doped glass (FIG. 6 (a)). Etching of the doped glass pattern and the exposed thermal oxide region 222/224 is accomplished substantially as described above, however, the etchant has an etch rate of the doped glass and thermal oxide 222/224 of the interlayer dielectric layer 245. (E.g., the etch rate ratio of doped glass and thermal oxide 222/224 to the interlayer dielectric layer 245 is such that the doped glass exposed without substantially removing the interlayer dielectric layer 245) Large enough to be virtually completely removed). Interlayer dielectric when doped glass pattern 230 includes or is derived from doped silicon oxide and source / drain regions 212/214 and undoped semiconductor regions 216 include or substantially consist of silicon Layer 245 can include silicon nitride.

  [0080] Referring now to FIGS. 5 (d) and 6 (b), after etching doped glass 230 and thermal oxide 222/224, the substrate is (optionally) cleaned and interconnect metal 250/252 is removed. , Printed on the exposed source / drain regions 212/214, respectively. As described above, interconnect metal 250/252 also contacts gate metal 240 (not shown). The printed interconnect metal 250/252 is used to connect to transistors in the same layer and / or provide a low resistance contact area for the upper via structure. If the interlevel dielectric 245 is selected to be compatible with a later high temperature process (eg, silicate, silicon nitride, etc.), a metal silicide may be present in one of the interconnect metal 250/252 and source / drain regions 212 and gate metal 240. It is formed at the boundary between the undoped semiconductor 216 on the side and at the boundary between the interconnect metal 250/252 and the undoped semiconductor 216 on the other side of the source / drain regions 214 and the gate metal 240. The interconnect metal resistance is preferably 10 ohms per square.

  [0081] Interconnect metal printing and forming, as many have described, prints appropriate interconnect metal precursors (eg, metal nanoparticles or compounds of organic nanometals, silicide precursor inks, etc.) and applies them to the interconnect metal. Includes a changing process. Alternatively, a precursor for the seed layer is printed on the contact area, converted to a seed layer, and then the interconnect metal (eg, Ag, Au, Cu, Pd) is electroplated or electroless plated on the seed layer. , Pt, etc.) may be formed. Prior to the plating process, the seed layer may be activated.

  [0082] Alternatively, interconnect metal patterning may be performed by coating or printing the interconnect metal precursor and exposing it entirely to laser radiation, changing the solubility characteristics of the printed interconnect metal precursor in the illuminated area. To do. Upon cleaning away the irradiated or non-irradiated areas (preferably non-irradiated areas), after any additional curing or annealing steps, the irradiated interconnect metal precursor remains to form the interconnect metal. This embodiment is advantageous for patterning high resolution metal interconnects that would not be directly achievable with direct printing.

  [0083] To ensure good contact, the structure is further annealed to form a silicide at the interconnect metal and silicon interface, or over the entire thickness of these contact regions. Thus, in such embodiments, the interlayer dielectric that protects the gate metal 240 during the etching of the doped glass pattern 230 is compatible with the siliconization temperature.

[0084] Referring to FIGS. 5 (e) and 6 (c), after printing the interconnect metal, the second interlayer dielectric 260/262/264 is over the gate 245 and the source / drain regions 212/213. Printed but leaves via hole 280 in an area appropriate for contact with the upper level of metallization. The precursors for the interlayer dielectrics 260-264 are the same or similar glass forming composition as the first interlayer dielectric 245 (eg, spin-on glass such as silicate or siloxane, organic dielectric such as polyimide or BCB, Silicon oxide precursors such as silane oxides) or molecules and / or nanoparticle based silicon or aluminum compositions that are oxidized or nitrided after printing.
Use printed ILD as mask for doped glass etching

  [0085] FIGS. 7 (a)-(d) and FIGS. 8 (a)-(d) show printed interlayer dielectrics for etching doped glass 330 to expose source / drain regions 312/314. The pattern 350/352/354 is used as a mask. The process flow of FIGS. 7A to 7D and FIGS. 8A to 8D mainly includes the first interlayer dielectric 350/352/354 (or FIGS. 8A to 8D). As shown, the etching selectivity of the doped glass pattern 330 with respect to the first interlayer dielectric 350 ′ / 352 ′ / 354 ′) is different. In the process of FIGS. 7 (a)-(d), the etching is selective and forms a thin printed interlayer dielectric pattern 350/352/354 compared to the process of FIGS. 8 (a)-(d). can do. In the processes of FIGS. 8 (a)-(d), the etching is non-selective, and compared with the processes of FIGS. 7 (a)-(d), the printed interlayer dielectric pattern 350/352/354 Therefore, it is possible to widen the range of types of materials used.

  [0086] Referring to FIGS. 7A and 8A, the first interlayer dielectric 350/352/354 (or 350 ′ / 352 ′ / 354 ′) includes the gate metal 340 and the substrate 300. The exposed area of the semiconductor island is completely covered, and the end of the semiconductor island (eg, reference numeral 316) and the doped glass pattern 330 are partially (not completely) covered. The precursors of the first interlayer dielectric 350/350 'to 354/354' can be formed of silicon and / or aluminum nitride or oxynitride, and any glass forming composition described herein. The interlayer dielectric can be printed or patterned as described herein.

  [0087] Subsequently, as shown in FIGS. 7 (b) and 8 (b), the exposed doped glass pattern 330 and the thermal oxidation 322/324 are etched to form a first interlayer in the source / drain regions 312/314. Areas not substantially covered with dielectric 350/352/354 (or 350 ′ / 352 ′ / 354 ′) are exposed. The doped glass pattern 330 is etched as described herein. In the process of FIG. 7 (b), in order to substantially completely remove the doped glass pattern 330 without substantially removing the first interlayer dielectric 350/352/354 or the source / drain regions 312/314, The etchant is generally selected so that the etch rate of the doped glass pattern 330 and the thermal oxide layer 322/324 is sufficiently greater than the first interlayer dielectric 350/352/354 and the underlying source / drain regions 312/314. The In the process of FIG. 8 (b), the etch rate of doped glass 330 and thermal oxide layer 322/324 is close to or substantially equal to the etch rate of first interlayer dielectric 350 ′ / 352 ′ / 354 ′, The etchant is selected so as to be relatively higher than the etching rate of the source / drain regions 312/314. Undercut structures 332 (FIG. 7B) and 332 ′ (FIG. 8B) are formed by removing the doped glass pattern by selecting the interlayer dielectric and its thickness. However, if the etch selectivity for the first interlayer dielectric is low (FIG. 8 (b)), the first interlayer dielectric can be made significantly thinner (FIG. 8 (b) the etched first interlayer dielectric 356). / 357/358 compared to the printed / patterned first interlayer dielectric 350 ′ / 352 ′ / 354 ′ of FIG. 8 (a)). In such a case, the thickness of the printed / patterned first interlayer dielectric 350 ′ / 352 ′ / 354 ′ can be larger than the thickness of the doped glass 330 (eg, ≧ 1.5x, ≧ 2x, ≧ 3x, ≧ 5x, ≧ 10x). By this method, the formation of the undercut structure 332 can be avoided as shown in FIG.

  [0088] In either case, the etch time is selected such that most (but not all) of the doped glass layer is removed from above the source / drain regions 312/314. Specifically, the gate metal 340 covered with the first interlayer dielectric 350 or 350 ′ and a small amount of doped glass 332 near the gate dielectric film 320 remain.

  [0089] After completing the etching and optional cleaning steps (not shown), as shown in FIGS. 7 (c) and 8 (c), the interconnect metal 360/362 is exposed to the exposed source / drain regions 312 / Printed on top of 314. Furthermore, the interconnect metal may also contact the gate metal (not shown). The printed interconnect metal can be used to connect transistors in the same layer and / or to provide an underlying contact area for the via structure. If the interlayer dielectric is compatible with later high temperature processing (eg, silicate, silicon nitride, etc.), siliconization of the source / drain contacts can occur after the deposition of the interconnect metal 360/362. The interconnect metal resistance is preferably less than 10 ohms per square. The interconnect metal is printed and formed in the manner described herein.

  [0090] After printing the interconnect metal 360/362, as shown in FIGS. 7 (d) and 8 (d), to cover the exposed activation regions (eg, gate and source / drain regions), However, the second interlayer dielectric 370 is printed to leave the via hole 380 in the appropriate area. The precursor for the interlayer dielectric 370 can include the same glass-forming composition and other materials as described herein for the interlayer dielectric.

  [0091] In one form of the process (not necessarily limited to FIGS. 7 (a) -8 (d)), laser patterning involves the following sub-step: resist material over a blanket deposited material-containing layer. Depositing one of the resist materials with a beam of a laser having a predetermined wavelength or wavelength range that is absorbed (i) a predetermined width and / or (ii) a resist (or with a dye in the resist); A step of selectively irradiating a portion, a step of developing the selectively irradiated region with a developer, and leaving a pattern corresponding to the structure to be formed (in the case of FIGS. 7A to 8D) Are gate metal 340 and / or interconnect 360/362. These steps apply to both positive and negative resists) and do not correspond to the desired or predetermined pattern. Removing those portions of the blanket deposited material (typically by dry or wet etching), and can include the step of removing the residual resist material. Preferably, the light may comprise an ultraviolet (UV) wavelength or wavelength range and / or a visible band of spectrum, but has an infrared band (IR) wavelength. In such a case, the resist (or dye) absorbs and / or reacts to the wavelength or band of light, and the beam light is focused or directed to the desired or predetermined portion of the resist. An exemplary embodiment is disclosed in US patent application Ser. No. 11 / 203,563, filed Aug. 11, 2005.

[0092] Alternatively, a semiconductor layer (eg, having the characteristics of transistor channels 7, 17, 27, 116, 210, or 310, having such a dopant level or concentration) can be used to print doped or undoped semiconductor ink on a substrate. While coating, it can be formed by simultaneously irradiating the ink / substrate. In some embodiments, the process spin coats an ink containing a semiconductor precursor onto a substrate while irradiating the ink with ultraviolet light during the substantial course of the spin coating. This technique (the latter aspect is often referred to as “UV spin coating”) is described in detail in co-pending US patent application Ser. No. 10 / 789,274, filed Feb. 27, 2004. . In another aspect, the printing process (which may include simultaneous or immediate UV irradiation) prints a doped or undoped semiconductor ink, inkjet or gravure, flexographic, screen or offset printing at a location corresponding to the active transistor region in the substrate. (Or other deposition techniques for depositing material on selected areas of the substrate). In either case, the semiconductor layer generally has an amorphous morphology after deposition with substantially simultaneous irradiation and is generally crystallized (eg, heated or otherwise) prior to further processing. (For example, see US patent application Ser. Nos. 10/950373 and 10/949013, each filed on Sep. 24, 2004). In many cases, such crystallization also activates at least some of the dopant.
Conclusion / Summary

[0093] The present invention is a printed self-aligned top-gate thin film transistor having reliable and commercially acceptable electrical properties (eg, on / off speed and ratio, carrier mobility, V _t 's, etc.). Is advantageously provided at a low cost. Semiconductor structures defined by printing and / or radiation (and optionally conductor structures defined by printing and / or radiation) have (1) similar results to structures formed by conventional approaches. (2) conventional graphic art printing technology (for example, inkjet), which is provided at a much lower cost and with a much higher throughput (in the order of hours to days for weeks to months) ) And a high pattern resolution and the same level or high throughput can be provided.

  [0094] The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. These are not exhaustive and are not intended to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible from the above teachings. The above embodiments have been selected and described in order to best explain the principles of the invention and its application, so that one skilled in the art can make use of the invention, the various embodiments, and the intended specific use. Various modifications can be implemented. It is intended that the scope of the invention be defined by the appended claims and their equivalents.

FIGS. 1 (a) -1 (e) show cross-sectional views at various stages of a typical manufacturing process flow of a printed self-aligned top-gate thin film transistor, illustrating a first dopant drive-in technique. FIGS. 2 (a) -2 (e) show cross-sectional views of another exemplary process flow including gate oxide formation after printing doped glass. FIGS. 3 (a) -3 (c) are cross-sections of process flows and (optional) further processes that reduce potential out-diffusion from the doped glass during gate oxide formation. The figure is shown. 4 (a) -4 (d) show cross-sectional views of a process flow for etching a doped glass pattern using a metal gate as a mask to form source / drain contacts and interconnects. FIGS. 5 (a) -5 (e) show cross-sectional views of other process flows for forming source / drain contacts and interconnects. 6 (a) -6 (c) are cross sections of other process flows that use the dielectric material covering the metal gate as a mask when etching the doped glass pattern to form source / drain contacts and interconnects. The figure is shown. FIGS. 7 (a) -7 (d) show printed interlayer dielectrics for etching the doped glass pattern to expose the doped polysilicon source / drain regions for later contact and interconnect formation. FIG. 9 shows a cross-sectional view of another process flow using the body as a mask. 8 (a) -8 (d) are printed to non-selectively etch the doped glass pattern to expose the doped polysilicon source / drain regions for later contact and interconnect formation. FIG. 9 shows a cross-sectional view of still another process flow using the etched interlayer dielectric as a mask.

Explanation of symbols

  2 ... silicon thin film (semiconductor thin film layer), 3 ... gate dielectric, 4 ... doped glass pattern, 5 ... gap, 6 ... drain region, 7 ... channel, 8 ... gate metal, 13 ... gate dielectric, 18 ... gate metal , 25 ... Passivation layer, 110 ... Undoped semiconductor layer part, 112, 114 ... Drain region, 116 ... Channel, 120 ... Gate dielectric, 122 ... Oxide layer, 130 ... Doped glass pattern, 140 ... Gate metal, 150, 152 ... interconnect, 160 ... interlayer dielectric, 210 ... channel, 220 ... gate dielectric, 222,224 ... thermal oxidation region, 230 ... doped glass, 240 ... gate, 245 ... first interlayer dielectric, 250,252 ... interconnect metal, 260 ... second interlayer dielectric, 280 ... via hole, 332 ... undercut Structure.

Claims (10)

A method of forming a thin film transistor (TFT),
(A) forming a semiconductor thin film layer;
(B) printing a doped glass pattern on the semiconductor thin film layer, wherein the glass pattern is formed with a gap defining a channel region of the TFT;
(C) forming a gate electrode having a gate dielectric film and a gate conductor thereon over or above the channel region;
(D) diffusing a dopant from the doped glass pattern into the semiconductor thin film layer;
Including methods.   The method of claim 1, wherein forming the semiconductor thin film layer comprises printing a liquid phase ink containing a semiconductor-containing precursor on a substrate.   The method according to claim 1, wherein the doped glass pattern is printed on or above a region of the semiconductor thin film layer corresponding to a source terminal and a drain terminal of the TFT. Forming the gate dielectric film over the entire surface of the semiconductor thin film layer, and then printing a doped glass pattern on the gate dielectric film;
Forming the gate conductor on the gate dielectric film at least in the gap, and
The method of claim 1, wherein forming the gate conductor comprises printing an ink comprising a gate conductor precursor on the gate dielectric film. Removing at least a portion of the doped glass pattern to a degree sufficient to expose a surface of the semiconductor thin film layer containing diffused dopants;
Forming a conductive interconnect structure on the exposed surface of the semiconductor thin film layer containing the diffused dopant; and
The method of claim 1 further comprising: A thin film transistor (TFT),
(A) a semiconductor thin film layer;
(B) A doped glass pattern formed on at least a portion of the semiconductor thin film layer, wherein at least two portions of the doped glass pattern define a gap above or above the channel region of the TFT. A glass pattern,
(C) a gate electrode formed above or above the channel region of the semiconductor thin film layer and having a gate dielectric film and a gate conductor thereon;
(D) a dopant-containing region formed on both sides of the channel region in the semiconductor thin film layer;
A thin film transistor comprising:   The thin film transistor according to claim 6, wherein the doped glass pattern is formed on or above the source and drain regions of the semiconductor thin film layer.   The thin film transistor according to claim 6, wherein the gate electrode fills the gap.   The thin film transistor according to claim 6, wherein the dopant in the dopant-containing region is the same as the dopant in the doped glass pattern. A plurality of openings formed in the doped glass pattern to expose a surface of the dopant-containing region of the semiconductor thin film layer;
A conductive interconnect structure formed on the exposed surface of the dopant-containing region of the semiconductor thin film layer;
The thin film transistor according to claim 6, further comprising:

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