TWI357157B - Printed, self-aligned, top-gate thin film transist - Google Patents

Description

1357157 IX. Description of the invention: [Technical field to which the invention belongs]

The present invention relates to a printed self-alignment (top-gate thin film transistor (TFT), metal-containing ink can be used to print a gate In one embodiment, the metal-contahhg ink comprises metal nanoparticles. The invention requires micro-temperature, non-semi-temperature or laser activation treatment after printing the metal ink. In the upper gate TFT process, first, by patterning the gate material, it is ensured that the gate is aligned with the source/drain region and is used as a dopant implant and/or activation mask. The problem encountered depends on the choice of gate metal, because the gate metal needs to be able to reflect ultraviolet laser radiation (such as A1) or can be co-fired with the heat (four) in the activation (9) generation temperature (such as #杂_(_) poly-silicon or Mo, Pd or W heat-resistant metal. Due to the high productivity of the printing process relative to photolithography, the traditional printing technology Such as inkjet printing) can be beneficial for the manufacture of electronic equipment J. However, due to ink droplets The volume is not small, so the high-resolution printing technology is limited to the print line width (about 10 μm or more). q Therefore, a TFT capable of forming a small line width (for example, less than 10 μm) is developed. Process (eg, using a gate of a printing technique), and/or process not limited to a particular gate material (eg, aluminum, heat resistant metal, or doped polyfluorene molecules).

The invention is directed to a method for providing a job-specific TFT, comprising the steps of: forming a thin semiconductor film; forming a doped glass pattern with a gate electrode to form a gate electrode in a channel region Above or above, a gate dielectric flkn and a gate dielectric film (gate c〇nduct〇r); and diffusing dopants from the doped glass pattern to Within the semiconductor film layer. Another invention of the invention is to provide a chat comprising: at least a portion of a doped glass pattern of a semiconductor film etched on a layer of a semiconductor film, wherein at least two portions of the glass pattern of the order are located a mesa and a human pole above the channel region of the TFT, on or above the channel region of the semiconductor thin film layer, the gate electrode 2: an electrocardiographic film and a gate conductor on the gate dielectric film; and a half 4 A region containing a dopant on both sides of the channel region in the film layer. Another method of the invention is to provide a method for forming a film junction, comprising forming a semiconductor thin film layer; printing the doped glass pattern on The semiconductor spleen exchange if, the gap in the doped glass flip case defines the channel region of the TFT; and the glass __ of the dopant is dispersed into the semi-conductive film layer. Another scope of the present invention is to provide a film The structure comprises: a semiconductor thin, at least a portion of the doped glass pattern on the semiconductor thin film layer, and at least two portions of the potted glass are located above the channel region of the TFT. And the swivel_layer The spacing between the (4) containing dopants on both sides of the channel region is mainly determined by the accuracy of the ink position plus the small force and accuracy of the printing device, so the interval between the two lines may be The minimum line width of the ρ column. Therefore, first print the source/dot pattern, with the position of the metal, enabling the fabrication of a high-efficiency printed upper gate TFT having a channel width smaller than 〇μιη. The process of fabricating TFTs and their circuits on various ridges, substrates containing, quartz gas) sheets or strips, plastic and/or metal foils, sheets or plates, and various substrates such as day and day may all contain one or more Buffer layer (such as Shi Xi and 1357157 / or oxide). Related applications include, but are not limited to, 'display i or sensing section. ',,, deep tail 褒 [implementation] self-aligned upper _ TFT (four) The printing heat-resistant metal or the butterfly is a significant challenge. The present invention overcomes the above challenges by the following process: the first-layer pattern 'defines the source-level polar region, then the activated doping, the lower annealing or the active side ), followed by __ metal precursor ink ^ Tian ^ - Preferably, the specific implementation of the shot, by the supplement (four) to be non-high temperature or cerebral processing steps 'silver or gold-containing pure precious metal ink can be used to print the gate of the gold Ming TFT can be in billion (GHz) _ rate Operating under the benchmark, with = (1) narrow channel width, (2) self-aligned but a small overlap with idler j and bungee terminations, and/or (3) high carrier mobility. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 'The singularity of the present invention is more clearly described, and the present invention is not made in the preferred embodiments disclosed above. Conversely, it is intended to cover various changes and presentations. The scope of the patent application is intended to be within the scope of the invention. Therefore, i ^ is the broadest solution according to the above description, so that all changes and equivalent arrangements can be referred to, for the sake of 'In this paper, the secret, (eGupled tG),,, connected with) refers to the direct printing, except for the 1 deposition 'contains all the deposition, coating and the elements or structures required or formed from the material. The material is quite different in terms of physical properties and/or electrical properties. "(poly)silane" refers to a compound or mixture of compounds, substantially comprising and/or hydrazine and (2) hydrogen, and (poly) oxalate significantly comprises at least 15 = 矽 and / or the form of 锗 atoms. Such forms may contain one or more cydic nng. '' (cydc^siiane) refers to a compound or a mixture of compounds, substantially containing (1) hydrazine and/or hydrazine and (2) hydrogen, and (ring) smoldering may contain One or more rings and less than 15 singular and/or samarium atoms.,, (hetero-burning, (iv) en) (eydQ>iriane) refers to the compound or compound mixture, which essentially contains (1) 矽 and / Or ruthenium, (2) hydrogen, and (3) - or a plurality of dopant atoms such as B, P, As or sb may be replaced by conventional hydrocarbons, decane or a suitable substituent, and iso (ring) The decane may contain one or more rings. Also, the structure or object, the major surface, is at least partially defined by the surface of the structure or the largest axis of the object (for example, if the structure is spherical and its half ^ is greater than Its thickness, the radial surface is the main surface of the structure; however, the structure is square

Where the shape or ellipse, the main surface of the structure is defined by two largest axes, generally length and width. X is a cyclodecane compound represented by the chemical formula (AHz) k, wherein a is hydrazine, z is 2 or 2 (preferably 2), and k is 3 to 12 (preferably 4 to 8), and the detailed preparation method can be The U.S. Patent Application No. 1/789,317 (filed on: February 27, 2004) is incorporated by reference. An isocyclic (cyclone) compound, a doped decane intermediate, a process for the preparation thereof, and a technique for determining and/or controlling the doping and active doping of the active film are filed in the U.S. Patent Application Serial No. No. 1〇/950,373 (application date: January 24, 2004), 1〇/949,013 (application date: September 24, 2004) and 1〇/956,714 (application number: 1 month of 2004) Japanese) is described in detail, and includes a compound represented by a chemical formula (Aiy/DR1; ^ and (AnHz)m(DRl3-m)q, wherein (AH^DR, η is 2 to 12, and m is 1 or 2) , A is Si or Ge, z is j or 2 ' D is Sb, As, P or B, R1 is alkyl, aromatic smoke, biyl}, scented CaralkyD or AR%, wherein R2 is hydrogen, Affiliation, aryl, aromatic alkyl or AyH2y+1 (where y is an integer from 1 to 4), η is an integer from 3 to 12, and z is (11_(}^ to (2n+ m is 1) An integer of 3, A is Si or Ge, D can be Sb, As, P or β, 8 1357157 i mi can be ίί, =: aromatic filament, aromatic filament or also, ,, t is 虱, alkane a base, a fragrant hydroxy group, an aromatic alkyl group or an A through g). The combination of decane and polydecane The system is disclosed in the United States 60 / win 4 (application 曰: October 6th, 2006) and heart ^ T11 lVrB) > * t ”; ΐ is hydrogen, (its * R2 is hydrogen sister base) or burnt base, but 疋If q=〇 and A is Shi Xi, then R is not phenyl (four), such as q=〇, then (n+be〇; if n=0, bite 2; if _ and _, then (n+q) 22 ' m value is 4 to 6, oligodecane or polydecane substantially contains 1 hydrogen, (Η) Shi Xi and/or

The ruthenium has a molecular weight of 45 Å to 23 gram per mole, which has a polydispersion index less than h. After curing to form a non-crystalline hydrogenated semiconductor, followed by annealing and/or sufficient irradiation to at least partially crystallization and/or reduce the hydrogen content of the amorphous hydrogenated semiconductor (hydr〇gen'c〇) Ntent) °, forming a film having a carbon content of not more than 0.1 at%. Generally, the liquid semiconductor ink further contains a solvent, but it is not always necessary, and the solvent is preferably cycloalkane. Therefore, when an ink substantially containing an IVA group element (e.g., a decane-based precursor such as ruthenium or doped ruthenium) is used, the step of forming the semiconductor layer 30 may further include the step of drying the liquid precursor ink after deposition. See US Patent Application No. 1〇/616,147 (Application Date: July 8, 2003), 1〇/789,317 (Application Date: February 27, 2004 and 10/789, 274 (Application: 2004) February 27, 2007. After deposition (and at least a little drying), the semiconductor layer is cured by heating, see U.S. Patent Application Serial No. 1/789,274 (filed on: February 27, 2004) and 10/. 949,013 (application 曰: September 24, 2014), and form a non-crystalline hydrogenated (doped) australis (a-Si:H) layer. When the semiconductor layer consists of (cyclo)stone and/or The 'curing/heating step formed by the ring can remove unwanted precursors/ink by-products, such as volatile carbonaceous materials, or reduce the hydrogen content of the a-Si:H layer (if the semiconductor layer is formed, It is particularly advantageous to use a laser to crystallize. When the semiconductor layer is formed of a hetero (cyclo) decane, the curing/heating step can activate a part of the dopant in the hetero (cyclo) alkane, ^ 9 1357157 疋 many In a specific embodiment, the activation of the dopant is more likely to occur during the laser crystallization process. The doped semiconductor layer may be made of a liquid semiconductor precursor ink. The area is printed and deposited on the gate metal and semiconductor layers (for example, US Patent Application No. 1/949,013 (Application Date: September 24, 2004) and 11/203,563 (Application 曰Γ 2005 8) The 11th)). The latter approach is close to the formation of metal oxide semiconductor (MOS) TFT structures, which can save costs because of the efficient use of G) semiconductor precursor materials and (ii) semiconductor deposition and mapping integration. A single printing step. Comprehensive deposition including vapor deposition, physical vapor deposition, sputtering, or chemical vapor deposition is known to those skilled in the art. Full deposition includes spin-on inks and cured inks (see U.S. Patent No. 6,878 , 184 and application No. 1 / 749, 876, application 12, December 31, 2003). The ink contains (cyclo) decane, polydecane or metal nanoparticles (not easily chemically reacted) and solvent. The sequential deposition, including s basic metals, traditional alloys and conductive metal compounds. Basic metals such as aluminum, titanium, vanadium, chromium, molybdemmi , tungsten (tungSten), iron (ir〇n), nickel (nickd), palladium, platinum, copper, zinC, silver or gold traditional alloys such as Ming copper alloy, Mingmeng alloy, Ming copper hair alloy, Qinhe alloy, molybdenum tungsten alloy or aluminum titanium alloy. The conductive compound is a base metal nitride and a telluride such as titanium nitride, titanium telluride, a nitride button, cobalt telluride, molybdenum telluride, or platinum telluride. In other embodiments, the step of overall deposition comprises spin coating ink, the ink comprising a metal containing material comprising metal nanoparticles and/or one or more organic precursors of the disclosed metal. Prior to laser mapping, the method of the present invention further comprises a solid annealing step of a metal, an organic precursor and/or a metal nanoparticle. The present invention describes the design and flow of fabricating a printed self-aligned upper gate TFT. The process comprises at least one of the following three methods of printing doped glass.丄二>3/丄:)/丄二>3/丄:)/ Source (1) Printed genre Tixian County fine secret (4) Pushing matter to the role of dielectric glass as inner dielectric; deep-layer Internal sound: glass ==, the step of the glass pattern is left in the inner layer = the _ space of the printable structure is the gate of the transistor, and the volume of the _ pole line is used for printing in the future. In technology, such as inkjet and gravure materials, the space between the structures is also expected to shrink. According to the invention, the line width of the combined door is continuously smaller than the minimum width of the red printed structure. The present invention will be described in detail in various aspects in the following specific embodiments. Straight-line quasi-source/; and inter-pole episodes are injected into the entire gate dielectric by a change of impurities. Figure - Α to map - Ε process before printing the glass pattern, first form the age of tf. The transistor channel (e.g., L s amorphous germanium or polycrystalline germanium on the real g) is protected from contamination by the subsequent deposition of doped glass. Referring to Figure 1A, the physically isolated ruthenium film can be formed by printing or coating molecular and/or nanoparticle-based ruthenium ink on the substrate, followed by conversion of the decane thin, for example by annealing. And / or curing). That is, the Shichen J film can be conventionally deposited (for example, by plasma assisted chemical vapor deposition (pECVD), low pressure chemical vapor deposition (fPCVD), and sputtering, etc.) and by ultraviolet laser irradiation, hot furnace or Rapid Thermal Annealing (RTA) is used for crystallization (selective in a crystalline catalyst such as 11 1357157) followed by low-resolution photolithography to produce a polycrystalline film. The cut film is laser-annealed and the second film can be removed by selective etching to remove the deposited non-crystalline, non-crystalline, non-crystalline portions. The preferred substrate comprises a dream wafer, a glass strip, a glass sheet, a plastic sheet or a metal sheet (which may alternatively be rigid or elastic, for example having a thin oxide layer thereon). The substrate 1 comprises a conventional mechanical support structure, and the non-conductive substrate may comprise disks, dishes and/or sheets each made of glass, ceramic, dielectric or plastic. Also, the ίί/ΐ substrate contains crystals, discs, sheets, and/or crucibles made of a semiconductor such as Shi Xi and/or metal. In the case where the substrate comprises a metal sheet and/or a box, the device is guided or capacitive, and the method may further comprise forming a conductor and/or electricity 4 from the metal substrate. However, any conductive contact should be on any of its electrically active U-structured financial-insulating layers (such as semiconductor layer 2), except that the conductive contacts are placed on the insulator to form the metal substrate. Structure (intermediate 1, conductor and / or capacitor - or a plurality of metal pads for electronic article surveillance (Electronic Article Surveillance, (Radio Frequency mentifcation, rfid) tag", for example, US Patent Application No. i 〇 / 885, 283 (application =. July 6th, 20th, 4th) and/or US Provisional Patent Application No. 6〇/592,596 (application for the date of July 31st, July 31st) and 6〇/617 617 (application date: 2〇〇) 4 years

If H ^ t please ° the substrate consists of a group of conductive elements consisting of Shi Xi wafer, glass fiber, Tao Jing substrate or Ganzi 'sheet or dish, metal box, metal sheet _ and sandwich board. There is typically an insulating layer thereon (eg, a corresponding oxide layer). The step of forming the semiconductor ship layer 2 may include printing the semiconductor precursor ink into a pattern 'then drying the ink' followed by curing the ink (by adding, drying, or annealing the remaining ink) to cross-bond ( _3祉) and / and / or increase the average molecular weight, increase the adhesion of the compound and / or: salty) "then the semiconductor film partially or substantially completely crusted to form a polycrystalline ship. The semiconductor thin film layer 2 generally comprises - or a plurality of w-type elements 12 1357157 Ϊ is a polystone or a stone slip. The thickness of a typical semiconductor layer 2 can be formed to be about 30, 75 500 or 1000 nm, or any value within the range. k select the appropriate film thickness to optimize the transistor electrical properties. The semi-semiconductor layer 1 substantially comprises a slightly doped inorganic + conductor material, such as - or a plurality of family elements (Shi Xi and / or 锗) $ mv" family of materials (such as: Ga spider 乂 and "n_VI," family (or The bismuth ore further contains a dopant having a density of from ~1〇16 to 〜5χ1〇18 atoms/cm3 = (for example, B, p, AS or Sb). The lightly doped semiconductor film is disclosed in US Application No. 10/ 949,013 (application 曰: September 24, 2004). In a practical example, the semiconductor (transistor channel) layer 2 is slightly doped (for example, doping is about 1〇16 to 5xl018). The ink-based ink is formed, and the lightly doped semi-J body layer 2 has a concentration table (for example, a doping concentration and a semiconductor thickness) in an amorphous state, and the thickness of the entire semiconductor layer uniformly exhibits an amorphous state. The semiconductor layer 2 comprises a layer of uniformly doped semiconductor material on the substrate, the doped semiconductor material comprising (a) a hydrogenated, amorphous or at least partially polycrystalline group of eight elements, the Group IVA element comprising at least one germanium. And 锗, and as a dopant. In a specific embodiment, the IVA group in the film structure The concentration of germanium, dopant (possibly B, p, As or sb, but preferably B or P) is substantially as described above. Referring to Figure 1B, the gate dielectric 3 can be semiconductor The thermal oxidation of layer 2 is either formed by printing or coating a suitable dielectric precursor on a semiconductor (e.g., d) film 2, which is then converted to a dielectric film (e.g., a four-burning base) Liquid phase deposition of a oxidized stone precursor such as tetraalkylsii〇Xane or tetraalkoxysilane or converted to other metal oxides (eg, Ti〇2, Zr〇2, Hf〇) 2) deposition, or chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), low pressure chemical oxygen deposition (LPCVD) or cesium clock converted to yttrium oxide and/or nitride layer. The doped glass film 4 as shown in Fig. C is then printed on (e.g., ink jet, gravure) gate dielectric 3. In one embodiment, the gate dielectric film 3 is formed on the entire surface of the semiconductor thin film layer 2, and then the doped glass pattern 4 is printed thereon. The 13 1357157 layout design of the doped glass pattern is substantially the same as the source of the TFT _ the expected layout of the immersed structure. The gap 5 between the ten-printable doped glass film regions defines the width of the gate gap to be 1 to 100 μm ( Preferably it is biOpm, in some implementations 1~5μιη). After the high temperature annealing, the dopants from the doped glass enter the polyresist film, and the source/recording region 5 is defined. The temperature at which the ^ 2 glass is diffused to the gate dielectric is preferably 11 〇〇ΐ to 7 〇〇 ° C for a sufficient period of time to dope the source/drain terminal; I. The process of doping the doped glass preferably by 'doping the doped glass utilizes a tool that can simultaneously dope the glass to different areas of the circuit. For example, there are two inkjet heads on the same frame, and the inkjet heads are separated by the distance between the N-type and p-type transistors in the circuit (or the distance). Several times). The two ink jet heads are correspondingly connected to the accumulation of the glass precursors of the N-type and p (·Γνοΐτ), and the same-printing action is performed to remove the Ν-type and p-type doped glasses in different regions of the circuit. . , the precursor of the miscellaneous glass contains a spin-on dopant (Spin_on_Dopant, S- (4) has an increased viscosity of the formulation (''Adjustment') by replacing or diluting the formulation with a high viscosity ft or compatible solvent Solvent), η side after deposition. c) t-oxidized age-incorporated ink formulation (for example, a cyclic, linear or dendritic low molecular or macromolecule with a push-substituent, Ξ =ycrH9PR2 ' The towel ruler is a low-carbon silk coffee core or a silk-based base, the doped precursor of the formula towel W, such as a Urt-butyl-phosphine, and an oxidized doped molecular stone An oxidized version of an ink formulation (eg, a cyclic, linear ribbed hetero-molecule or a high-length CyCl〇_Sl5〇5iilD with a dopant precursor) (eg, mono-, di- or tri-tert-butyl phosphate) , an oxide] or a heterocyclic substituent, and an organic phosphate containing a conformational compound such as di_n_butylph〇sphate, and a sulphate group (eg, tributyl) a glass forming formulation of a borate (tri t_ 14 Ί 357157 butylborate) (such as a so-called solute gel) S〇l gel))). Suitable dielectrics also include phosphorus, oxygen (further containing cerium, carbon, hydrogen and/or nitrogen), boron (further containing cerium, carbon, hydrogen, oxygen and/or nitrogen), cerium and/or cerium (further included) Compounds and/or polymers of hydrazine, carbon, hydrogen and/or oxygen.

The phosphorus-containing dielectric material comprises: a mercaptophosphoric acid (0X0 phosphorus) compound and an acid (for example, ρ2〇3, ρ2〇5, POCl3, etc.); a phosphosilicate; a mono(monomeric), a double (dimeric) And/or oligo (〇lig〇meric) phosphate (eg, metaphosphate and/or polyphosphate); phosphate (phosphonate), phosphinate, and phosphine;

An organic oxo phosphorus compound and an acid (eg, an alkyl (aryl) phosphate, a phosphate, a hypophosphite, and a concentrated product thereof), and an alkyl phosphate and/or Alkyl hypophosphorous acid and/or aromatic hydroxyphosphoric acid and/or an aromatic hydroxy acid. The carbonaceous dielectric comprises: an inorganic carbon compound and an inorganic carbonic acid (for example, boric acid or B2〇3); a borosilicate, a borazole, and a polymer thereof; a boron halogenide (eg, BBr3); 15 1357157 Borane (eg, B1()H1()), sila-) and/or azaborane; and organoboron compounds and organoborates (eg, Alkyl/aromatic hydroxycarbonic acid, borate, boroxine, boron hexacycline, and addition of shed composites). The arsenic-containing and/or antimony-containing dielectrics include: the above-mentioned oxo (0X0-) and aza- (aza-) analogous compounds, such as As203 and Sb203; and the arsinosilane, such as cyclo-As5 (SiH3). ) 5. Therefore, the source and drain terminals comprise (i) Group IVA elements, Group III-V compound semiconductors such as GaAs, or Group VI-VI (sulfide) semiconductors such as ZnS or ZnS, and (ii) dopant elements. . The semiconductor includes one of a group IV element (such as Si and/or Ge) and a group of B, P, As, and Sb. In various embodiments, the gate width is at least 0.1 microns, 0.5 microns, 1 micron or 2 microns. In one embodiment, the minimum gate width is about 5 microns. The length of the gate is from Ιμιη to ΙΟΟΟμπι or a value in any range thereof (e.g., from 2μιη to 200μηι or from 5μιη to ΙΟΟμιη). The gate thickness is from 50 nm to 1 〇〇〇〇 nm or a value in any range (e.g., 100 nm to 5000 nm or from 200 nm to 2000 nm). The thickness of the source and drain terminals is from 1 〇 nm to 1 〇〇〇 nm or a value in any range (eg, l〇nm, 20nm or 250nm to 1〇〇〇nm, 1〇〇nm or 50nm) ° Referring to Figure IE, by depositing a suitable gate metal precursor (for example, a metal ink or an organometallic compound ink, doped molecules and/or nanoparticle-based ruthenium ink, ruthenium precursor ink), The gate metal 8 to 'lessly printed on the & brush-doped glass case A is connected to the gate metal'. The doped Shishi ink secret ship-(d) is subjected to high-temperature annealing light radiation to form poly 16 1357157 wafers and/or to activate dopants to achieve sufficient conductivity. That is, the precursor of the seed layer can be printed in the gap of the printed doped glass pattern, and the gate metal (eg, Ag, Au, Cu, pd, pt) can be electroplated or Electroless plating (eiectrolessl god 1 in the seed layer before the coating process, the activation step / upper seed layer is required

The printing of the gate metal precursor includes inkjet, gravure, lithographic development. Further, the step of patterning the gate metal includes coating or printing the gate gold flooder 'locally exposing it to laser illumination, resulting in an exposed area change characteristic (see U.S. Patent Application No. 1/ 749,876, application 曰: December 31, 2). After the unexposed areas are washed away, additional gated metal precursors are cured or annealed to form gate metal. That is, it can be used;; the positive "system II and the shaft method" is exposed to the area under irradiation. These examples of Ϊιίϊΐΐ® have high-resolution i-metal gates that cannot be directly (four), the advantages of the case In general, the gate conductor contains a metal. _, the pair of poles and the '''metal'' contains doped poly-stone molecules. Print the other printable inks revealed hereby by tradition

. For example, the printing means that the metal-containing ink is subjected to a predetermined ink jet printing, screen printing, gravure printing, lithography, elastic relief exography, spray coating, and slit coating. Touch (micr〇sp〇tting), flat plate coating _c 'M0P (StamPing) ' dispense mode to print out. The ink essentially contains the metal precursor servant. Suitable for printing or coating metal precursors containing organic gold compounds or metals (such as Chin, copper, silver, lanthanum, turn, crane, austen, nickel, ^, nano, iron 'or metal alloy' is preferred Nanoparticles of silver or gold)

If there is a 17 1357157 (four) surfactant, and provide one or more surfaces (such as the ® atom), or remain non-listening. The coating consists of a laser using a metal (such as U Ιΐ ί particles or an organometallic compound to write a seed layer of a human metal, followed by a coating) ϋ (for example, by electroless plating or electroplating) a conductor (such as c〇, N g conductor (such as Sl and the domain Ge) are on the seed layer after the laser writing, that is, the ink contains a paste containing one or more metal or alloy powders in the adhesive. The ink of the sentence can be general and/or others. Knowing the process to dry it. For example, the k-genus precursor ink can be removed by heating the ink containing the printed metal precursor ink at a temperature for a sufficient period of time to remove the solvent and/or the adhesive, S 3 : Dry. The appropriate temperature for removing the solvent from the printable ink is 8 〇ΐ to 1 C, or a value in any range (for example, 1 〇〇. 〇 to 12 〇. 〇. Remove the solvent from the J brush ink Appropriate length of time is 1

= This heating method can be carried out on a common hot plate and baked in a selective atmosphere. Temperature 1埂仃, the dry metal-containing material separated from the county is sighed enough to slam the temperature 盥 gate = annealing to improve electrical and / or physical properties (for example, guide and fine

i ϋ ϋ ΐΐ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ ϊϊ () minutes to 3 = heat in the mantle or in a healthy environment. Handle Ϊ ί = patterned surface ship 耿 耿 善 、 概 概 概 概 18 18 18 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The pattern removes moisture from the gate metal precursor ink, effectively confining it to the gap defined by the doped glass pattern. Before the gate metal precursor ink is deposited, a doped glass pattern is used (eg, by electricity) Slurry irradiation 'fluorinated iayer or other materials with decontamination properties" ensures dehumidification. Gate metal precursor inks and / or glass precursors are included to ensure doped glass pattern removal gate An additive to a metal precursor ink. In another embodiment, the gate metal precursor wets the doped glass pattern such that it extends beyond the gap region between the doped glass pattern portions and at least a portion is covered Doped glass pattern. This embodiment is beneficial for reducing the loading The gate within the gate induces a drain leakage condition. According to the present invention, the process for fabricating a TFT comprises the steps of: depositing a lightly doped or undoped germane to form an amorphous germanium film; (selectively) dehydrogenating amorphous germanium Diluting difficult oxides, growing gate oxides, or other means (such as hot oxygen)

Crystallization of lightly doped or undoped amorphous states, treated by excimer laser or furnace); knife area ^ by refilling _ glass reprint or other drawing green (10) pole and immersion treatment 匕And/or diffusing dopants into the source and the polar regions (eg, 'thermally (selectively) depositing a metal seed layer; depositing a gate metal; gate metal (optionally) annealing; 19 1357157 deposition protection Passivation (for example, oxide or nitride), after the gasification of the shape of the plant, Figure 2: 8 shows the rU ' by the injection of dopants from the doped glass. Another process that is beneficial to the formation of inter-electrode dielectrics.

The cold film 12 is closed on the substrate 11 by printing or printing, and the ink is used as the main ink (4), and then converted into a thin film, and the germanium is deposited by a conventional method (for example, , PECVD, LPCVD, sputtering, crystallization by laser beam riding, neon or RTA annealing (selection, in the case of crystallization catalysts such as ii, Nl, AI). Therefore, refer to Figure 2B 'Doped glass 14 is printed (eg, inkjet printed, recessed or lithographically printed) on a (poly) stone film. The layout of the printable doped pattern is substantially the same as the intended layout of the source-drain region. That is, the miscellaneous glass is assigned to the slightly doped region of the TFT (10) (for example, a slightly doped dipole). The second doped glass pattern can then be printed to form a relatively heavy-for-source-polar region. The gap metal between the miscellaneous glass region 14 and the position of the dielectric material. The gap width can be (4) (relative to ΐμηι to ΙΟμιη or _ to 5_. After printing, the doped glass pattern is selectively at a sufficiently low temperature Curing to ensure that no dopants then diffuse from the doped glass to the tantalum film Diffusion to define the gap between the gate metal and the gate dielectric. In one example, the doped glass pattern creates a plurality of holes that expose half of the surface containing dopants (eg, 'slightly doped.' 2C, the formation of the gate dielectric 13 can be printed or coated with a suitable dielectric precursor and converted film, or SiO 2 or other oxidation by the thermal oxidation of the exposed polylithic layer. Liquid deposition of metal, or oxidized stone and cerium deposition, such as PECVD, LPCVD, in the presence of Wei Qiang gas source 20 1357157 element (four) age small Wei transfer (10) _. To the trench i region U, suppress or avoid the doping material containing any of the above gate dielectric films and then the shape is smaller than the value in any range of SHI (for example, 30A to ί μα ί

2〇〇l:t^^ * 500A , J or 疋 in another embodiment, about 1500A) yttrium oxide or oxidized material is a preferred choice. Yu Yishi::: The thickness of the J-based electrical film 13 is greater than that of the heavily doped secret and the terminal of the drain, and the electrical connection between the source and the drain terminal and the gate metal layer is low. In the case of high-speed transistors, thin gate dielectric films are preferred. After the gate oxide 13 is formed, referring to Figure 2D, the temperature is raised (e.g., greater than 800 C) sufficient to diffuse the dopant (driving) to the semiconductor to form the source/_ domain 16. Further, the high temperature rise occurs simultaneously with the driving of the dopant. Need to induce significant dopant diffusion ^ The preferred annealing temperature of the doped glass is higher than the temperature of the effective gate dielectric used to form the dielectric, but not higher than the maximum processing temperature of the substrate (eg : Metal foils such as aluminum, which are relatively low-melting materials, do not exceed 600 ° C, and perhaps in the case of lasers, the non-mine steel book 'will not exceed 11 ° C temperature production. Thereafter, referring to Fig. 2E', the formation of the gate metal 18 is substantially the same as the formation of the gate metal 8 of Fig. 1. ~ 21 1357157 A thin glass layer of yfh ΐΊ ΐΊ 图 图 图 图 图 图 图 图 图 图 图 图 图 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积 沉积Another possibility of over-diffusion - the process. Therefore, in the - phosphorus or carbon) (four) film. Correction, lack of dopants, il production iS doped glass film in hot water or water vapor in the stone eve 22 ίίΓ ΐ some tweaks 'but in the glass block (especially enough dopants are beneficial to the source / No extreme age 蒦曰... 蒦曰 and/or dopant-depleted layer 25 can be formed by exposing the film to a twisted wire that can change surface properties, such as avoiding ==== diffusion to the channel, such as exposure to ozone or Ν2〇 For details, please refer to Figure 3. The protective layer or barrier layer 25 (which can be a lion layer) can be formed before the dopant is implanted, which is much lower than that used for guiding: The barrier layer effectively prevents the dopant from turning from the glass, at two temperatures: to the junction structure (for example, the polysilicon 27 dielectric and/or the inner dielectric). The oxidized stone eve 'undoped oxidized oxide eve is not an obstacle to the subsequent gate dielectric formation process. The process of fabricating the barrier layer includes the deposition of Si 〇 2 (矽 矽 — 卿 以及 以及 acid) Boric acid: water crimes and substances) 'produces high-quality gate dielectric films at appropriate temperatures. 11 继 24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The lateral extension need not be limited to the gap of the doped glass pattern/structure 24 =. In fact, in some examples, it is desirable that at least a portion of the idler 23 can completely or partially cover the surface of the doped glass pattern (Fig. 3b =). In some examples, the gate dielectric layer itself also provides a barrier/protective layer that inhibits or prevents the doped glass layer 24 or the source/drain pattern from being too diffuse dopant. The source/secret region 26 is formed substantially the same as FIG. 1 D = pole/drain region 26. In some cases, due to the enhanced oxidation rate of the doping material,

= The pre-dopant is excessively diffused into the human channel region 27. Enhanced oxidation produces a thicker gate oxide illusion at the edge of the channel 27. The thicker dielectric is reduced by =26 the electric field at the edge is reduced, causing the leakage of her (10) Dram Leakage, GIDL). Referring to Figure 3, T' metal 28 is printed to deposit a suitable gate metal ruthenium drive (e.g., metal nanoparticles or organometallic compounds, dopant molecules, and/or

The rice particles are mainly _ink, and the precursor of the material is in the gap 25 defined by the _-doped glass pattern 24 and is converted into the gate metal electrode 8. U

The process flow of the source/drain contacts and their interconnected 源_source/drain contacts and their interconnected structures can be used with any of the known device structures and/or processes. Responsible for the source/bungee contact engraving point mask. Figure 4A to Figure 4D show the formation of the source/drain contact and the inner dielectric (ILD) in Figure 1 to Figure The basic TFT structure shown in Figure 3. Referring to FIG. 4A, the process uses a printed metal gate 14〇 partially covering the doped glass pattern 130 as a mask for etching the doped glass pattern 13〇 to expose the source-level regions 112 and m. Contact area. This embodiment ensures the source / 汲 23 1357157

The distance between the pole contacts is quite close (and thus the resistance), causing the optical germanium on the source/drain contacts to exist above the source/drain regions 112/114 as if there were no organic inner dielectric. Further, extending the gate metal 140 beyond the area of the gate dielectric 120 and leaving a portion of the doped glass 130 under the gate metal 140 reduces the gate leakage caused by the gate.

The source/drain regions 112/114 and the channel 116 are formed on the substrate 1A similar to the source/nomogram region 6 and the channel 7 of FIG. After implanting the dopant from the doped glass 130, a portion 110 of the undoped semiconductor layer remains. The doped glass layer 13 is left behind after the source/tin region 112/114 is formed. The formation of the gate dielectric 12 类似于 is similar to the formation of the gate dielectric 3 of FIG. 1 or the gate dielectric 13 of FIG. The oxide layer 122 is formed during the oxidation of the exposed surface of the semiconductor layer (e.g., 110) not covered by the doped glass layer GO.

As shown in FIG. 4B, the doped glass pattern 13 and the exposed dielectric layer 122 are finished by a wet etchant that is exposed to - or suitably fine, but not limited to HF (eg, buffered oxide etch). Agent (6 〇 cut), n〇e, bottom etchant, pyridineOT side agent solution), hf-based or certified vapor corpus, or electric secret. The side agent is selected such that the side rates of the gate dielectric f 122 and the push glass 130 can be greater than the side layers of the underlying layer (eg, layers ιι, ι 2, and gold pole layer 140, such that the glass can be substantially Need any wire miscellaneous metal. 1 Nana glass and light clean steps (not shown), please refer to ° ° ϊί Not as good as 1# technology, interconnect metal can also be printed on the storm 'but , the bottom of the bottom, the area, not the plane. The metal 150 or 152 of the fragrant scent / violent road also pulls the blood with the gate metal 140, interconnecting metal objects (not shown). The lower contact area of the pipe structure. The interconnection is all 0^ day, electricity day and/or provide a good choice. The resistance of the genus is less than 10 ohms and the square is more than 24 1357157 to ensure good contact, ® 4 The structure of c can be further annealed to form the interface of the interconnected metal calendar 52 of the ίί/ΐίϊ, or the entire film thickness of the contact surface of the intertwined t and the underlying 112/114. The formed metal includes, but is not limited to, A1, Ni, pd, smog, JV Ti Co. Interconnecting metals can be formed from these ceramides Dependent selection, that is, an interconnect metal precursor ink containing a halide (eg, a silver ink doped with Ni organometallic) and an additive has been observed to reduce interconnection 150/152 and doped yttrium source Contact resistance between /dipole region 112/114. However, additives such as nickel may separate from the tantalum interface and/or form a telluride.

After printing the interconnect metal 150/152 (can be formed by multiple processes, such as sputtering and photolithography, but printing is preferred), and see Figure 4D, the inner dielectric 160 is printed to cover any exposed active areas (eg, 140 and source/drain regions 112/114), but leaving a suitable area of hole 2/164 (eg, interconnection point 150/) Above 152). The inner dielectric precursor comprises a glass forming formulation (eg, a spin-on glass formulation, an organic bismuth or an organic tellurite), an organic dielectric (eg, polyimide, poly(cyclobutene) a cerium oxide precursor (for example, oxidized decane, si5H5 (〇H) 5) or a ruthenium-based oxidized molecule and/or a nanoparticle-based ruthenium formulation (for example, ruthenium ink). The step of the quality 160 comprises inkjet, gravure, lithographic printing, similar to the printing process of other disclosed printable inks. That is, the step of patterning the two layers of dielectric comprises printing or depositing the inner layer. An electrical property (eg, a polythene film that is sensitive to ultraviolet light and/or infrared light) and exposure to illumination (eg, infrared, visible, or ultraviolet light) to alter the solubility characteristics of the illuminated area. Exposure of the layer The exposed (positive) or unexposed (negative) area of the inner dielectric forming the hole in the pipe may be removed by a suitable etchant or solvent. In another embodiment, the discardable material is first printed on the corresponding inner layer. Pipe hole position formed after electric quality In the position, the inner dielectric precursor is then printed or fully deposited. After curing the inner dielectric precursor, the tube 25 discards the material to decompose and form a tube hole. One of the pole/secret terminals or the gate terminal #conductor can also be reduced to the other conductor. For example, in the case of a cell with a two-pole vacuum tube, the conductor can be electrically connected to a source/汲a terminal and a gate. In the body of the capacitor, the conductor can be electrically connected to the source/drain terminal. That is, a thin dielectric layer can be formed over the source/drain terminal, capacitively A conductor connected to the lower source/nopole terminal can be formed on the thin dielectric layer. The inner layer of the source/pile contact etching device

In C ’ and Figure VIII are called 八<:). The structure formed in another process for fabricating a TFT can be shown using the above-mentioned technique 5A to 5E. Referring to FIG. 5A, a channel 210, a first source/drain region 212, a second source/nomogram region 214, and an undoped semiconductor (e.g., germanium) region 216 are formed on the substrate 200. Doped glass 230 and conductive gate metal 240 are printed on or over substrate 200. Gate dielectric 22 and thermal oxide 222/224 are formed as shown. Similar to the process of Figures 4A through 4E, the process of Figures 5A through 5E uses a gate 240' that is limited to the area between the printed doped glass regions 230 (gate dielectric 210). The doped glass pattern 230 is covered. However, in this embodiment, during the etching of the doped glass pattern 230, the first inner dielectric 245 is deposited to protect the gate metal 240 and the gate dielectric 22, exposing the source/drain Region 212/214 or a contact point thereon (not shown). In Figure 5B, the first inner dielectric 245 is printed such that the gate metal, gate dielectric 220, and at least some but all of the doped glass pattern 230 are completely covered. The precursor ink of the first inner dielectric 245 comprises a glass forming formulation (Example 26 1357157, for example, spin-on glass formulation, citrate or organic oxime), organic dielectric, yttrium film, BCB), oxidized Shi Xi precursor (for example, oxidized Shi Xizhuo,

SiAHhj), or a zebra formula based on molecules that are oxidized after printing and/or nai particles. The printing of the first inner layer dielectric 245 includes a method of inkjet, gravure printing, lithography, and the like. That is, the method of patterning the inner dielectric includes printing or depositing an inner dielectric (polyimide film sensitive to ultraviolet light and/or infrared light), and exposure to ultraviolet light, visible light, infrared light. Under irradiation) to change the solubility characteristics of the riding area. Exposing the layer to a suitable etchant or solvent will remove the exposed (positive) or unexposed (negative) area within the inner dielectric forming the via hole. As shown in Figure 5C, the doped glass pattern 230 and the thermally oxidized regions 222 and 224 are engraved sufficient to remove the thermal oxidized regions 222 and, as well as the exposed, dopant// and polar regions 212/214. The completion of the silver-exposed exposed doped glass pattern 230 and the violent thermal oxide 222/224 may be removed by exposing the appropriate surname to the thermal oxide regions 222 and 224 for a sufficient period of time, but retaining the An inner dielectric 245 is left over the gate metal, and the etchant includes, but is not limited to, Hp is the main wet money agent (eg, 'buffered oxide etchant (B〇E), N〇E, 僖=, Py-, proof-based or HP-made 丄2 gas = plasma etch. In many embodiments, portions of the doped glass pattern 23 也 also remain above the doped source/drain regions 212/214. The etchant may be selectively interposed between the doped glass pattern 230 and the first inner layer dielectric 245, between the doped glass pattern 230 and the thermal oxide regions 222/224, or the three & That is, between the doped glass pattern 230, the first inner layer dielectric 245 and the oxide 222/224), the etchant is selected such that the doping ratio of the doped glass 23 and the tantalum oxide 222/224 is sufficiently larger than Etching rates of the underlying semiconductors (eg, source i/drain regions 212/214 and undoped semiconductor regions 216), resulting in The thermal oxide 222/224 is substantially completely removed without removing the underlying semiconductor. Depending on the time of engraving, the engraving agent removes only the relatively thin 27 1357157 of the doped glass pattern 230 by exposing only the source/nomogram region 214 / 216 small border or area. In 1 , all the above mentioned materials are suitable for the first inner layer of dielectric quality doped glass 23G with low side of the closed-cell miscellaneous words 'Please refer to the six A 'Select the appropriate time for the secret time so that most of the 'excluding the doped glass 232 small (or other insulator) metal 240 and the gate dielectric 220. In this case, select the appropriate 45 so that its side rate Compared with the side ratio of the doped glass pattern, in this case, an organic or insulator can be selected (for example, poly-aluminum _ with a protective layer and/or a ruin-poor layer for the printable doped glassy substance) Poverty is the column tt t Α to Figure 3 C) 'The etch rate of the undoped protective layer/doped doped glass pattern is negligible. Eight eclipse to sheep, and 』i, =m230 (Figure 5 b) is used to expose the source / and pole & field 212 / 214 and leave the replacement glass, the residue" said (Figure 6A No. _Doped glass illuminates and exposes the thermal oxide region 222/22 as described herein' but selects the appropriate side agent such that the 222/224 is sufficiently large compared to the inner dielectric bleed g = in addition to J (tetra) doped glass * will remove any _ dielectric layer 2 cut. In the embodiment of the doped glass pattern 230 or in the doped oxidized stone eve, and the polar region 212 / 214 and The undoped semiconductor region 216 of the solid dielectric layer 245 comprises nitrite. X贞上贞S石夕, please refer to Figure 5D and Figure 6B' in the doped glass 23〇 and the tantalum oxide 222/224 After etching, the substrate can be (selectively) cleaned and the interconnect metal 25 〇 = printed on the exposed source/nomogram regions 212/214. The interconnect 250/252 is also in contact with the gate metal 24〇 (not shown). Printed Interconnect = 250/252 is used to connect the transistors in the same layer, and / or provide low power __^ 28 1357157 to the above pipe structure. If the appropriate connection 5 = 252 and the source / no-pole region 212 are selected, the conductor 21 is located on the side of the interpole metal 24 匕 and the source/drain region 214 is located on the other side. The resistance of the interconnect metal is preferably less than 丨〇 ohms/square. The printing of the inter-metal interconnects is performed by interconnecting metal precursors (such as 'metal nanoparticles or organometallic compounds, telluride precursor inks') and converted to interconnect metals. That is, the precursor of the seed layer can be printed on the contact surface and converted into a seed layer, followed by interconnecting the metal (eg, Ag, Au, a, ke, can be electro-mine or electrolessly plated. The seed is light The step of activating the pattern. The step of patterning the interconnect metal comprises coating the embossed interconnect metal precursor and regional exposure to laser illumination such that the printed interconnect metal precursor of the exposed area changes the smear. After listening to the area of the Ruth (4) (a preferred practice is to wash away the unexposed area) 'Selectively after the additional curing or annealing step, the irradiated interconnect metal precursor will remain to form the interconnect metal. Examples provide the advantages of high-resolution metal interconnect drawings that cannot be achieved directly by the printing method. • To ensure good contact, the structure is further annealed to form the interface between the interconnect metal and the germanium or the contact surface. The entire film thickness. In this embodiment, the inner dielectric of the gate metal 24 is protected during the etching process of the doped glass pattern 230. Suitable for the germanium temperature. See Figure 5E and Figure 6c, print After the metal is attached, the second inner dielectric 260/262/264 is printed over the gate 245 and the source/drain regions 212/214, but leaving the tube holes 280 within the appropriate area for use with the higher metal Degree of contact. The precursor of the inner dielectric 260-264 comprises a glass forming formulation similar to or similar to the first inner dielectric 245 (such as a spin-on glass formulation of Shi Xizhuo, Shi Xi Oxygen, such as a polythene film). BCB's organic dielectric, such as yttrium oxide yttrium oxide precursor 29 =. ' or after printing or oxidizing or nitriding molecules and / or nanoparticle-based Shi Xi or Ming

The exposed source/drain regions 312 and 314 are exposed, and the process flow of the etched inner dielectric pattern 350/352/354^ is used as the mask for the etched glass 330. . The main difference between the flow of Fig. 7A to Fig. 7D and Fig. 8a to D is that the etching selectivity of the doped glass pattern 33〇 is the same as that of the first inner dielectric 350/352/354 (as shown in Fig. 8 to Fig. 8D). As shown, the first inner dielectric is 350V352V354,) related. In the flow of Figures 7A through 7D, the etch is selective, so that a thinner printable inner dielectric pattern 350/352/354 can be produced relative to the flow of Figures 8A through 8D. In the process of FIGS. 8A to 8D, the etching process is non-selective, and thus the material for printing the inner dielectric patterns 350, /352, /354, relative to the process of FIGS. 7A to 7D. There is a wide range of variability. Referring to Figure 7A and Figure 8A, the first inner dielectric 350/352/354 (or 350V352Y354D can be printed so that it can completely cover the gate metal 34〇 and other exposed areas on the substrate 300' And a portion (but not completely) covering the doped glass pattern 330' as a semiconductor island edge (such as 316). The precursor of the first inner layer dielectric 350/350' to 354/354' comprises any glass forming formulation, like nitrogen An oxynitride of the compound or the stellite and/or aluminum. The inner dielectric system can be printed or used for mapping. Next, as shown in Figure 7B and Figure 8B, the exposed doped glass pattern 330 and heat The oxides 322/324 are engraved to expose the source/drain regions 312/314 that are not covered by the first inner dielectric 350/352/354 (or 350V 352V354'). Doped glass pattern 330 is unique. In the process of Figure VIIB, an appropriate etchant is selected such that the etch rate of doped glass 330 and thermal oxide 322/324 is sufficiently greater than the first inner dielectric 350/352/354 and the underlying source/ Etching rate of the drain region 312/314 so that the doped glass 330 can be completely removed without removing any first 30 1357157 Electrode 350/352/354 or source/> and polar region 312/314. In the process of Figure VIIIB, the appropriate etchant is selected such that the doping ratio of doped glass 330 and thermal oxide 322/324 is close to or the same The etching rate of the first internal dielectric 3507352, /354, but relatively higher than the etching rate of the lower source/drain region 312/314. According to the choice of the inner dielectric and its thickness, the doped glass pattern Removal may result in relief structure S 332 (Fig. 7B) or 332' (Fig. 8B). However, when the doped glass has a low etch selectivity with respect to the first inner dielectric (as shown in Fig. 8B), There is a relatively thin first inner dielectric (the first inner dielectric 356/357/358 etched in Figure VIIIB and the printable/patterned first inner dielectric 350, 352 in Figure VIIIA) , /354i compared). In this example, the thickness of the printable/patterned first inner dielectric 35〇|/3521/354 is greater than the thickness of the doped glass ^30 (eg '>l_5x, Gong, attack, 汾, y〇x). As shown in Fig. 8B, 'this arrangement avoids the formation of the relief structure 332. In one case, select the appropriate etching time so that most (but not all) doping The glass layer can be removed from above the source/drain 312/314. In particular, leaving the first inner, dielectric 350 or 350 and adjacent to the gate metal 34 and the gate dielectric film 320 A small portion of the doped glass 332. After the etching and light cleaning (not shown) steps, the interconnect metal 36〇/362 can be printed on the exposed source/drain 312/314, as shown in Figure VII and Figure Eight c shows. Further, the interconnect metal can be in contact with a gate metal (not shown). Printable interconnects can be used to connect transistors in the same layer and/or provide a lower contact surface for the pipe structure. If the inner dielectric is suitable for subsequent high temperature processing (e.g., niobate, nitrogen), after deposition of interconnect metal 360/362, the source/no-pole contacts may be deuterated. The resistance of the interconnect metal is preferably less than 丨〇 ohms/square. The steps of printing and forming the interconnect metal are as described herein. After printing the interconnect metal 360/362, as shown in FIG. 7D and FIG. 8, the second inner dielectric 370 can be printed to cover the exposed active area (eg, gate and source/drain regions). ), but leaving the pipe hole 38 within the appropriate area. The precursor of the inner dielectric 370 comprises the same glass forming formulation as well as other inner dielectric materials. _ iϊ疋 in the example (not limited to Figure 7A _ person d), the laser system contains the lion _ _ (four) good boots ♦ metal layer) u ten ground can be used as a corrosion inhibitor (anti-corrosion dyeing, Or (9) a wavelength or band of laser radiation remaining one or two __ to correspond to the structure being formed "this step metal 34G and / or interconnect metal genus 62;;

Patterned all sewn pepper poplar (four) miscellaneous (borrowing paste. Light with infrared light band is the better choice, although or for 7b skin length or wave sense, light silk line riding in need or scheduled anti-money The embodiment is disclosed in U.S. Patent Application No. 11/2: August 11, 2005. ^^月髀髀;: time-emitting substrate, semiconductor layer (for example, having an electro-crystal fii λ 27, 116 , 21G or characteristics, such as dopant level or concentration) can be formed by printing or coating doped or undoped semiconductor ink on the substrate

on. In an embodiment, during the process of the spin coating step, the process of illuminating the ink with ultraviolet light includes the technique of spin coating the ink containing the semiconductor precursor on the base g (also for the surface light spin coating). JV spin-coating)) is described in the application US Patent Application No. 1/789,274 'Application Date: February 27, 2004. In another embodiment, the printing (including simultaneous or immediate ultraviolet light irradiation) comprises inkjet or gravure printing, elastic relief printing, screen printing or lithographic doping or non-doping of the semiconductor ink on the substrate corresponding to the activated transistor The location of the area (or other deposition technique used to deposit material on selected areas of the substrate). In one example, the semiconductor layer, after deposition simultaneously, generally has an amorphous state, which is typically crystallized prior to further processing (eg, by heating or laser irradiation; see U.S. Patent Application Serial Nos. 10/950,373, and 10) /949,013, the application date is September 24, 2004 曰). In many instances, crystallization will activate at least a portion of the dopant. 32 1357157 In contrast to the prior art, the present invention provides a low cost method for making acceptable electrical (e.g., on/of E speeds and ratios of gates tft.) printable and/or Irradiation of ΐ; results from the structure of more traditional methods; lower cost and higher productivity, and (2) higher resolution; j in traditional cartographic printing (eg inkjet) 'have similar or higher yields The details of the specific embodiment of the 'parent invention' are intended to describe this more clearly.

Hi invented the patent scope of (4). Because of the fascination of the 2 2 2 ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ ΐϊ

33 1357157 - Shiyi: 2, 12, 22 Clearance: 5, 15 ' Protective layer: 25 Closed dielectric: 3, 13, 23, 120, 122, 210, 220 Closed metal: 8, 18, 28, 140, 240, 340 ·· Glass: 4, 14, 24, 130, 230, 232, 330, 332 Source/Bungee: 6, 16, 26, 112, 114, 212, 214, 312, 314 Area: 7, 17, 27, 116, 216, 310 Vertical metal: 150, 152, 250, 252, 360, 362 Inner dielectric: 160, 245, 260, 262, 264, 350, 352, 354, 350 ', 352, 354', 356, 357, 358, 370 pipe holes: 162, 164, 280, 380 thermal oxides: 222, 224, 322, 324 35

Claims (1)

May 31, 100, the scope of the patent application: 1. The method of forming a thin film transistor (TFT), comprising the steps of: forming a semiconductor thin film layer; and placing a doped glass pattern ( a doped glass pattern printed on or above the semiconductor thin film layer, a gap in the doped glass pattern exposing a portion of the semiconductor thin film layer and defining a channel region of the thin film transistor Forming a gate electrode on or above the channel region. The gate electrode includes a gate dielectric film and a gate on the gate dielectric film a gate conductor; and diffusing a dopant from the doped glass pattern into the semiconductor film layer. 2. The method of claim 1, wherein the step of forming the semiconductor thin film layer comprises printing a liquid phase ink on a substrate, the liquid ink comprising a semiconductor precursor The method of claim 1, wherein the doped glass pattern is printed on a source and a drain corresponding to the thin film transistor (semiconductor) Drain) The upper or upper area of the semiconductor film layer of the terminal. The method of claim 4, comprising forming the gate conductor on the gate dielectric film and forming at least in the gap. 5. The method of claim 5, wherein the step of forming the gate conductor comprises printing ink containing one of the gate conductor precursors on the film of the gate dielectric thin film on May 31, 100. Tender and tender, the glass pattern of the object 7. The film is formed in the gap 1 method, the step of the towel and the maternity and the second, the glass flip and the heating of the semiconductor film layer to a temperature without Forming a source in the semiconductor film layer / 8 · ^ patent application scope! The method of claim, wherein printing the doped glass comprises printing an ink comprising a doped glass precursor on the water layer; or above the water layer comprising the doped glass precursor The ink is converted to a doped glass. The method described in the paragraph A, the step of removing the portion of the dopant is sufficiently exposed to expose the surface of the + conductor film layer containing the dopant of the chick. 10. The method of claim 1 wherein the step of removing the portion of the doped glass pattern leaves the remainder of the contaminated glass. The method of claim 10, further comprising forming a conductive interconnect structure on the exposed surface of the semiconductor film layer comprising the diffused dopant. / 12. The method of claim 1G, wherein the step of forming an interlayer dielectric film over the doped glass and above the gate electrode. 13. The method of claim 1, further comprising: a passivation layer or a poorly-missed layer (dopant_such as coffee (4) formed ^ 37 100 May 31 曰 U side case / exposed surface. A thin film transistor comprising: a semiconductor thin film layer; at least a portion of the surface pattern is located on the semiconductor thin film layer, and at least two portions of the ::: doped glass pattern define a gap therebetween a thin portion of the semiconductor film layer over the channel region and between the doped glass patterns; located on the channel region and the gate electrode The invention comprises: a germanium film and a gate conductor on the gate dielectric film; a plurality of regions of the conductor containing the dopant, located on both sides of the channel region; An electrical interconnect structure on the exposed surface of the semiconductor-containing film layer containing the impurity-containing region. The thin film transistor according to the above-mentioned patent, which includes a plurality of semi-conductive 16+-genus I, layers Located in a transistor body pattern on a substrate. The fine crystal according to item 15, wherein the modified glass 17 pattern is located on or above the source and drain regions of the semiconductor thin film layer. The thin film transistor, wherein the gate electrode fills the gap. The thin film transistor according to Item 15, wherein the gate dielectric film comprises a thermal oxide of the semiconductor thin film layer (thermal The thin film transistor according to claim 15, wherein the doped glass has a pattern on the semiconductor thin film, and the gate (4) film is located only in the gap. For example, the application of the micro-crystal according to the above-mentioned (4), wherein the gate conductor 38 comprises a metal according to the semiconductor film of the fifth aspect, wherein the film contains the 22 ^ impurity and the The dopant of the doped glass is the same. The thin film transistor according to item 15 of the tm, further comprising a plurality of openings (QPeninS) in the case of two or two persons, exposing the semiconductor film layer The surface of the region where the dopant is oblique. 23^!1 Patent scope No. 15 The thin film transistor further includes an inner electrode, located on the doping axis __ and the gate electrode. The film transistor according to claim 15 of the patent scope, further comprising - is θ or doped a negative layer, located on the exposed surface of the doped glass pattern 0 25. ^Application of a full-time 'film thin film transistor of the '15 item, wherein - between the independent region on the impurity and the channel region Each of the interfaces is substantially aligned with one of the edges of the alternating glass pattern. 26. A method of forming a thin film transistor (TFT) comprising the steps of: forming a semiconductor thin film layer; dielectrically blocking a gate Forming a thin film on the entire surface of the semiconductor thin film layer; printing a doped glazed pattern on or above the gate dielectric film such that the doped glass pattern has a gap, Exposing a portion of the semiconductor thin film layer and defining a channel region of the thin film transistor; forming a gate electrode on or above the channel region in the gap, the gate electrode package a gate dielectric film and a gate conductor on the gate dielectric film (gate will be thin conductor on May 31, 2010, May 31, 100; and - dopant (dopant) from the glass layer. u Wang 4 thousand and other thin germanium transistors, including: a semiconductor film layer; = at least part of the glass pattern, in which the axis is interposed (four) earned in the gap, two;; a portion of the surface of the ruthenium layer; a plurality of regions containing dopants located in the region of the channel ϋϋΐί ^