JP2000000348A - Pachinko machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pachinko machine capable of generating an attractive effect sound corresponding to a reach section. SOLUTION: A pachinko machine is provided with a special picture design display device 30, a sub-control unit 74 for performing control regarding an effect sound output and a voice synthesizing circuit 86 connected to the sub- control unit 74, the voice synthesizing circuit 86 is provided with a sound frequency setting register, a noise frequency setting register, a volume setting register and a setting register having an area for setting the starting/stopping of sound reproducing and an area for setting repeating and, if a reach is set in the special picture design display device 30, the sub-control unit 74 sends a control command corresponding to a reach division to the voice synthesizing circuit 86 and thereby a different effect sound is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pachinko machine that issues a sound effect for reporting information according to a game state.

[0002]

2. Description of the Related Art Generally, a pachinko machine is configured to generate a sound from a speaker according to a game state. For example, Japanese Patent Application Laid-Open No. 8-266709 discloses a game control unit for controlling a game state of a gaming machine, a voice synthesis circuit controlled by the game control unit, and for synthesizing voice according to the game state of the game machine, Data for ADPCM (Ad
up Differential Pulse
And an audio ROM storing code modulation data, wherein the audio synthesizing circuit is configured to synthesize a stereo sound based on audio data read from the audio ROM in accordance with a game state. Have been.

[0003] The above-mentioned voice synthesizing circuit uses a DSP (Digital).
tal Signal Processor), a memory interface, a microcomputer interface, a reset circuit, a clock oscillator, an ADPCM decoder, three electronic volumes, a panpot circuit, two mixing circuits, and two digital / analog converters. And

The game control unit gives a command to the DSP in accordance with the game state. The DSP gives an address of data to be read from the voice ROM to the memory interface in response to the command. Is read. The DSP further controls the three electronic volumes and the panpot circuit according to the command given from the game control unit to adjust the volume of the synthesized voice of each channel, thereby using the stereo voice to surround the player. Voice control is performed such that the sound source circulates or the sound source moves forward, backward, left, and right for the player.

[0005] However, the above-mentioned audio control means of the pachinko machine is configured by separately arranging and composing each element constituting an audio ROM and an audio synthesizing circuit on a circuit board. In manufacturing, each element must be arranged on a circuit board and electrically connected to each other, which requires a long working time.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pachinko machine capable of generating a more interesting sound effect corresponding to the reach category.

[0007]

The pachinko machine of the present invention comprises:
A special symbol display device, a sub-control unit for performing control regarding sound effect output, and a voice synthesis circuit connected to the sub-control unit, wherein the voice synthesis circuit includes a sound frequency setting register and a noise frequency setting register. Register, a register for volume setting and a setting register having a region for setting start and stop of sound reproduction and a region for setting repetition, and when the special symbol display device is reached, the sub control unit Sends different sound effects to the voice synthesizing circuit by sending control commands corresponding to the reach categories.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a front view of the pachinko machine according to the embodiment. The pachinko machine 1 includes a pachinko machine main body 2 and a card unit 3 arranged side by side on the left side of the pachinko machine main body 2.

An inner frame 4 is provided on an outer frame (not shown) of the pachinko machine main body 2 by a hinge or the like so as to be openable and closable in the front direction of the drawing. A board 5 is provided. A metal frame 6 is provided in the inner frame 4 so as to surround the gaming board 5, and a glass door 7 is attached to the metal frame 6 so as to be openable and closable. Below the metal frame 6, an upper tray 8 for aligning and waiting the pachinko balls is provided, a lower tray 9 is provided below the upper tray 8, and a hitting handle 10 is provided to the right of the lower tray 9. The speakers 11a and 11b are provided inside the upper receiving tray.

A frame decoration portion 12 is provided on the upper edge of the inner frame 4, and inside the frame decoration portion 12, two frame decoration lamps A1 and A1 are provided in the center, and a frame decoration lamp is provided on the left side. A
2 and a frame decoration lamp A3 are provided, and a frame decoration lamp A2 and a frame decoration lamp A3 are provided on the right side. Further, a key decoration portion 13 is provided above the right edge of the inner frame 4, and two key decoration lamps B 1 and B 1 are arranged inside the key decoration portion 13.

FIG. 2 is a front view showing the game board 5 of the pachinko machine 1. As shown in FIG. As shown in FIG. 2, a symbol display unit 14 is provided substantially at the center of the game board 5, and a left gate 1 is provided at the lower left and right sides of the symbol display unit 14, respectively.
5, a right gate 16 is provided, and a tulip-type starting winning opening 17 driven by a solenoid or the like is provided below the symbol display unit 14, and an accessory unit 18 is provided below the game board 5 surface. It is arranged.

Further, on the surface of the game board 5, there are provided windmills 19, 19 with lamps on the left and right of the upper part of the symbol display unit 14, respectively. Winners 2 on the sleeves of the board 5
0 and 21 are provided. Further, a payout display section 22 is provided at the upper left corner of the game board 5, and a ball out display section 23 is provided at the upper right corner of the game board 5. The game board 5 is provided with an out port 24, a windmill 25, an inner rail 26, an outer rail 27, and the like, and these elements are the same as those in the related art.

FIG. 3 is a view showing the arrangement of various lamps and LEDs on the game board 5, FIG. 4 is an enlarged front view of the symbol display unit 14, and FIG. 5 is an enlarged front view of the accessory unit 18. . As shown in FIG. 3, in the game board 5, a payout LED (P
1) is provided, and a ball-out LED (P2) is provided inside the ball-out display section 23 at the upper right corner. Further, a rail decoration portion 28 is provided along the outer rail 27 on the outer upper side of the outer rail 27, and a decoration LED is provided inside the rail decoration portion 28.
(Q1) and decorative LED (Q2) are arranged alternately.

Further, decorative lamps C1, C1 are provided behind the windmills 19, 19 with lamps, respectively, and decorative lamps D1, D are provided behind the left gate 15 and the right gate 16, respectively.
1, decorative lamps E1 and E1 are respectively provided behind the normal winning openings 20 and 21, and a decorative lamp F1 is provided behind the electric tulip 29 having the starting winning opening 17.

As shown in FIG. 2, the symbol display unit 14 includes a special symbol display device 30 composed of a color liquid crystal display device at the center, and a frame 31 for incorporating and supporting the special symbol display device 30. . Frame 3
1 is provided with an arch-shaped overhang portion 32 at the top, and at the top of the overhang portion 32 and on the left and right sides of the overhang portion 32, a passage entrance 3 is provided.
3, 33, 33 are provided respectively. As shown in FIG. 4, the overhanging portion 32 is provided with a normal symbol display 34 composed of a segment type display at the center portion, and two normal symbol displays on the left and right sides of the normal symbol display 34. The number of stored LEDs 35, 35, 35, 35 are arranged. In addition, decorative LEDs (J1, J
1) is provided.

As shown in FIG. 4, on both sides of the lower portion of the overhang portion 32 of the frame 31, decorative members 3 which protrude left and right sides are provided.
6 and 36, respectively, and the left and right decorative members 36 and 3
6, decorative members 37, 37 are respectively provided below, further decorative members 38, 38 are provided below these, and a concave portion 39 is provided in the center of the frame 31 below the overhanging portion 32. The special symbol display device 30 is provided in the recess 39.
Are arranged.

Behind the left and right decorative members 36, 36, two stored number display LEDs 41, 4 for special symbols are provided.
1, 41, 41 are provided, and decorative LEDs (K1, K1) are provided inside the decorative members 37, 37, and inside the decorative members 38, 38 and inside the side wall of the frame 31, which is the upper part thereof. Three decorative LEDs (H1, H2, H3) are provided respectively.

Further, ball outlets 40, 40 are provided at the lower left and right sides of the frame 31, respectively.
In the lower part of 1, the guiding members 42 facing the ball outlets 40, 40,
Each of the guide members 42 is provided with a notch 43 between the guide members 42 for dropping the pachinko ball downward.

The display unit 44 of the special symbol display device 30 is divided into an upper symbol display unit 45 and a lower moving image display unit 46. The symbol display unit 45 further includes a left symbol display unit 47 and a middle symbol display unit 48. And a right symbol display section 49.

As shown in FIG. 5, the accessory unit 18 is provided with a large winning opening 50 opened at the center by an opening / closing door 51, and has a normal winning opening 52, 52 on the left and right and a decorative LED (M1). ~ M8), decorative LED (N1 ~ N8)
Are aggregated and deployed. A specific area 53 which is a special winning area is provided in a part of the inside of the special winning opening 50.

The special winning opening 50 is set to 15 payout openings, the normal winning opening 21 is set to 8 payout openings, and the other starting winning opening 17, the normal winning opening 20, and the normal winning opening 52, 52. Are set to six payout ports.

As described above, each element arranged on the game board 5 has been described. The left gate 15 and the right gate 16 in FIG.
Is set as the starting port for the start of symbol fluctuation in. In addition, the lottery probability of the hit related to the ordinary symbol display 34 is set to 5/10.

The starting winning opening 17 shown in FIG. 2 is connected to the left, middle,
It is set as the starting port for starting the symbol change for the right symbol. In addition, the lottery probability of big hits related to special symbols,
Two types are set, a normal probability of 1/337 and a high probability of 5/337.

The types of symbols stopped and displayed on each of the left symbol display unit 47 and the right symbol display unit 49 in the special symbol display device 30 are "1", "2", "3",
"4", "5", "6", "7", "8", "9",
There are 12 types of “X”, “Y”, and “Z”. The type of the symbol stopped and displayed on the middle symbol display section 48 is “1”,
"2", "3", "4", "5", "6", "7",
One of "8", "9", "X", "Y", "Z", "L"
There are three types.

FIG. 6 is a rear view of the game board 5 shown in FIG. On the back side 5a of the game board, there are passage entrances 33, 3 shown in FIG.
Guide paths 54 and 55 are provided on the left and right, respectively, for guiding the pachinko balls entered into the ball exits 40a and 40b into the ball exits 40a and 40b.
A guide path 56 for guiding the pachinko ball that has entered the right gate 16 to the ball exit 40 is provided in communication with the guide path 54.
A guide path 57 for guiding to b is provided in communication with the guide path 55.

At the lower part of the back face 5a of the game board, there is a starting winning port 1
7, Normal winning opening 20, Normal winning opening 21, Normal winning opening 5
A collecting gutter 58 is provided for collecting the pachinko balls that have won the winning holes 17, 20, 21, 52, 52, 50 so as to cover the winning pachinko balls 2 and 52 and the special winning opening 50. A safe ball guiding gutter 59 to be aligned in one row is disposed below the collecting gutter 58.

A start opening winning detection switch SW1 is provided corresponding to the starting winning opening 17, and the left and right gates 15,
16, gate switches SW2 and SW3 for detecting gate passage are provided, respectively, and a special winning opening winning detection switch SW4 is provided corresponding to the special winning opening 50, and a specific area inside the special winning opening 50 is provided. A specific area passage detection switch SW5 for detecting a prize to 53 is provided.
A prize detection switch SW6 is provided corresponding to the normal prize opening 21 which is an individual payout opening, and a normal electric accessory opening solenoid 60 for expanding the starting prize opening 17 and a large opening for opening the opening / closing door 51. Open prize opening solenoid 6
1. A specific area door opening solenoid 62 for opening a door (not shown) for closing the specific area 53 so that pachinko balls can be won, and a guide member drive for moving the guide members 42, 42 up and down. Motor MT is provided.

Further, at the end of the safe ball guiding gutter 27,
A safe ball detection switch 63 is provided, and a safe ball discharge solenoid 6 for discharging the safe balls one by one.
4 are provided.

Next, a control system provided in the pachinko machine of this embodiment will be described. FIG. 7 is a block diagram of a main part of a main control unit, and FIG. 8 is a block diagram of a circuit for controlling a lamp and an LED in the main control unit.
FIG. 9 is a main block diagram of the sub control unit. FIG.
In FIG. 9 to FIG. 9, illustration of a power supply line is omitted.

The main control unit 65 comprises a CPU for performing substantial control relating to the game in accordance with the game situation, a ROM storing each control program executed by the CPU, and a RAM capable of reading and writing data as needed. Have been. Note that the illustration of the internal configuration of the main control unit 65 is omitted.

The main control unit 65 includes a switch detection circuit 66, a solenoid drive circuit 67, an LED drive circuit 68,
The motor drive circuit 69, the lamp drive circuit 70, the lamp drive circuit 71, the LED drive circuit 72, the information output circuit 73, and the sub control unit 74 are connected.

The switch detecting circuit 66 includes a starting winning opening 1
7, a start-up winning detection switch SW1 for detecting a pachinko ball that has won 7; a switch SW2 for a left gate for detecting that a game ball has passed through the left gate 15; and a switch SW2 for detecting that a game ball has passed through the right gate 16. Right gate switch SW3 for detecting, large winning opening 50 of accessory unit 18
A special winning opening winning switch SW4 for detecting a pachinko ball that has won the prize, a specific area passage detecting switch SW5 for detecting a pachinko sphere winning in a specific area 53 in the special winning opening 50, and eight payout ports are set. Ordinary winning opening 21
Is connected to a winning detection switch SW6 for detecting a winning pachinko ball, and the states of the switches SW1 to SW4 are simultaneously input to the main control unit 65.

The solenoid drive circuit 67 includes a normally-operated accessory opening solenoid 60 for expanding the starting winning opening 17 and a special winning opening solenoid 61 for opening and closing the opening / closing door 51 of the accessory unit 18. Solenoid 62 for opening a specific area door for opening and driving a door closing area 53
And connected to. The solenoid drive circuit 67 individually operates the solenoids 60 to 62 at a predetermined timing in response to a command signal from the main control unit 65.

The LED drive circuit 68 includes a main control unit 65
This is a circuit for driving the display of the ordinary symbol display 34 in accordance with the control signal from the CPU and lighting and driving the stored number display LED 35 for ordinary symbols and the stored number display LED 41 for special symbols.

The motor drive circuit 69 includes guide members 42 and 4
2 is connected to a guide member driving motor MT for moving the motor 2 up and down. The guide member driving motor MT is constituted by a stepping motor. Motor drive circuit 69
Drives the guide member driving motor MT to move the guide members 42, 42 up and down 15.3 times per minute in accordance with a control signal from the main control unit 65.

The special symbol display device 30 includes a symbol display CP.
U (not shown) and a memory or the like (not shown).
The display unit 44 is connected so as to be capable of transmitting data in the direction, and according to the display command data transferred from the main control unit 65.
, A left symbol, a middle symbol, a right symbol, and a moving image.

The lamp driving circuit 70 includes a frame decoration lamp A1, a frame decoration lamp A2, and a frame decoration lamp A3 shown in FIG.
Is connected. The lamp driving circuit 70 controls the frame decoration lamps A1 to A1 according to a control signal from the main control unit 65.
3 is controlled to be turned on.

The decorative lamps C1, D1, E1, and F1 shown in FIG. 3 are connected to the lamp driving circuit 71. The lamp drive circuit 71 individually controls the lighting of the decorative lamps C1, D1, E1, and F1 according to a control signal from the main control unit 65.

The LED driving circuit 72 includes decorative LEDs (Q1) and (Q2) shown in FIG.
(K1), (H1), (H2), (H3) and decoration LE
D (M1 to M8) and decorative LEDs (N1 to N8) are connected. The LED drive circuit 72 includes a main control unit 65
According to the control signal from the LED (Q1), (Q
2) and decorative LED (J1), (K1), (H1),
(H2), (H3), the decorative LEDs (M1 to M8) and the decorative LEDs (N1 to N8) are individually controlled to be turned on.

The sub control unit 74 mainly controls the sound effect output according to the status data indicating the game state of the pachinko machine sent from the main control unit 65, and controls the lending of the pachinko balls and the paying out of the prize balls. Is what you do. The sub-control unit 74 includes a CPU for performing substantial control relating to pachinko ball lending and payout of prize balls, and an R that stores various control programs executed by the CPU.
It is composed of an OM and a RAM from which data can be read and written at any time. The sub control unit 7
The illustration of the internal configuration of 4 is omitted.

The sub-control unit 74 is connected to the main control unit 65 so as to be able to transfer data. Normally, data transfer in only one direction from the main control unit 65 to the sub-control unit 74 is performed. When the control unit 74 detects a fraud, a fraud detection signal is sent from the sub control unit 74 to the main control unit 65. The sub control unit 74 includes an LED drive circuit 75, a lamp drive circuit 76, a switch detection circuit 7,
7, voice drive circuit 78, solenoid drive circuit 79, information output circuit 73, prize ball discharging device 80, hit ball launching device 8
1. The card interface 82 is connected.

The data transferred from the main control unit 65 to the sub-control unit 74 are status data indicating the gaming state of the pachinko machine and data on the number of prize balls paid out according to the winning of the pachinko balls.

The LED drive circuit 75 receives the command signal from the sub-control unit 74 and receives the payout LED (P1) shown in FIG.
And the lighting of the ball cut LED (P2). The lamp drive circuit 76 receives a command signal from the sub-control unit 74 and controls lighting of the key decoration lamp B1.

The switch detection circuit 77 includes a metal frame opening detection switch 84 for detecting the opening of the metal frame 6, a supply ball out detection switch 85 for detecting a ball out of the ball tank, and a safe ball detection. Safe ball detection switch 63
The detection signal (see FIG. 6) is input to the sub control unit 74.

The voice driving circuit 78 includes a voice synthesizing circuit and a sound amplification amplifier, which will be described later, and responds to a command output from the sub-control unit 74 in response to status data indicating the game state of the pachinko machine. The data is synthesized and reproduced, amplified and output as sound effects from the speakers 11a and 11b.

In response to the payout control signal output from the sub-control unit 74, the prize ball discharging device 80 discharges pachinko balls in the number corresponding to the ball lending, and pays out six, eight, and fifteen prize balls. Individual payout is performed. Hitting ball launcher 81
Operates in response to the drive signal output from the sub-control unit 74, and bounces the pachinko ball toward the game board 5 surface. The operating state of the hit ball firing device 81 is input to the sub control unit 74.

The card interface 82 is connected to the ball lending operation unit 83 provided on the front of the card unit 3 and the upper tray 8 shown in FIG. 1, and receives the amount information sent from the card unit 3 and the ball lending operation unit 83. The ball lending information is output to the sub-control unit 74, and the ball lending completion signal sent from the sub-control unit 74 is output to the card unit 3.

The information output circuit 73 is a circuit for outputting the information data output from the main control section 65 and the information data output from the sub control section 74 to a host computer, such as a hall computer.

The information data output from the main control unit 65 includes information representing the state of the jackpot from the start of the jackpot to the end of the jackpot (high level from the start of the jackpot to the end of the jackpot), the state of the jackpot from the start of the jackpot to the end of the jackpot, and Information indicating that the high probability is in progress (high level during the period from the start of the big hit to returning to the normal probability), information indicating the determination of the special symbol (high level for a predetermined time each time the special symbol is stopped),
Information representing winning in the specific area 53 (high level for a predetermined time each time a winning is detected in the specific area 53), and information representing determination of a normal symbol (normally high level for a predetermined time each time a symbol is stopped). is there.

The information data output from the sub-control unit 74 includes information indicating the occurrence of a broken ball (high level during a period in which the replenishment-ball-out detection switch 85 detects the out-of-ball state), and indicates unauthorized opening of the metal frame 6. Information (metal frame opening detection switch 8
4 is at the high level during the detection of the open state of the gold frame 6, information indicating the prize ball payout (high level for a predetermined time every time 10 prize balls are discharged), and information indicating the ball lending (ball lending). It is at a high level for a predetermined time every 25 prize balls discharged in response to the operation), and a stop signal of the hit ball launching device 81 is transferred from the hall computer and input to the sub control unit 74. You.

Next, the audio drive circuit 78 of the present embodiment will be described. FIG. 10 is a circuit block diagram of the audio drive circuit 78. The voice drive circuit 78 includes a voice synthesis control IC 86 constituting a voice synthesis circuit and a voice synthesis control IC.
The amplifier 86 comprises amplifiers 87 and 88 to which a synthesized voice signal is applied.

The voice synthesizing control IC 86 sequentially reads out the performance data from the performance data ROM 95 in response to a command from the sub-control unit 74 and a performance data storage means comprising a performance data ROM 95 storing performance data. An audio reproducing means 89 for reproducing and outputting, and an electronic volume 96
, 97, a two-channel digital mixer 98, D /
A converter 99 and mix level controller 10
0, a reset signal input unit 101, and a clock frequency input unit 102 are integrally included.

Further, the sound reproducing means 89 includes a sound source controller 90 for reproducing a musical sound and an RO for performance data.
A sequencer 91 and a sequencer 92 for sequentially reading out the tone data stored in the M95 and supplying the tone data to the tone generator controller 90, and an ADPCM (Adaptive Difference) stored in the performance data ROM 95.
Tial Pulse Code Modulatio
n) AD for sequentially reading sound data and reproducing the sound
It comprises a PCM controller 93 and a CPU interface 94 for giving commands given from the sub-control unit 74 to the sequencer 91, the sequencer 92, the ADPCM controller 93, and the mix level controller 100.

The reset signal input section 101 is for resetting the voice synthesis control IC 86 in response to the input of the reset signal from the sub control section 74. It is reset when the power is turned on. The clock frequency input unit 102 is for inputting a clock signal used in the voice synthesis control IC 86, and is connected to a crystal oscillation circuit (not shown).

FIG. 11 is a memory map showing the storage state of voice synthesis data stored in the performance data ROM 95. The performance data ROM 95 has a total of 2
It has a megabit storage capacity and has an address of 000000
(Hexadecimal notation) to 0000C0, ADPCM
The start address tables from the sound number 1 to the sound number 63 are from address 0000C1 to address 00018.
By the time, number 1 to number 63 of ADPCM sound
End address table up to the address 00018
From 1 to 00003F, a start address table from tune number 1 to number 63 is stored. From addresses 000240 to 03FFF1, ADPCM sound data and tune data are stored, respectively.

FIG. 12 is a diagram showing the structure of one sound of the ADPCM sound data. One ADPCM sound data is composed of 4 bits, and two sampling times are treated as one data. Then, n pieces of ADPCM sound data are sequentially stored from the start address AS to the end address AE.

FIG. 14 is a diagram showing the structure of one piece of music data. The song data consists of steps, register addresses,
Three bytes each having one byte of register data as a set are configured as one block. The step is a wait time until the next block is read, and (wait time) = (step set value) × (minimum step time)
It is. The minimum step time is set in a tempo control register of the sequencer described later. The register address is a setting address of each setting register in the tone generator controller 90 described later. The register data is setting data to be set in each setting register in the tone generator controller 90 described later specified by the register address.

FIGS. 15 and 16 show the sound source controller 9.
7 is a register map of various setting registers arranged in the register 0. The sound source controller 90 includes channels 1A and 1
B, 1C, a total of three channels of a tone generator, a noise generator, a mixer for mixing the tone generated by the tone generator with the noise generated by the noise generator, and an output of the mixer. A first-system sound source controller including an envelope generator for generating an envelope of an output level by changing the frequency, and channels 2A, 2B and 2C.
A tone generator having a total of three channels, a noise generator, a mixer for mixing a tone generated by the tone generator with a noise sound generated by the noise generator, and changing an output of the mixer. And a second sound source controller including an envelope generator for generating an output level envelope.

The tone generator controller 90 simultaneously operates the first tone generator controller and the second tone generator controller, thereby providing a performance data ROM.
From a maximum of 63 pieces of music data stored in the memory 95, up to two simultaneous performances can be performed.

As shown in FIGS. 15 and 16, the first tone generator controller of the tone generator controller 90 has eight-bit setting registers AOA1, AOA2 and AOA2 for setting reproduction conditions when reproducing musical sound data. AOB1,
AOB2, AOC1, AOC2, ANO1, AMI1,
AOA3, AOB3, AOC3, AEN1, AEN2
AEN3, AOA4, AOB4, AOC4
Similarly, the tone generator controller of the system similarly sets each of the 8-bit configuration registers BOA1, BOA2, BOB1, BOB2, and B for setting playback conditions when music data is played back.
OC1, BOC2, BNO1, BMI1, BOA3, B
OB3, BOC3, BEN1, BEN2, BEN3, B
OA4, BOB4, BOC4.

Next, each setting register will be described with reference to FIGS. Since the first tone generator controller and the second tone generator controller have the same configuration, the contents of each setting register will be described only for the first trace, and the description of the second trace will be omitted. .

As shown in FIG. 17, the setting register AOA
Reference numerals 1 and AOA2 are registers for setting a tone frequency generated by the tone generator of channel A in the first tone generator controller. The setting register AOA1 and the setting register AOA2 set one frequency as a pair. D7 (bit 7) to D0 (bit 0) of the setting register AOA1 are set to TP7 to TP0, respectively.
Using D3 (bit 3) to D0 (bit 0) of A2 as TP11 to TP8, respectively, the setting register AOA2
D7 (bit 7) to D4 (bit 4) are not used.

The tone frequency ft produced by the tone generator is
ft = (fundamental frequency) / (16 TP) MHz. However, TP = (TP11 × 2048) + (TP10 × 1
024) + (TP9 × 512) + (TP8 × 256) +
(TP7 × 128) + (TP6 × 64) + (TP5 × 3
2) + (TP4 × 16) + (TP3 × 8) + (TP2 ×
4) + (TP1 × 2) + TP0.

Setting registers AOB1 and AOB2 for setting the tone frequency generated by the tone generator of channel B in the first tone generator controller, and the tone frequency generated by the tone generator of channel C in the first tone generator controller. Setting register AOC for setting
1 and AOC2 have the same configuration.

Further, setting registers BOA1 and BOA for setting the tone frequencies generated by the tone generators of channels A, B and C in the second tone generator controller, respectively.
OA2, BOB1 and BOB2 and BOC1 and BO
The same applies to C2.

As shown in FIG. 18, setting register ANO
Reference numeral 1 denotes a register for setting a noise frequency generated by the noise generator in the first system sound source controller,
D4 (bit 4) to D0 (bit 0) of the setting register ANO1 are used as NP4 to NP0, respectively, and D7 (bit 7) to D5 (bit 5) of the setting register ANO1 are used.
Is not used.

The frequency f of the noise generated by the noise generator
n is fn = (fundamental frequency) / (16 NP) MHz. However, NP = (NP4 × 16) + (NP3 × 8)
+ (NP2 × 4) + (NP1 × 2) + NP0. Further, a setting register BNO for setting a noise frequency generated by a noise generator in the second system tone generator controller
1 has the same configuration.

As shown in FIG. 19, setting register AMI
Reference numeral 1 denotes a register for setting whether or not to output a tone (tone) and noise for each of the channels A, B, and C in the first tone generator controller.
D5 (bit 5) to D3 (bit 3) of MI1 are for noise, are set to channel C, channel B, and channel A, respectively, and D2 (bit 2) to D0 (bit 0) are for musical sound. Are set to channel C, channel B and channel A, respectively, and the setting register AN
D7 (bit 7) to D6 (bit 6) of O1 are not used.

If the value of the corresponding bit of each channel is 0, the output is obtained. If both the noise and the tone are 0, the output is a mixing output. Are output in the setting registers AOA3 to AOC3.

In the second tone generator controller, a setting register BMI for setting whether or not to output a musical tone (tone) and noise for each of the channels A, B, and C.
1 is the same as the setting register AMI1.

As shown in FIG. 20, setting register AOA
Reference numeral 3 denotes a register for setting the volume of channel A in the first tone generator controller.
Let D4 (bit 4) of A3 be M, and D3 (bit 3) to
Using D0 (bit 0) as L3 to L0 respectively,
D7 (bit 7) to D5 (bit 5) of the setting register AOA3 are not used.

When M = 0, the volume level to be set is 0 to 4 bits by L4 to L0 data.
It can be set to one of 16 levels up to 15. When M = 1, it can be set in 32 levels from 0 to 31 by 5-bit data of E4, E3, E2, E1, and E0 generated by the envelope generator. , E2, E1, and E0 change with time, so that the variable volume setting is performed.

A setting register AOB3 for setting the volume of channel B in the first tone generator controller.
The setting register AOC3 for setting the volume of the channel C in the first tone generator controller also includes:
The configuration is the same as that of the setting register AOA3.

Further, each of the setting registers BOA3, BOB3 and BOC3 for setting the volume of each of the channels A, B and C in the second tone generator controller has the same configuration.

As shown in FIG. 21, setting register AEN
Reference numerals 1 and AEA2 are registers for setting the repetition frequency of the envelope in the first tone generator controller, and the setting register AEN1 and the setting register AEN2 set one frequency as a pair. Setting register AEN
D7 (bit 7) to D0 (bit 0) of E1
P7 to EP0, and D7 (bit 7) to D0 (bit 0) of the setting register AEN2 are EP15 to TP8, respectively.
Use as

The repetition frequency fe of the envelope is f
e = (fundamental frequency) / (256 EP) MHz. However, EP = (EP15 × 32768) + (EP14 ×
16384) + (EP13 × 8192) + (EP12 ×
4096) + (EP11 × 2048) + (EP10 × 1
024) + (EP9 × 512) + (EP8 × 256) +
(EP7 × 128) + (EP6 × 64) + (EP5 × 3
2) + (EP4 × 16) + (EP3 × 8) + (EP2 ×
4) + (EP1 × 2) + EP0.

The setting registers BEN1 and BEN2 for setting the repetition frequency of the envelope in the second tone generator controller have the same configuration as the setting registers AEN1 and AEN2.

As shown in FIG. 22, setting register AEN
Reference numeral 3 denotes a register for setting the shape of an envelope in the first tone generator controller.
Using D3 (bit 3) to D0 (bit 0) of N3 as 4-bit data, D7 (D7) of the setting register AEN3
(Bit 7) to D4 (Bit 4) are not used. In addition,
The envelope shape to be set is as shown in FIG.

A setting register BEN3 for setting the shape of the envelope in the second tone generator controller.
Has the same configuration as the setting register AEN3.

As shown in FIG. 23, setting register AOA
Reference numeral 4 denotes a register for setting a panpot (localization) of the channel A in the first tone generator controller, and uses D3 (bit 3) to D0 (bit 0) of the setting register AOA4 as 4-bit data to set Register A
D7 (bit 7) to D4 (bit 4) of OA4 are not used.

The localization that can be set is D3 to 16 in 16 steps.
When D0 is “1000”, the localization is the center,
When D3 to D0 are “0000”, the sound is muted. It should be noted that the ratio of the output to the left and right channels at the time of output is as shown in FIG.

A setting register A for setting the channel B panpot in the first tone generator controller
OB4 and a setting register AOC4 for setting a channel C panpot in the first system tone generator controller
Has the same configuration as the setting register AOA4.

Further, setting registers BOA4, BOB4 and BOC4 for setting respective pan pots for channels A, B and C in the second tone generator controller have the same configuration.

FIG. 24 is a register map of various setting registers provided in the ADPCM controller 93. The ADPCM controller 93 includes a performance data RO.
A sound designation register for designating ADPCM sounds (numbers 1 to 63) set in M95, a volume setting register for setting volume, a panpot setting register for panpot setting, and playback One channel for reproducing the ADPCM sound data is configured as an on / off register for specifying start and stop of reproduction and a repetition setting register for setting repetition of reproduction.
Up to a total of eight channels, and eight ADPCM sounds can be reproduced simultaneously.

Next, each setting register for setting the reproduction condition of the ADPCM sound in each channel will be described with reference to FIGS. Since the configuration of each setting register is the same for channels 1 to 8, only the setting registers PA1, PA2, PA3, and PA4 of channel 1 will be described as representatives, and the setting registers PB1, PB2, and PB of channel 2 will be described.
3, PB4 to channel 8 setting registers PH1, P
A description of H2, PH3, and PH4 is omitted.

As shown in FIG. 25, setting register PA1
Uses D7 (bit 7) to D6 (bit 6) as 2-bit data for frequency setting, and uses D5 (bit 5) to D0 (bit 0) as 5-bit data and
Used to specify the DPCM sound number.

The frequencies that can be set are D7 = 1 and D6 = 1
32 kHz for D, 16 for D7 = 1 and D6 = 0
kHz, D7 = 0, 8 kHz when D6 = 1, D7 =
It is 4 kHz when 0 and D6 = 0. ADPC
The M tone number can be selected from one of a range from 1 to 63.

As shown in FIG. 26, setting register PA2
Is a register for setting the volume. D3 (bit 3) to D0 (bit 0) are used as 4-bit data for setting the volume, and D7 (bit 7) to D4 (bit 4) are used. do not do. Settable volume is from 0 to 15
Can be set in 16 steps in the range of 0, 0 means mute, and 15 means maximum volume.

As shown in FIG. 27, setting register PA3
Is a register for setting a pan pot, and D3
(Bit 3) to D0 (Bit 0) are used as 4-bit data for setting the panpot, and D7 (Bit 7) to D4 (Bit 4) are not used. The localization that can be set can be set in 16 steps, and when D3 to D0 are “1000”, the localization becomes the center, and D3 to
When D0 is “0000”, the sound is muted.

As shown in FIG. 28, setting register PA4
Uses D1 (bit 1) for reproduction start / stop control, uses D0 (bit 0) for repetitive reproduction setting, and uses D7 (bit 7) to D2 (bit 2).
Is not used. Playback starts when D1 = 1,
When D1 = 0, playback is stopped. D0 = 1
, Reproduction is repeated, and when D0 = 0, reproduction is performed only once.

FIG. 29 is a register map of various setting registers provided in the sequencer 91 and the sequencer 92 and a setting register provided in the mix level controller 100. Setting register SR of sequencer 91
1, SR2, SR3, and SR4, and setting registers SS1, SS2, SS3, and S of the sequencer 92.
Since the respective configurations of S4 are the same, the setting registers SR1, SR2, SR3 and SR of the sequencer 91 are
4 will be described, and description of the sequencer 92 will be omitted.

As shown in FIG. 30, setting register SR1
Uses D7 (bit 7) for controlling the start / stop of musical performance, uses D6 (bit 6) for setting the repetition of performance, and sets D5 (bit 5) to D0 (bit 0) to 5 bits. Of the song number.

When D7 = 1, the performance starts.
When 7 = 0, the performance stops. When D6 = 1, the performance is repeated, and when D6 = 0, the performance is performed only once. The tune number can be selected from one of a range of 1 to 63.

As shown in FIG. 31, setting register SR2
Is a register for setting a minimum step time for determining a performance tempo. D5 (bit 5) to D0 (bit 0)
To TMP5, TMP4, TMP3, TMP2, respectively.
Used as TMP1 and TMP0, and set register SR2
D7 (bit 7) to D6 (bit 6) are not used.

The inverted data of the bit data TMP5 to TMP0 are respectively expressed as tmp5, tmp4, tmp3 and tm.
If it is expressed as p2, tmp1, and tmp0, the set minimum step time TMP (ms) is TMP = (tm
p5 × 4) + (tmp4 × 2) + (tmp3 × 1) +
(Tmp2 × 0.5) + (tmp1 × 0.25) + (t
mp0 × 0.125). However, 0.125 ≦ T
MP ≦ 8. The tempo can be changed by rewriting during the performance.

As shown in FIG. 32, setting register SR3
Is a register for setting which of the channels 1 to 8 of the ADPCM controller 93 is occupied and used. D of setting register SR3
7 (7 bits) to D0 (0 bits) are set in the occupancy setting flags for channel 8 to channel 1 in order.

When the value of each occupancy setting flag is 1, occupancy is used, and when the value of the occupancy setting flag is 0, no use is made. Note that the above-mentioned ADPCM
ADP is directly written into each setting register corresponding to channel 1 to channel 8 of the controller 93 to perform ADP.
When the reproduction is performed by the CM controller 93, the occupation designation of the channel used in the setting register SR3 on the sequencer side is not used.

As shown in FIG. 33, setting register SR4
Are the first channels A,
This register is used to set which of the six channels B, C and the second system channels A, B, C is occupied and used. D5 of setting register SR4
(5 bits) is for setting the occupancy of the second channel C,
D4 (4 bits) of the setting register SR4 is used for setting the occupancy of the channel B of the second system.
(3 bits) are used for setting the occupation of the second channel A,
D2 (2 bits) of the setting register SR4 is used to set the occupancy of the channel C of the first system.
(1 bit) is for occupancy setting of the first channel B,
D0 (0 bit) of the setting register SR4 is set to each occupancy setting flag for occupancy setting of the channel A of the first system. Note that D7 (bit 7) of the setting register SR4
ＤD6 (bit 6) is not used.

When the value of each occupancy setting flag is 1, occupancy is used, and when the value of the occupancy setting flag is 0, no occupancy is used.

Note that the sequencer 91 occupies and uses the first system channels A, B, and C of the tone generator controller 90, and the sequencer 92 occupies the second system channels A, B, and C of the tone generator controller 90. By using this, it is possible to simultaneously perform a maximum of two pieces of music from a maximum of 63 pieces of music data stored in the performance data ROM 95.

FIG. 13 shows the mix level controller 1
FIG. 7 is a diagram showing the contents of a setting register MIX provided in the 00. The setting register MIX is a register for setting the tone level of the tone generator controller 90 when mixing the tone generated by the tone generator controller 90 and the reproduced tone reproduced by the ADPCM controller 93. Setting register M
D3 (bit 3) to D0 (bit 0) of IX are used as mix3, mix2, mix1, and mix0, respectively, and D7 (bit 7) to D4 (bit 4) of the setting register MIX are not used.

The mixing ratio MIX of the settable tone from the tone generator controller 90 to the volume of the ADPCM controller 93 is MIX = (mix3 / 4) + (mi
x / 8) + (mix 1/16) + (mix 0/32). Note that the maximum volume of the musical tone from the sound source controller 90 is larger than the maximum volume of the ADPCM controller 93.
15/32.

Next, the sub control unit 74 will be described with reference to FIG.
Tone and ADPCM of voice synthesis control IC86
The sound reproducing operation will be described. Note that, as an example, the sound effect generated according to the gaming state may be such that the left symbol and the right symbol stop at the same symbol on the special symbol display device 30 and a big hit may occur depending on the stop symbol of the middle symbol. A description will be given as a sound effect (song number 4 and a drum sound) that is emitted when a state occurs (hereinafter, referred to as reach).

The sub-control unit 74 transmits a command corresponding to the occurrence of the reach to the voice synthesis control IC 86. First, the sub-control unit 74 sends a command having a content "start the performance of the melody of the song number 4" to the voice synthesis control IC 86. The command is, specifically, C
The address of each setting register of the sequencer 91 is specified to the PU interface 94, and the setting data to be written to the sequencer 91 is transmitted. After that, data to be set by addressing is transmitted to the mix level controller 100. The setting data to be written into the sequencer 91 is data to be written into each of the setting registers SR1 to SR4 of the sequencer 91,
Is musical tone level data to be written into the setting register MIX.

In the setting register SR1, the performance start / stop setting flag has a value of 1 which defines the performance start, the performance repetition setting flag has a value of 1 which defines the repetitive performance, and the data "000100" which specifies the number 4 as the music number designation data. Is set.

Although the specific numerical value of the minimum step time for determining the performance tempo is unknown, the setting data is set in the setting register SR2 so as to satisfy 0.125 ≦ TMP ≦ 8.

In the setting register SR3, in this case, a musical tone is generated by giving the music data to the tone generator controller 90. Therefore, since the occupied channel is not specified to the ADPCM controller 93, all channels are not occupied. Data “00000000” is set.

In this case, the setting register SR4 contains the first
Since the musical tone is reproduced by occupying the channels A, B, and C of the tone generator controller of the system, data "00000111" that defines this is set.

When the sequencer 91 is designated by the sub-control unit 74, the CPU interface 94
The sequencer 9 sends the command “Start the melody of song number 4” sent from the sequencer 9.
1 is written to each setting register.

The sequencer 91 reads out the song data of the song number 4 from the performance data ROM 95 one block at a time in response to the command "Start the performance of the melody of the song number 4" (see FIG. 14).
Each setting register AOA1 to AOC of the tone generator controller 90 corresponding to the register address of the read music data
Then, the register data of the music data is sequentially written in No. 1 (see FIG. 15).

The tone generator controller 90 produces a tone at a tone frequency set by data separately written for each of the channels A, B, and C, and
While digitally reproducing this musical tone according to the set volume, envelope frequency, envelope shape and panpot, it generates noise at the set noise frequency, mixes the musical tone and noise based on the set mix specification, and creates an electronic volume. The signal is output to a two-channel digital mixer 98 via 96.

Also, the mix level controller 100
The specific numerical value of the tone level data to be written into the setting register MIX is unknown, but is any of 0 (silence) to 15 (maximum volume).

At this point, it is assumed that the ADPCM sound is not being reproduced by the ADPCM controller 93. Therefore, the ADPCM controller 93 does not output the reproduced sound. The two-channel digital mixer 98 includes a setting register MIX of the mix level controller 100.
Is mixed with the digital musical sound sent from the tone generator controller 90 and the digital reproduced sound sent from the ADPCM controller 93, using the value of the musical sound level data written into the D / A converter 99. In this case, only the digital tone transmitted from the tone generator controller 90 is output to the D / A converter 99.

The D / A converter 99 converts the mixed digital sound output from the two-channel digital mixer 98 into analog, and then distributes the analog sound to the left and right terminals by an analog switching method, and the left and right amplifiers 87 and 88.
Give to. The amplifiers 87 and 88 amplify the voice synthesis signal and generate stereo voice (music number 4) from the speakers 11a and 11b shown in FIG.

The musical sounds of channels A, B, and C are
By changing the panpot data set in the setting registers AOA4, AOB4, and AOC4 (see FIG. 23),
The output levels of the left and right channels at the time of output can be distributed to a predetermined amount, and the sound source localization can be changed to the center, to the left, or to the right.
The sound source localization can be moved back and forth by changing according to the envelope repetition frequency and the envelope shape set in N1 to AEN3, and by changing these in combination, the sound source localization orbits around the player. A sound effect can be generated.

As described above, while the stereo sound (music number 4) is being generated from the speakers 11a and 11b, the sub-control unit 74 sets the content of "generate a drum sound (voice C)". Command for voice synthesis control IC8
Send to 6. The reproduced sound is reproduced from channel 1 of the ADPCM controller 93. Specifically, the command is transmitted to the CPU interface 94 by A
The address of each setting register of the DPCM controller 93 is designated, and the setting data to be written is transmitted. The setting data is data to be written to the setting registers PA1 to PA4 of the ADPCM controller 93.

The setting register PA1 has a frequency of 8.0 k.
The data "01" specifying the Hz and the data "0000011" specifying the ADPCM sound number 3 of the voice C are set.

Data (one of 0 to 15) for determining the sound volume is set in setting register PA2. Also,
Data (one of the data shown in FIG. 27) for setting the pan pot is set in the setting register PA3. Further, in the setting register PA4, a value 1 specifying the reproduction start is set in the reproduction start / stop setting flag, and a value 0 specifying the reproduction only once is set in the reproduction repetition setting flag.

When the sub-control unit 74 specifies the ADPCM controller 93, the CPU interface 94
The ADPCM controller 93 sequentially transmits the command “generate a drum sound” sent from the sub control unit 74.
In each of the setting registers PA1 to PA4.

The ADPCM controller 93 reads the ADPCM sound data of the ADPCM sound number 3 from the performance data ROM 95 one byte at a time in response to the command "generate a drum sound" (see FIG. 12).
ADPC according to set frequency, volume and pan pot
It reproduces in the M system and outputs the reproduced digital reproduced sound.
The digital reproduction sound output from the ADPCM controller 93 is input to the two-channel digital mixer 98 via the electronic volume 97.

The two-channel digital mixer 98 uses the value of the musical sound level data written in the setting register MIX of the mix level controller 100 to determine the digital musical sound transmitted from the tone generator controller 90 and the digital reproduced sound transmitted from the ADPCM controller 93. And outputs the result to the D / A converter 99.

The D / A converter 99 converts the mixed digital musical sound and digital reproduced sound output from the two-channel digital mixer 98 into analog, and then distributes them to the left and right terminals by an analog switching method, and the left and right amplifiers 87 and 88. Give to. The amplifiers 87 and 8
8, a speaker 11 shown in FIG.
The stereo sound (music number 4 music sound) is generated from a and 11b.

As a result, a drum sound is emitted once so as to overlap the music number 4 at the time of the reach being performed from the speakers 11a and 11b.

The performance stop of the music is stopped by writing a value 0 defining stop into the performance start / stop setting flag of the setting register SR1 of the sequencer 91.

Next, the output and display operation of sound effects and sounds generated according to the operating state of the pachinko machine 1 of the embodiment will be described. 34 and 35 are diagrams showing the correspondence between the operation state of the pachinko machine 1 and the output display operation of sound effects and sounds. FIGS. 36 to 38 are diagrams showing the triggers and operating ranges of the types of sound effects and sounds.

When the power of the pachinko machine 1 is turned on, the left, middle and right symbols of the special symbol display device 30 are "3" and "3", respectively.
"5" and "7" are displayed, a predetermined picture at power-on is displayed on the moving image display section 46, and the picture display 34 normally displays "0". Also, the storage number display LEDs 35 and 41, frame decoration lamps A1 to A3, decoration lamps C1, D1, E1, F
1. Decoration LED (J1), (K1), (H1), (H
2), (H3), decoration LED (M1-M8), decoration LE
D (N1 to N8), payout LED (P1) and ball out LE
All of D (P2) are off. The guide member drive motor MT is driven to rotate, and the guide members 42, 42
Move up and down 15.3 times per minute.

A player inserts a prepaid card into the card insertion slot 3a of the card unit 3 and
Is operated, a predetermined number of pachinko balls corresponding to the operation are discharged from the prize ball discharging device 80 and lent to the upper tray 8. Then, when the player rotates the hitting handle 10, the hitting ball launching device 81 is operated to hit the pachinko ball toward the game board 5 surface. When the hit ball firing device 81 operates, the operation state is detected by the sub-control unit 74, and the key decoration lamp B1 is turned on. Note that the key decoration lamp B1 is always turned on while the hit ball firing device 81 is operating.

When the game ball passes through one of the left and right gates 15 and 16, the passage of the game ball is detected by one of the left gate switch SW2 and the right gate switch SW3. The pachinko balls that have entered the left and right gates 15 and 16 return to the game board 5 from the respective ball outlets 40a and 40b.

When the passage of the pachinko ball to the left and right gates 15 and 16 is detected, the symbol of the ordinary symbol display 34 starts to change, and after about 6.0 seconds, the change of the symbol stops.
When a new pachinko ball is detected to pass through the left and right gates 15 and 16 while the symbol of the ordinary symbol display 34 is being changed, up to four gate passages are stored and the number of stored gates is changed to the number for the ordinary symbol. The number of LEDs is displayed by the stored number display LEDs 35a to 35d. The lighting order is the LED 35a,
LED 35b, LED 35c, and LED 35d are in that order.

When the normal symbol whose fluctuation is stopped is any one of "1", "3", "5", "7", and "9", the ordinary electric accessory opening solenoid 60 is activated, and the prize is won. The opening (start winning opening) 17 is opened for a predetermined time. In addition, the opening time of the start winning opening 17 is, when the jackpot lottery probability related to the start winning opening 17 is the normal probability, the opening is performed for 0.3 seconds, the lottery probability of the jackpot related to the starting winning opening 17 is set. When the probability is high, the spreading operation is performed three times for 1.7 seconds. When the pachinko ball wins the starting winning opening 17 during the expanding operation, the expanding operation ends. Note that the jackpot lottery probability relating to the starting winning opening 17 will be described later.

When the game ball wins the start winning port 17, the start port win detection switch SW1 detects the start port winning of the pachinko ball. When the start opening winning of the pachinko ball is detected, the symbol of the special symbol display device 30 is changed to a left symbol, a right symbol,
Start to change in the order of the middle symbol. At the start of the special symbol change, the value of the animation flag is determined. If the value of the animation flag is 0, the sound effect 1 during the change of the special symbol is emitted, while the value of the animation flag is 1
If it is ５5, the sound effect 2 is generated and sounds until the left symbol stops.

When a new winning of the pachinko ball into the starting winning opening 17 is detected during the change of the special symbol, up to four starting opening winnings are stored, and the number of the stored winnings is stored in the special symbol. Number display LED 41a-41d.

A random counter RND1 is used in the special symbol display device 30 to determine in advance whether or not to generate a big hit in the symbol variation display result.
The value of the random counter RND1 is counted up one by one at a predetermined timing in a range of 0 to 336. Then, when the start opening winning is detected, the random counter R
The value of ND1 is read and stored, and the counter value stored at a predetermined timing during the period from the start of the change of the symbol to the stop of the left symbol is read, and is compared with a predetermined value for the big hit to obtain the big hit. Is determined.

When about 5.3 seconds or more have elapsed since the start of the change of the special symbol, the symbols are stopped in the order of the left symbol, the right symbol, and the middle symbol to determine the symbol. If the left symbol and the right symbol, which have been fixed and stopped, coincide with each other at the time of final stop of the right symbol, reach occurs.

In the moving picture display section 46 of the special symbol display device 30, forty-six kinds of reach patterns are set according to the kind of the character displayed in the moving picture and the difference in movement (difference in story development). The reach patterns are divided into eight groups, reach section a to reach section h, divided into groups each having the same type of lamp and LED display and sound effect.

The random counter RND3 is used to select one of these reach sections. The value of this random counter RND3 is 0 to 7
Are counted up one by one at a predetermined timing in the range of. Then, the type of the reach section is determined by the value of the random counter RND3 at the time when it is determined that the reach has occurred when the right symbol is fixed and stopped.

When the left symbol, the right symbol, and the middle symbol of the above-mentioned special symbols stop, the sound effect 3 sounds once when each symbol stops. However, when performing the reach operation, the left symbol,
The right symbol sounds only when stopped.

Hereinafter, only the case where the middle symbol performs the reach operation will be described. When the left symbol and the right symbol stop and the middle symbol starts the reach operation, the voice A "reach" is generated after the right symbol stops. Next, the sound effect 4 at the start of the reach operation starts to sound after the voice A “reach”.

When the generated reach pattern is reach section a, and when the stopped middle symbol is "L", a re-lottery operation for starting the change of the middle symbol is performed again.

When the generated reach pattern is the reach section b, the sound F of “pyeong” is generated, the sound C of “dawn” is generated, and the sound effect 5 of the first half of the reach section b sounds next. start. Then, after a lapse of a predetermined time, the sound effect 6 in the latter half of the reach section b starts to sound after the sound effect 5, and sounds until the middle symbol stops. Even when the generated reach pattern is the reach section b, when the stopped middle symbol is “L”, the re-lottery operation for starting the variation of the middle symbol is performed again.

The generated reach pattern is reach category c to
In the case of f, the sound F of "pyeong" is generated, and then the sound effect 7 starts to sound until the middle symbol stops.
During the generation of the sound effect 7, the sound G of “Gyun” is changed to 2
Generated multiple times. In the reach categories e and f, when the middle symbol returns by one symbol, the sound J of "Hyuwan" is generated. Also, when the generated reach pattern is the reach section c to f, when the stopped middle symbol is “L”, the re-lottery operation for starting the variation of the middle symbol is performed again.

If the generated reach pattern is reach section g, a sound F of "pyeong" is generated, a sound B of "pa-on" is generated, and then a sound effect 8
Starts to sound and sounds until the middle symbol stops. Note that a drum sound “Dan” (voice D) and a drum sound “Dan” (voice E) are generated over the sound effect 8.

When the generated reach pattern is reach section h, a sound F of “Pyeong” is generated, then a sound B of “Paohn” is generated, and then a sound effect 8
Starts to sound and sounds until the elephant in the movie starts throwing the symbol. When the elephant of the moving image starts throwing the symbol, the sound effect 9 starts to sound and sounds until the middle symbol stops.
Note that a drum sound “Dan” (voice D) and a drum sound “Dan” (voice E) are generated over the sound effect 8. Also, every time the elephant in the video throws a design,
Is generated once. Furthermore, when the middle symbol returns by one symbol at the time of the reach section h, "Piyoyoyon"
Is generated.

When the generated reach pattern is reach section a, reach section b, reach section c-f, a re-lottery operation is performed.
2 starts to sound after switching to the re-lottery screen, and sounds until the middle symbol stops.

The combinations of the left, middle, and right symbols that have been fixed and stopped are “111”, “222”, “333”, and “44”.
4 "," 555 "," 666 "," 777 "," 88 "
8 "," 999 "," XXX "," YYY "," ZZ "
When it becomes "Z", a big hit occurs. In the case of a combination other than the above-mentioned combination, the combination will be out of order.

When the middle symbol performs the reach operation and is fixed and stopped, in all reach patterns, when the middle symbol comes off and stops at the symbol, the sound effect 10 sounds, and the sound effect 11 sounds after the sound effect 10.

When the middle symbol performs a reach operation and stops, the sound effect 13 is sounded when the middle symbol stops at the big hit symbol in all reach patterns.

When a big hit occurs, the special winning opening 50
Opened for 0 seconds. Further, the door of the specific area 53 is opened simultaneously with the opening of the special winning opening 50. At the time of the big hit, the sound effect 14 is sounded after the sound effect 13 until the opening of the first big winning opening.

If ten game balls are awarded during the opening of the special winning opening 50, the winning winning opening 5 is set with the tenth winning.
0 closes. If one game ball passes through the specific area 53 during the opening of the special winning opening 50, the door of the specific area 53 closes, and after the special winning opening 50 is closed, the special winning opening 50 is repeated again. Open. The opening operation of the special winning opening 50 is
Up to 16 times including the first opening. At the time of a big hit, the sound effect 15 is emitted from the start of opening of the first special winning opening to the start of opening of the last special winning opening. And, from the start of the opening of the final winning opening to the end of the pause after the opening ends,
Sound effect 16 sounds.

[0150] The sound effect 16 generated when the special winning opening 50 is opened can also be more exciting by moving the sound source back and forth, left and right, and orbiting around the player.

Further, when the metal frame 6 is opened due to wrongdoing, the opening of the metal frame 6 is detected by the metal frame opening detection switch 84, and a detection signal of the metal frame opening detection switch 84 is input to the sub control unit 74. You. In response, sub-control unit 84 outputs a fraud detection signal to main control unit 65. The main controller 65 turns on the decoration LED (Q1) and the decoration LED (Q2) according to the fraud detection signal. In addition, the starting winning opening 1
If the jackpot lottery probability for 7 is high,
In addition to the lighting of the decoration LED (Q1) and the decoration LED (Q2), the frame decoration lamps A1, A3 and A2 alternately blink at a cycle of 251 ms. In addition, when detecting an irregularity of disconnection or short circuit, or an irregularity of movement of the special winning opening winning detection switch, the sound effect 17 sounds and continues to sound until the abnormality is eliminated.

[0152]

According to the pachinko machine of the present invention, when the special symbol display device has reached the reach, the sub-control unit sends a control command corresponding to the reach to the speech synthesis circuit to the sound synthesizer circuit, thereby achieving the sound frequency. The contents of the setting register, the noise frequency setting register, the volume setting register, and the setting register having an area for setting start and stop of sound reproduction and an area for setting repetition are rewritten. Can be generated, and a more interesting sound effect can be generated.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko machine according to an embodiment.

FIG. 2 is a front view of the game board surface of the pachinko machine.

FIG. 3 is a front view showing an arrangement of various lamps and LEDs arranged on a game board.

FIG. 4 is an enlarged front view of the symbol display unit.

FIG. 5 is an enlarged front view of the accessory unit.

FIG. 6 is a rear view of the game board showing an arrangement of each detection switch.

FIG. 7 is a block diagram of a main control part of a control system provided in the pachinko machine according to the embodiment;

FIG. 8 is a block diagram of a lamp drive unit and an LED drive unit provided in the pachinko machine according to the embodiment;

FIG. 9 is a block diagram of a sub-control part of a control system provided in the pachinko machine according to the embodiment;

FIG. 10 is a block diagram showing the internal configuration of a voice synthesis control IC in the voice drive circuit.

FIG. 11 is a diagram showing a memory map showing a storage state of voice synthesis data stored in a performance data ROM of a voice synthesis control IC;

FIG. 12 shows ADPCM stored in a performance data ROM.
Diagram showing the structure of one sound of sound data

FIG. 13 is a diagram showing the contents of a setting register provided in a mix level controller of a voice synthesis control IC.

FIG. 14 is a diagram showing a configuration of one piece of music data stored in a performance data ROM.

FIG. 15 is a diagram showing a register map of a setting register provided in the first system of the sound source controller of the voice synthesis control IC;

FIG. 16 is a diagram showing a register map of a setting register provided in a second system of the sound source controller of the voice synthesis control IC;

FIG. 17 is a diagram showing contents of a setting register for setting a tone frequency provided in the tone generator controller;

FIG. 18 is a diagram showing contents of a setting register for setting a noise frequency provided in the sound source controller;

FIG. 19 is a diagram showing contents of a setting register for setting mixing of a musical sound and a noise provided in the tone generator controller.

FIG. 20 is a diagram showing the contents of a setting register provided for the sound source controller for setting a sound volume;

FIG. 21 is a diagram showing contents of a setting register for setting an envelope frequency provided in the sound source controller.

FIG. 22 is a view showing contents of a setting register for setting an envelope shape provided in the sound source controller;

FIG. 23 is a diagram showing contents of a setting register for setting a panpot provided in the sound source controller;

FIG. 24 is a diagram showing a register map of a setting register provided in the ADPCM controller of the voice synthesis control IC;

FIG. 25 is a diagram showing contents of a setting register provided for an ADPCM controller for setting a frequency and setting an ADPCM sound number;

FIG. 26 is a diagram showing the contents of a setting register provided for an ADPCM controller for setting a sound volume;

FIG. 27 is a diagram showing contents of a setting register for setting a panpot provided in the ADPCM controller;

FIG. 28 is a diagram showing the contents of a setting register provided for the reproduction start / stop setting and the repetitive reproduction setting provided in the ADPCM controller.

FIG. 29 is a diagram showing a register map of a setting register provided in the sequencer of the voice synthesis control IC.

FIG. 30 is a diagram showing the contents of setting registers provided for a sequencer to set performance start / stop, repeat performance, and music number.

FIG. 31 is a diagram showing contents of a setting register for setting a performance tempo provided in the sequencer;

FIG. 32 is a diagram showing contents of a setting register for setting channel occupancy of an ADPCM controller provided in a sequencer;

FIG. 33 is a diagram showing the contents of a setting register for setting the channel occupancy of the tone generator controller provided in the sequencer;

FIG. 34 is a diagram showing the correspondence between the operation state of the pachinko machine and the output display operation of the sound effect.

FIG. 35 is a diagram showing a correspondence relationship between an operation state of the pachinko machine and an output display operation of sound.

FIG. 36 is a diagram showing an operation trigger and an operation range of the type of sound effect.

FIG. 37 continued from FIG. 36;

FIG. 38 is a diagram showing an operation trigger and an operation range of a sound type;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pachinko machine 2 Pachinko machine main body 3 Card unit 4 Inner frame 5 Game board 6 Gold frame 7 Glass door 8 Upper tray 9 Lower tray 10 Hitting handle 11 Speaker 12 Frame decoration part 13 Key decoration part 14 Symbol display unit 15 Left gate 16 Right Gate 17 Starting winning port 18 Special prize unit 19 Windmill with lamp 20 Ordinary winning port 21 Ordinary winning port 22 Payout display section 23 Out of ball display section 24 Out port 25 Windmill 26 Inner rail 27 Outer rail 28 Rail decoration section 29 Electric tulip 30 Special Symbol display device 31 Frame 32 Overhang 33 Passage entrance 34 Ordinary symbol indicator 35 Memorized number display LED (for ordinary symbol) 36 Decorative member 37 Decorative member 38 Decorative member 39 Recess 40 Ball outlet 41 Memorized number LED (for special symbol) ) 42 guide member 43 notch 44 display 45 Design display part 46 Movie display part 47 Left design display part 48 Middle design display part 49 Right design display part 50 Big winning opening 51 Opening and closing door 52 Ordinary winning opening 53 Specific area 54 Taxiway 55 Taxiway 56 Taxiway 57 Taxiway 58 Assembly Gutter 59 Safe ball guiding gutter 60 Ordinary electric accessory opening solenoid 61 Large winning opening opening solenoid 62 Specific area door opening solenoid 63 Safe ball detection switch 64 Safe ball discharge solenoid 65 Main control unit 66 Switch detection circuit 67 Solenoid drive circuit 68 LED drive Circuit 69 Motor drive circuit 70 Lamp drive circuit 71 Lamp drive circuit 72 LED drive circuit 73 Information output circuit 74 Sub-control unit 75 LED drive circuit 76 Lamp drive circuit 77 Switch detection circuit 78 Sound drive circuit 79 Solenoid drive circuit 80 Prize ball discharge device 81 shots Shooting device 82 Card interface 83 Ball lending operation unit 84 Gold frame open detection switch 85 Supply ball out detection switch 86 Voice synthesis control IC 87 Amplifier 88 Amplifier 89 Voice reproduction means 90 Sound source controller 91 Sequencer 92 Sequencer 93 ADPCM controller 94 CPU interface 95 Performance data ROM 96 Electronic volume 97 Electronic volume 98 2-channel digital mixer 99 D / A converter 100 Mix level controller 101 Reset signal input unit 102 Clock frequency input unit A1 to A3 Frame decoration lamp B1 Key decoration lamp C1 Decoration lamp D1 Decoration lamp E1 Decorative lamp F1 Decorative lamp H1 to H3 Decorative LED J1 Decorative LED K1 Decorative LED M1 to M8 Decorative LED N1 to N8 Decorative LED 1 Payout LED P2 Ball out LED Q1 to Q2 Decoration LED SW1 Starting gate winning detection switch SW2 Left gate switch SW3 Right gate switch SW4 Special winning opening winning detection switch SW5 Specific area passing detection switch SW6 Winning detection switch MT For guiding member drive motor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04R 3/00 310 H04R 3/00 310

Claims (1)

[Claims] 1. A special symbol display device, a sub-control unit for controlling a sound effect output, and a voice synthesis circuit connected to the sub-control unit, wherein the voice synthesis circuit includes a sound frequency setting register. A register for noise frequency setting, a register for volume setting, and a setting register having an area for setting start and stop of sound reproduction and an area for setting repetition, and when the special symbol display device has reached a reach. A pachinko machine, wherein the sub-controller generates a different sound effect by sending a control command to the voice synthesizing circuit in accordance with a reach category.