ITTO920929A1 - Dispositivo a semiconduttore e procedimento per la sua fabbricazione - Google Patents
Dispositivo a semiconduttore e procedimento per la sua fabbricazioneInfo
- Publication number
- ITTO920929A1 ITTO920929A1 IT000929A ITTO920929A ITTO920929A1 IT TO920929 A1 ITTO920929 A1 IT TO920929A1 IT 000929 A IT000929 A IT 000929A IT TO920929 A ITTO920929 A IT TO920929A IT TO920929 A1 ITTO920929 A1 IT TO920929A1
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- manufacture
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3308946A JP2721607B2 (ja) | 1991-11-25 | 1991-11-25 | 半導体装置及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITTO920929A0 ITTO920929A0 (it) | 1992-11-17 |
ITTO920929A1 true ITTO920929A1 (it) | 1994-05-17 |
IT1258717B IT1258717B (it) | 1996-02-27 |
Family
ID=17987160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITTO920929A IT1258717B (it) | 1991-11-25 | 1992-11-17 | Dispositivo a semiconduttore e procedimento per la sua fabbricazione. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5489793A (it) |
JP (1) | JP2721607B2 (it) |
DE (1) | DE4239463C2 (it) |
IT (1) | IT1258717B (it) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09213943A (ja) * | 1996-01-29 | 1997-08-15 | Mitsubishi Electric Corp | パワーmosfetの製造方法 |
DE10209073A1 (de) * | 2002-02-28 | 2003-09-18 | Infineon Technologies Ag | Halbleiterchip, sowie Verfahren und Vorrichtung zur Herstellung des Halbleiterchips |
US6870206B2 (en) | 2001-11-27 | 2005-03-22 | Infineon Technologies Ag | Semiconductor chip, fabrication method, and device for fabricating a semiconductor chip |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5268376A (en) * | 1975-12-05 | 1977-06-07 | Nec Corp | Semiconductor device |
US4197632A (en) * | 1975-12-05 | 1980-04-15 | Nippon Electric Co., Ltd. | Semiconductor device |
US4144493A (en) * | 1976-06-30 | 1979-03-13 | International Business Machines Corporation | Integrated circuit test structure |
US4413271A (en) * | 1981-03-30 | 1983-11-01 | Sprague Electric Company | Integrated circuit including test portion and method for making |
DE3850790T2 (de) * | 1987-02-09 | 1994-12-22 | Fujitsu Ltd | Gatematrix mit in Verbindungsgebiet begrabenem Transistor. |
JP2776549B2 (ja) * | 1989-04-03 | 1998-07-16 | 日本電気アイシーマイコンシステム 株式会社 | 半導体集積回路 |
JPH03104169A (ja) * | 1989-09-18 | 1991-05-01 | Mitsubishi Electric Corp | 半導体装置 |
-
1991
- 1991-11-25 JP JP3308946A patent/JP2721607B2/ja not_active Expired - Lifetime
-
1992
- 1992-11-17 IT ITTO920929A patent/IT1258717B/it active IP Right Grant
- 1992-11-24 DE DE4239463A patent/DE4239463C2/de not_active Expired - Fee Related
-
1994
- 1994-07-08 US US08/272,285 patent/US5489793A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE4239463A1 (en) | 1993-05-27 |
ITTO920929A0 (it) | 1992-11-17 |
JP2721607B2 (ja) | 1998-03-04 |
IT1258717B (it) | 1996-02-27 |
US5489793A (en) | 1996-02-06 |
JPH05144906A (ja) | 1993-06-11 |
DE4239463C2 (de) | 1995-01-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19971129 |