ITRM20010104A0 - Modo di lettura a compressione di dati per il collaudo di memorie. - Google Patents

Modo di lettura a compressione di dati per il collaudo di memorie.

Info

Publication number
ITRM20010104A0
ITRM20010104A0 IT2001RM000104A ITRM20010104A ITRM20010104A0 IT RM20010104 A0 ITRM20010104 A0 IT RM20010104A0 IT 2001RM000104 A IT2001RM000104 A IT 2001RM000104A IT RM20010104 A ITRM20010104 A IT RM20010104A IT RM20010104 A0 ITRM20010104 A0 IT RM20010104A0
Authority
IT
Italy
Prior art keywords
data compression
reading mode
memory testing
compression reading
testing
Prior art date
Application number
IT2001RM000104A
Other languages
English (en)
Inventor
Giovanni Santin
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to IT2001RM000104A priority Critical patent/ITRM20010104A1/it
Publication of ITRM20010104A0 publication Critical patent/ITRM20010104A0/it
Priority to US09/943,642 priority patent/US6930936B2/en
Publication of ITRM20010104A1 publication Critical patent/ITRM20010104A1/it
Priority to US11/127,599 priority patent/US7113435B2/en
Priority to US11/430,339 priority patent/US7248516B2/en
Priority to US11/430,550 priority patent/US7180803B2/en
Priority to US11/430,549 priority patent/US7280420B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
IT2001RM000104A 2001-02-27 2001-02-27 Modo di lettura a compressione di dati per il collaudo di memorie. ITRM20010104A1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT2001RM000104A ITRM20010104A1 (it) 2001-02-27 2001-02-27 Modo di lettura a compressione di dati per il collaudo di memorie.
US09/943,642 US6930936B2 (en) 2001-02-27 2001-08-30 Data compression read mode for memory testing
US11/127,599 US7113435B2 (en) 2001-02-27 2005-05-12 Data compression read mode for memory testing
US11/430,339 US7248516B2 (en) 2001-02-27 2006-05-09 Data compression read mode for memory testing
US11/430,550 US7180803B2 (en) 2001-02-27 2006-05-09 Data compression read mode for memory testing
US11/430,549 US7280420B2 (en) 2001-02-27 2006-05-09 Data compression read mode for memory testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001RM000104A ITRM20010104A1 (it) 2001-02-27 2001-02-27 Modo di lettura a compressione di dati per il collaudo di memorie.

Publications (2)

Publication Number Publication Date
ITRM20010104A0 true ITRM20010104A0 (it) 2001-02-27
ITRM20010104A1 ITRM20010104A1 (it) 2002-08-27

Family

ID=11455275

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001RM000104A ITRM20010104A1 (it) 2001-02-27 2001-02-27 Modo di lettura a compressione di dati per il collaudo di memorie.

Country Status (2)

Country Link
US (5) US6930936B2 (it)
IT (1) ITRM20010104A1 (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20010104A1 (it) * 2001-02-27 2002-08-27 Micron Technology Inc Modo di lettura a compressione di dati per il collaudo di memorie.
DE10350356B3 (de) * 2003-10-29 2005-02-17 Infineon Technologies Ag Integrierte Schaltung, Testsystem und Verfahren zum Auslesen eines Fehlerdatums aus der integrierten Schaltung
ITRM20040418A1 (it) * 2004-08-25 2004-11-25 Micron Technology Inc Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.
US7644201B2 (en) * 2004-11-17 2010-01-05 International Business Machines Corporation Method and system for performance enhancement via transaction verification using a counter value in a polled data storage environment
US20070070740A1 (en) * 2005-09-28 2007-03-29 Hynix Semiconductor Inc. Semiconductor memory device having data-compress test mode
ITRM20060074A1 (it) 2006-02-15 2007-08-16 Micron Technology Inc Circuito per dati a latch singolo in un dispositivo di memoria volatile e delle a piu livelli
US7434124B2 (en) * 2006-03-28 2008-10-07 National Instruments Corporation Reduced pattern memory in digital test equipment
US7596729B2 (en) * 2006-06-30 2009-09-29 Micron Technology, Inc. Memory device testing system and method using compressed fail data
KR100771875B1 (ko) * 2006-07-10 2007-11-01 삼성전자주식회사 테스트하고자 하는 메모리 셀의 개수를 임의로 설정할 수있는 반도체 메모리 장치 및 반도체 메모리 장치의 테스트방법
US7508724B2 (en) * 2006-11-30 2009-03-24 Mosaid Technologies Incorporated Circuit and method for testing multi-device systems
TWI327732B (en) 2007-03-03 2010-07-21 Nanya Technology Corp Memory device and related testing method
KR100878307B1 (ko) * 2007-05-11 2009-01-14 주식회사 하이닉스반도체 멀티 워드라인 테스트 제어 회로 및 그의 제어 방법
KR100907927B1 (ko) * 2007-06-13 2009-07-16 주식회사 하이닉스반도체 반도체메모리소자 및 그의 구동방법
JP2009093709A (ja) * 2007-10-04 2009-04-30 Nec Electronics Corp 半導体集積回路及びテスト方法
US7913128B2 (en) 2007-11-23 2011-03-22 Mosaid Technologies Incorporated Data channel test apparatus and method thereof
TW201009704A (en) * 2008-08-20 2010-03-01 Incomm Technologies Co Ltd Memory card and non-volatile memory controller thereof
TWI370971B (en) * 2008-08-20 2012-08-21 Incomm Technologies Co Ltd Memory card and non-volatile memory controller thereof
KR101487190B1 (ko) * 2008-09-11 2015-01-28 삼성전자주식회사 압축 코덱을 구비한 플래시 메모리 집적 회로
KR101069677B1 (ko) * 2009-06-09 2011-10-04 주식회사 하이닉스반도체 반도체 메모리 장치 및 이를 위한 프로브 테스트 제어 회로
KR101069681B1 (ko) * 2009-07-30 2011-10-04 주식회사 하이닉스반도체 반도체 메모리 장치
KR101033490B1 (ko) * 2009-11-30 2011-05-09 주식회사 하이닉스반도체 패드를 선택적으로 이용하는 반도체 메모리 장치
KR101083675B1 (ko) * 2009-12-28 2011-11-16 주식회사 하이닉스반도체 데이터 압축 테스트 회로를 포함하는 반도체 메모리 장치
US8726104B2 (en) * 2011-07-28 2014-05-13 Sandisk Technologies Inc. Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages
US10949278B2 (en) * 2018-06-26 2021-03-16 Qualcomm Incorporated Early detection of execution errors
US20200119838A1 (en) * 2018-10-12 2020-04-16 Micron Technology, Inc. Adapting channel current

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872168A (en) * 1986-10-02 1989-10-03 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit with memory self-test
JPH05325598A (ja) * 1992-05-22 1993-12-10 Texas Instr Japan Ltd 半導体記憶装置
US5506959A (en) * 1994-08-04 1996-04-09 Telecommunication Research Laboratories Method and apparatus for testing electronic memories for the presence of multiple cell coupling faults
JPH0877797A (ja) * 1994-09-01 1996-03-22 Fujitsu Ltd 半導体記憶装置
JPH08180700A (ja) * 1994-12-28 1996-07-12 Nec Corp 半導体記憶装置とその試験方法
US5627786A (en) * 1995-02-10 1997-05-06 Micron Quantum Devices, Inc. Parallel processing redundancy scheme for faster access times and lower die area
US5535164A (en) * 1995-03-03 1996-07-09 International Business Machines Corporation BIST tester for multiple memories
US5563833A (en) * 1995-03-03 1996-10-08 International Business Machines Corporation Using one memory to supply addresses to an associated memory during testing
US5787097A (en) * 1996-07-22 1998-07-28 Micron Technology, Inc. Output data compression scheme for use in testing IC memories
KR100494281B1 (ko) * 1996-10-31 2005-08-05 텍사스 인스트루먼츠 인코포레이티드 전류-모드데이터압축테스트모드를갖는집적회로메모리장치및그테스트방법
US5966388A (en) * 1997-01-06 1999-10-12 Micron Technology, Inc. High-speed test system for a memory device
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US6032274A (en) * 1997-06-20 2000-02-29 Micron Technology, Inc. Method and apparatus for compressed data testing of more than one memory array
US6072737A (en) * 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
DE19906939C2 (de) * 1999-02-19 2002-09-19 Honsel Ag Induktionstiegelofen und dessen Verwendung zum Herstellen von Gußteilen aus partikelverstärkten Aluminium- und Magnesiumlegierungen
ITRM20010104A1 (it) * 2001-02-27 2002-08-27 Micron Technology Inc Modo di lettura a compressione di dati per il collaudo di memorie.

Also Published As

Publication number Publication date
US20020118580A1 (en) 2002-08-29
US7280420B2 (en) 2007-10-09
US7248516B2 (en) 2007-07-24
US20060221736A1 (en) 2006-10-05
US20060215470A1 (en) 2006-09-28
US20060221737A1 (en) 2006-10-05
ITRM20010104A1 (it) 2002-08-27
US7113435B2 (en) 2006-09-26
US20050213397A1 (en) 2005-09-29
US6930936B2 (en) 2005-08-16
US7180803B2 (en) 2007-02-20

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