ITRM20030040A0 - Modo di lettura a compressione di dati per collaudo di memorie. - Google Patents
Modo di lettura a compressione di dati per collaudo di memorie.Info
- Publication number
- ITRM20030040A0 ITRM20030040A0 IT2003RM000040A ITRM20030040A ITRM20030040A0 IT RM20030040 A0 ITRM20030040 A0 IT RM20030040A0 IT 2003RM000040 A IT2003RM000040 A IT 2003RM000040A IT RM20030040 A ITRM20030040 A IT RM20030040A IT RM20030040 A0 ITRM20030040 A0 IT RM20030040A0
- Authority
- IT
- Italy
- Prior art keywords
- data compression
- reading mode
- memory testing
- compression reading
- testing
- Prior art date
Links
- 238000013144 data compression Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000040A ITRM20030040A1 (it) | 2003-01-31 | 2003-01-31 | Modo di lettura a compressione di dati per collaudo di memorie. |
| US10/696,971 US7254756B2 (en) | 2003-01-31 | 2003-10-30 | Data compression read mode for memory testing |
| US11/780,734 US7657802B2 (en) | 2003-01-31 | 2007-07-20 | Data compression read mode for memory testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000040A ITRM20030040A1 (it) | 2003-01-31 | 2003-01-31 | Modo di lettura a compressione di dati per collaudo di memorie. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITRM20030040A0 true ITRM20030040A0 (it) | 2003-01-31 |
| ITRM20030040A1 ITRM20030040A1 (it) | 2004-08-01 |
Family
ID=29765638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT000040A ITRM20030040A1 (it) | 2003-01-31 | 2003-01-31 | Modo di lettura a compressione di dati per collaudo di memorie. |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US7254756B2 (it) |
| IT (1) | ITRM20030040A1 (it) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7596729B2 (en) * | 2006-06-30 | 2009-09-29 | Micron Technology, Inc. | Memory device testing system and method using compressed fail data |
| US9443615B2 (en) * | 2012-12-04 | 2016-09-13 | Micron Technology, Inc. | Methods and apparatuses for memory testing with data compression |
| US9183952B2 (en) * | 2013-02-20 | 2015-11-10 | Micron Technology, Inc. | Apparatuses and methods for compressing data received over multiple memory accesses |
| KR102336458B1 (ko) | 2015-07-30 | 2021-12-08 | 삼성전자주식회사 | 고속으로 결함 비트 라인을 검출하는 불휘발성 메모리 장치 및 그것의 테스트 시스템 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5535164A (en) * | 1995-03-03 | 1996-07-09 | International Business Machines Corporation | BIST tester for multiple memories |
| US5787097A (en) * | 1996-07-22 | 1998-07-28 | Micron Technology, Inc. | Output data compression scheme for use in testing IC memories |
| US5966388A (en) * | 1997-01-06 | 1999-10-12 | Micron Technology, Inc. | High-speed test system for a memory device |
| US6032274A (en) * | 1997-06-20 | 2000-02-29 | Micron Technology, Inc. | Method and apparatus for compressed data testing of more than one memory array |
| US6072737A (en) * | 1998-08-06 | 2000-06-06 | Micron Technology, Inc. | Method and apparatus for testing embedded DRAM |
| JP3495276B2 (ja) * | 1999-01-14 | 2004-02-09 | 日本電気株式会社 | 半導体記憶装置 |
| US6484289B1 (en) * | 1999-09-23 | 2002-11-19 | Texas Instruments Incorporated | Parallel data test for a semiconductor memory |
| JP2001243795A (ja) * | 1999-12-24 | 2001-09-07 | Nec Corp | 半導体記憶装置 |
-
2003
- 2003-01-31 IT IT000040A patent/ITRM20030040A1/it unknown
- 2003-10-30 US US10/696,971 patent/US7254756B2/en active Active
-
2007
- 2007-07-20 US US11/780,734 patent/US7657802B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US7254756B2 (en) | 2007-08-07 |
| US20040153599A1 (en) | 2004-08-05 |
| US7657802B2 (en) | 2010-02-02 |
| US20080016419A1 (en) | 2008-01-17 |
| ITRM20030040A1 (it) | 2004-08-01 |
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