IT967422B - Cella a tre linee per memoria a circuito integrato con accesso casuale - Google Patents

Cella a tre linee per memoria a circuito integrato con accesso casuale

Info

Publication number
IT967422B
IT967422B IT29148/72A IT2914872A IT967422B IT 967422 B IT967422 B IT 967422B IT 29148/72 A IT29148/72 A IT 29148/72A IT 2914872 A IT2914872 A IT 2914872A IT 967422 B IT967422 B IT 967422B
Authority
IT
Italy
Prior art keywords
integrated circuit
random access
circuit memory
line cell
cell
Prior art date
Application number
IT29148/72A
Other languages
English (en)
Italian (it)
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of IT967422B publication Critical patent/IT967422B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
IT29148/72A 1971-09-16 1972-09-13 Cella a tre linee per memoria a circuito integrato con accesso casuale IT967422B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US18098771A 1971-09-16 1971-09-16

Publications (1)

Publication Number Publication Date
IT967422B true IT967422B (it) 1974-02-28

Family

ID=22662423

Family Applications (1)

Application Number Title Priority Date Filing Date
IT29148/72A IT967422B (it) 1971-09-16 1972-09-13 Cella a tre linee per memoria a circuito integrato con accesso casuale

Country Status (8)

Country Link
US (1) US3706079A (fr)
JP (1) JPS5228538B2 (fr)
BE (1) BE788583A (fr)
DE (1) DE2242332C3 (fr)
FR (1) FR2152607B1 (fr)
GB (1) GB1338856A (fr)
IT (1) IT967422B (fr)
NL (1) NL7210911A (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3765000A (en) * 1971-11-03 1973-10-09 Honeywell Inf Systems Memory storage cell with single selection line and single input/output line
US3774177A (en) * 1972-10-16 1973-11-20 Ncr Co Nonvolatile random access memory cell using an alterable threshold field effect write transistor
US3859545A (en) * 1973-12-10 1975-01-07 Bell Telephone Labor Inc Low power dynamic control circuitry
US3882472A (en) * 1974-05-30 1975-05-06 Gen Instrument Corp Data flow control in memory having two device memory cells
DE2442131B2 (de) * 1974-09-03 1976-07-08 Siemens AG, 1000 Berlin und 8000 München Dynamisches ein-transistor-speicherelement
JPS63894A (ja) * 1986-06-20 1988-01-05 Hitachi Ltd メモリ
JPH0713872B2 (ja) * 1987-11-24 1995-02-15 三菱電機株式会社 半導体記憶装置
KR950008385B1 (ko) * 1990-05-24 1995-07-28 삼성전자주식회사 반도체 소자의 워드라인 형성방법
JP2824713B2 (ja) * 1992-04-24 1998-11-18 三菱電機株式会社 半導体記憶装置
US5657267A (en) * 1994-06-17 1997-08-12 The United States Of America As Represented By The Secretary Of The Air Force Dynamic RAM (random access memory) with SEU (single event upset) detection
US5526305A (en) * 1994-06-17 1996-06-11 The United States Of America As Represented By The Secretary Of The Air Force Two-transistor dynamic random-access memory cell
US6242772B1 (en) * 1994-12-12 2001-06-05 Altera Corporation Multi-sided capacitor in an integrated circuit
US6580454B1 (en) * 1998-11-18 2003-06-17 Agilent Technologies, Inc. CMOS active pixel sensor having in-pixel local exposure control
JP2001291389A (ja) 2000-03-31 2001-10-19 Hitachi Ltd 半導体集積回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585613A (en) * 1969-08-27 1971-06-15 Ibm Field effect transistor capacitor storage cell

Also Published As

Publication number Publication date
FR2152607A1 (fr) 1973-04-27
JPS4838946A (fr) 1973-06-08
US3706079A (en) 1972-12-12
DE2242332A1 (de) 1973-03-29
FR2152607B1 (fr) 1976-05-21
NL7210911A (fr) 1973-03-20
DE2242332B2 (de) 1975-03-13
BE788583A (fr) 1973-01-02
DE2242332C3 (de) 1975-11-13
GB1338856A (en) 1973-11-28
JPS5228538B2 (fr) 1977-07-27

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