IT1060668B - Circuito logico numerico per un registro dinamico di memoria - Google Patents

Circuito logico numerico per un registro dinamico di memoria

Info

Publication number
IT1060668B
IT1060668B IT7623486A IT2348676A IT1060668B IT 1060668 B IT1060668 B IT 1060668B IT 7623486 A IT7623486 A IT 7623486A IT 2348676 A IT2348676 A IT 2348676A IT 1060668 B IT1060668 B IT 1060668B
Authority
IT
Italy
Prior art keywords
logic circuit
dynamic memory
memory register
numerical logic
numerical
Prior art date
Application number
IT7623486A
Other languages
English (en)
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Application granted granted Critical
Publication of IT1060668B publication Critical patent/IT1060668B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Record Information Processing For Printing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
IT7623486A 1975-05-23 1976-05-21 Circuito logico numerico per un registro dinamico di memoria IT1060668B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/580,450 US4012721A (en) 1975-05-23 1975-05-23 Digital logic circuit for a dynamic buffer register

Publications (1)

Publication Number Publication Date
IT1060668B true IT1060668B (it) 1982-08-20

Family

ID=24321151

Family Applications (1)

Application Number Title Priority Date Filing Date
IT7623486A IT1060668B (it) 1975-05-23 1976-05-21 Circuito logico numerico per un registro dinamico di memoria

Country Status (9)

Country Link
US (1) US4012721A (it)
JP (1) JPS51147136A (it)
CA (1) CA1058711A (it)
DE (1) DE2622769A1 (it)
DK (1) DK228376A (it)
FR (1) FR2312073A1 (it)
GB (1) GB1545605A (it)
IT (1) IT1060668B (it)
SE (1) SE408240B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2443723A1 (fr) * 1978-12-06 1980-07-04 Cii Honeywell Bull Dispositif de reduction du temps d'acces aux informations contenues dans une memoire d'un systeme de traitement de l'information
US4829421A (en) * 1984-11-05 1989-05-09 S. C. Yuter, J.S.D. Data transfer regulating system for recording data at a varying recording

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2995729A (en) * 1956-02-16 1961-08-08 Digital Control Systems Inc Electronic digital inventory computer
US3116410A (en) * 1959-11-30 1963-12-31 Monroe Calculating Machine Simple general purpose digital computer
GB1103385A (en) * 1964-03-02 1968-02-14 Olivetti & Co Spa Improvements in or relating to program controlled electronic computers
FR1460650A (fr) * 1965-09-01 1966-03-04 Commissariat Energie Atomique Perfectionnements aux enregistreurs, analyseurs ou sélecteurs en temps, d'impulsions électriques pouvant se succéder à des intervalles extrêmement rapprochés
US3404377A (en) * 1965-10-01 1968-10-01 Stanley P. Frankel General purpose digital computer
US3439342A (en) * 1966-05-11 1969-04-15 Packard Instrument Co Inc Data organization system for multiparameter analyzers
US3651481A (en) * 1968-02-29 1972-03-21 Gen Electric Readout system for visually displaying stored data
US3781807A (en) * 1969-01-20 1973-12-25 Olivetti & Co Spa Stored program electronic computer using macroinstructions
US3623020A (en) * 1969-12-08 1971-11-23 Rca Corp First-in first-out buffer register
US3733588A (en) * 1971-05-17 1973-05-15 Zimmerman M Digital computer having a plurality of serial storage devices for central memory
US3750104A (en) * 1971-10-12 1973-07-31 Burroughs Corp Method and apparatus for synchronizing a dynamic recirculating shift register with asynchronously rotating memories
US3761894A (en) * 1972-05-12 1973-09-25 Bell Telephone Labor Inc Partitioned ramdom access memories for increasing throughput rate
US3883855A (en) * 1973-09-27 1975-05-13 Stromberg Carlson Corp Control system for a digital switching network

Also Published As

Publication number Publication date
DK228376A (da) 1976-11-24
SE408240B (sv) 1979-05-21
JPS51147136A (en) 1976-12-17
GB1545605A (en) 1979-05-10
US4012721A (en) 1977-03-15
CA1058711A (en) 1979-07-17
DE2622769A1 (de) 1976-12-02
SE7605658L (sv) 1976-11-24
FR2312073A1 (fr) 1976-12-17

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