IT956847B - Sistema di memoria perfezionato - Google Patents

Sistema di memoria perfezionato

Info

Publication number
IT956847B
IT956847B IT26240/72A IT2624072A IT956847B IT 956847 B IT956847 B IT 956847B IT 26240/72 A IT26240/72 A IT 26240/72A IT 2624072 A IT2624072 A IT 2624072A IT 956847 B IT956847 B IT 956847B
Authority
IT
Italy
Prior art keywords
memory system
improved memory
improved
memory
Prior art date
Application number
IT26240/72A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT956847B publication Critical patent/IT956847B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IT26240/72A 1971-06-30 1972-06-27 Sistema di memoria perfezionato IT956847B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15818071A 1971-06-30 1971-06-30

Publications (1)

Publication Number Publication Date
IT956847B true IT956847B (it) 1973-10-10

Family

ID=22566979

Family Applications (1)

Application Number Title Priority Date Filing Date
IT26240/72A IT956847B (it) 1971-06-30 1972-06-27 Sistema di memoria perfezionato

Country Status (7)

Country Link
US (1) US3761881A (it)
JP (1) JPS5136178B1 (it)
CA (1) CA960783A (it)
DE (1) DE2227882C2 (it)
FR (1) FR2144265A5 (it)
GB (1) GB1342459A (it)
IT (1) IT956847B (it)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764996A (en) * 1971-12-23 1973-10-09 Ibm Storage control and address translation
US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
US3825904A (en) * 1973-06-08 1974-07-23 Ibm Virtual memory system
US3866183A (en) * 1973-08-31 1975-02-11 Honeywell Inf Systems Communications control apparatus for the use with a cache store
FR130806A (it) * 1973-11-21
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
US3909798A (en) * 1974-01-25 1975-09-30 Raytheon Co Virtual addressing method and apparatus
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
JPS5615066B2 (it) * 1974-06-13 1981-04-08
DE2542845B2 (de) * 1975-09-25 1980-03-13 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Betreiben eines hierarchisch gegliederten, mehrstufigen Arbeitsspeichersystems und Schaltungsanordnung zur Durchführung des Verfahrens
DE2605617A1 (de) * 1976-02-12 1977-08-18 Siemens Ag Schaltungsanordnung zum adressieren von daten
JPS52130532A (en) * 1976-04-27 1977-11-01 Fujitsu Ltd Address conversion system
US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
US4241401A (en) * 1977-12-19 1980-12-23 Sperry Corporation Virtual address translator utilizing interrupt level code
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
DE2842288A1 (de) * 1978-09-28 1980-04-17 Siemens Ag Datentransferschalter mit assoziativer adressauswahl in einem virtuellen speicher
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
US4254463A (en) * 1978-12-14 1981-03-03 Rockwell International Corporation Data processing system with address translation
US4298932A (en) * 1979-06-11 1981-11-03 International Business Machines Corporation Serial storage subsystem for a data processor
DE2939411C2 (de) * 1979-09-28 1982-09-02 Siemens AG, 1000 Berlin und 8000 München Datenverarbeitungsanlage mit virtueller Speicheradressierung
JPS5687282A (en) * 1979-12-14 1981-07-15 Nec Corp Data processor
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
US4393443A (en) * 1980-05-20 1983-07-12 Tektronix, Inc. Memory mapping system
JPS5734251A (en) * 1980-08-07 1982-02-24 Toshiba Corp Address conversion and generating system
US4386402A (en) * 1980-09-25 1983-05-31 Bell Telephone Laboratories, Incorporated Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4482952A (en) * 1980-12-15 1984-11-13 Nippon Electric Co., Ltd. Virtual addressing system using page field comparisons to selectively validate cache buffer data on read main memory data
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
US4539637A (en) * 1982-08-26 1985-09-03 At&T Bell Laboratories Method and apparatus for handling interprocessor calls in a multiprocessor system
US4819154A (en) * 1982-12-09 1989-04-04 Sequoia Systems, Inc. Memory back up system with one cache memory and two physically separated main memories
AU569857B2 (en) * 1982-12-09 1988-02-25 Sequoia Systems, Inc. Memory backup system
JPS59157887A (ja) * 1983-02-28 1984-09-07 Hitachi Ltd 情報処理装置
DE3483489D1 (de) * 1983-04-13 1990-12-06 Nec Corp Speicherzugriffseinrichtung in einem datenverarbeitungssystem.
US4580217A (en) * 1983-06-22 1986-04-01 Ncr Corporation High speed memory management system and method
US4731739A (en) * 1983-08-29 1988-03-15 Amdahl Corporation Eviction control apparatus
US4680700A (en) * 1983-12-07 1987-07-14 International Business Machines Corporation Virtual memory address translation mechanism with combined hash address table and inverted page table
US4663742A (en) * 1984-10-30 1987-05-05 International Business Machines Corporation Directory memory system having simultaneous write, compare and bypass capabilites
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4821171A (en) * 1985-05-07 1989-04-11 Prime Computer, Inc. System of selective purging of address translation in computer memories
US4636990A (en) * 1985-05-31 1987-01-13 International Business Machines Corporation Three state select circuit for use in a data processing system or the like
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
WO1988006763A1 (en) * 1987-02-24 1988-09-07 Digital Equipment Corporation Central processor unit for digital data processing system including virtual to physical address translation circuit
JPH0221342A (ja) * 1987-02-27 1990-01-24 Hitachi Ltd マルチプロセッサシステム及びマルチプロセッサシステムにおける論理キャッシュメモリのアクセス方法
JP2507756B2 (ja) * 1987-10-05 1996-06-19 株式会社日立製作所 情報処理装置
JPH01154261A (ja) * 1987-12-11 1989-06-16 Toshiba Corp 情報処理装置
US5150471A (en) * 1989-04-20 1992-09-22 Ncr Corporation Method and apparatus for offset register address accessing
JPH0679296B2 (ja) * 1989-09-22 1994-10-05 株式会社日立製作所 多重仮想アドレス空間アクセス方法およびデータ処理装置
US5584003A (en) * 1990-03-29 1996-12-10 Matsushita Electric Industrial Co., Ltd. Control systems having an address conversion device for controlling a cache memory and a cache tag memory
US5193184A (en) * 1990-06-18 1993-03-09 Storage Technology Corporation Deleted data file space release system for a dynamically mapped virtual data storage subsystem
JP3190700B2 (ja) * 1991-05-31 2001-07-23 日本電気株式会社 アドレス変換装置
JPH10506483A (ja) * 1994-06-10 1998-06-23 テキサス・マイクロ・インコーポレーテッド フォールト・トレラントなコンピュータ・システムのためのメイン・メモリ・システム及びチェックポイント用プロトコル
US5890221A (en) * 1994-10-05 1999-03-30 International Business Machines Corporation Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit
JP3086779B2 (ja) * 1995-06-19 2000-09-11 株式会社東芝 メモリ状態復元装置
US5864657A (en) * 1995-11-29 1999-01-26 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system
US5751939A (en) * 1995-11-29 1998-05-12 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory
US5745672A (en) * 1995-11-29 1998-04-28 Texas Micro, Inc. Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
US5737514A (en) * 1995-11-29 1998-04-07 Texas Micro, Inc. Remote checkpoint memory system and protocol for fault-tolerant computer system
US5724551A (en) * 1996-05-23 1998-03-03 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage keys for controlling accesses to the buffers
TW379298B (en) * 1996-09-30 2000-01-11 Toshiba Corp Memory updating history saving device and memory updating history saving method
US6968398B2 (en) * 2001-08-15 2005-11-22 International Business Machines Corporation Method of virtualizing I/O resources in a computer system
US7604658B2 (en) * 2004-05-04 2009-10-20 Codman & Shurtleff, Inc. Multiple lumen sensor attachment

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB979633A (en) * 1960-04-20 1965-01-06 Nat Res Dev Improvements in or relating to electronic digital computing machines
DE1218761B (de) * 1963-07-19 1966-06-08 International Business Machines Corporation, Armonk, N. Y. (V. St. A.) Datenspeidbereinrichtung
US3339183A (en) * 1964-11-16 1967-08-29 Burroughs Corp Copy memory for a digital processor
US3568155A (en) * 1967-04-10 1971-03-02 Ibm Method of storing and retrieving records
US3533075A (en) * 1967-10-19 1970-10-06 Ibm Dynamic address translation unit with look-ahead
GB1265006A (it) * 1968-11-08 1972-03-01
GB1234484A (it) * 1968-11-12 1971-06-03
US3648254A (en) * 1969-12-31 1972-03-07 Ibm High-speed associative memory

Also Published As

Publication number Publication date
JPS5136178B1 (it) 1976-10-07
DE2227882C2 (de) 1982-11-04
US3761881A (en) 1973-09-25
CA960783A (en) 1975-01-07
GB1342459A (en) 1974-01-03
FR2144265A5 (it) 1973-02-09
DE2227882A1 (de) 1972-12-28

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