IT1010164B - Sistema di memoria perfezionato - Google Patents

Sistema di memoria perfezionato

Info

Publication number
IT1010164B
IT1010164B IT21995/74A IT2199574A IT1010164B IT 1010164 B IT1010164 B IT 1010164B IT 21995/74 A IT21995/74 A IT 21995/74A IT 2199574 A IT2199574 A IT 2199574A IT 1010164 B IT1010164 B IT 1010164B
Authority
IT
Italy
Prior art keywords
memory system
improved memory
improved
memory
Prior art date
Application number
IT21995/74A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1010164B publication Critical patent/IT1010164B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IT21995/74A 1973-06-04 1974-04-29 Sistema di memoria perfezionato IT1010164B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US367046A US3911401A (en) 1973-06-04 1973-06-04 Hierarchial memory/storage system for an electronic computer

Publications (1)

Publication Number Publication Date
IT1010164B true IT1010164B (it) 1977-01-10

Family

ID=23445718

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21995/74A IT1010164B (it) 1973-06-04 1974-04-29 Sistema di memoria perfezionato

Country Status (7)

Country Link
US (1) US3911401A (it)
JP (1) JPS5420294B2 (it)
CA (1) CA1000412A (it)
DE (1) DE2422732C2 (it)
FR (1) FR2232009B1 (it)
GB (1) GB1425804A (it)
IT (1) IT1010164B (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226124A (en) * 1975-08-22 1977-02-26 Fujitsu Ltd Buffer memory control unit
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4128882A (en) * 1976-08-19 1978-12-05 Massachusetts Institute Of Technology Packet memory system with hierarchical structure
US4084234A (en) * 1977-02-17 1978-04-11 Honeywell Information Systems Inc. Cache write capacity
US4399503A (en) * 1978-06-30 1983-08-16 Bunker Ramo Corporation Dynamic disk buffer control unit
CA1123964A (en) * 1978-10-26 1982-05-18 Anthony J. Capozzi Integrated multilevel storage hierarchy for a data processing system
US4467411A (en) * 1981-03-06 1984-08-21 International Business Machines Corporation Scheduling device operations in a buffered peripheral subsystem
US4458310A (en) * 1981-10-02 1984-07-03 At&T Bell Laboratories Cache memory using a lowest priority replacement circuit
JPS5862291A (ja) * 1981-10-07 1983-04-13 古河鉱業株式会社 坑道掘削方法および坑道掘削機
JPS6153988A (ja) * 1984-08-20 1986-03-18 鹿島建設株式会社 水噴射切削装置の移動装置
US4727486A (en) * 1986-05-02 1988-02-23 Honeywell Information Systems Inc. Hardware demand fetch cycle system interface
AU597363B2 (en) * 1987-05-22 1990-05-31 Honeywell Bull Inc. Present bit recycle and detect logic for a memory management unit
NL8800158A (nl) * 1988-01-25 1989-08-16 Philips Nv Computersysteem voorzien van een hierarchisch georganiseerd geheugen.
CA2055295C (en) * 1991-11-12 2000-05-23 Jean Gilles Fecteau Logical mapping of data objects using data spaces
US6378042B1 (en) * 1999-08-11 2002-04-23 Fast-Chip, Inc. Caching associative memory
US7855672B1 (en) * 2004-08-19 2010-12-21 Ixys Ch Gmbh Compressed codeset database format for remote control devices
US7484074B2 (en) * 2006-01-18 2009-01-27 International Business Machines Corporation Method and system for automatically distributing real memory between virtual memory page sizes

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573750A (en) * 1968-03-29 1971-04-06 Nippon Electric Co High-speed memory system
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3541529A (en) * 1969-09-22 1970-11-17 Ibm Replacement system
US3647348A (en) * 1970-01-19 1972-03-07 Fairchild Camera Instr Co Hardware-oriented paging control system
US3701107A (en) * 1970-10-01 1972-10-24 Rca Corp Computer with probability means to transfer pages from large memory to fast memory

Also Published As

Publication number Publication date
JPS5023537A (it) 1975-03-13
GB1425804A (en) 1976-02-18
FR2232009B1 (it) 1976-06-25
DE2422732C2 (de) 1983-02-17
CA1000412A (en) 1976-11-23
US3911401A (en) 1975-10-07
JPS5420294B2 (it) 1979-07-21
DE2422732A1 (de) 1975-01-02
FR2232009A1 (it) 1974-12-27

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