IT9020650A0 - metodo per conversione - Google Patents

metodo per conversione

Info

Publication number
IT9020650A0
IT9020650A0 IT9020650A IT2065090A IT9020650A0 IT 9020650 A0 IT9020650 A0 IT 9020650A0 IT 9020650 A IT9020650 A IT 9020650A IT 2065090 A IT2065090 A IT 2065090A IT 9020650 A0 IT9020650 A0 IT 9020650A0
Authority
IT
Italy
Prior art keywords
conversion method
conversion
Prior art date
Application number
IT9020650A
Other languages
English (en)
Other versions
IT9020650A1 (it
IT1248855B (it
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of IT9020650A0 publication Critical patent/IT9020650A0/it
Publication of IT9020650A1 publication Critical patent/IT9020650A1/it
Application granted granted Critical
Publication of IT1248855B publication Critical patent/IT1248855B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Transceivers (AREA)
IT02065090A 1990-05-04 1990-06-15 Metodo per conversione di modo di un dispositivo di memoria a due ingressi IT1248855B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900006350A KR920003269B1 (ko) 1990-05-04 1990-05-04 듀얼 포트 메모리소자의 모우드 전환방법

Publications (3)

Publication Number Publication Date
IT9020650A0 true IT9020650A0 (it) 1990-06-15
IT9020650A1 IT9020650A1 (it) 1991-12-15
IT1248855B IT1248855B (it) 1995-01-30

Family

ID=19298718

Family Applications (1)

Application Number Title Priority Date Filing Date
IT02065090A IT1248855B (it) 1990-05-04 1990-06-15 Metodo per conversione di modo di un dispositivo di memoria a due ingressi

Country Status (10)

Country Link
JP (1) JPH073747B2 (it)
KR (1) KR920003269B1 (it)
CN (1) CN1019238B (it)
DE (1) DE4021600C2 (it)
FR (1) FR2661770B1 (it)
GB (1) GB2243700B (it)
IT (1) IT1248855B (it)
NL (1) NL194899C (it)
RU (1) RU2109330C1 (it)
SE (1) SE512454C2 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1067477C (zh) * 1996-04-16 2001-06-20 联华电子股份有限公司 以串行编码方式进行芯片组间信号传输的装置
KR100773065B1 (ko) * 2006-09-12 2007-11-19 엠텍비젼 주식회사 듀얼 포트 메모리 장치, 메모리 장치 및 듀얼 포트 메모리장치 동작 방법
KR100773063B1 (ko) * 2006-09-12 2007-11-19 엠텍비젼 주식회사 듀얼 포트 메모리 장치, 메모리 장치 및 듀얼 포트 메모리장치 동작 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5589980A (en) * 1978-11-27 1980-07-08 Nec Corp Semiconductor memory unit
US4703449A (en) * 1983-02-28 1987-10-27 Data Translation Inc. Interrupt driven multi-buffer DMA circuit for enabling continuous sequential data transfers
SU1298754A1 (ru) * 1985-03-12 1987-03-23 Войсковая часть 03080 Устройство управлени распределением оперативной пам ти
SU1348860A1 (ru) * 1986-06-25 1987-10-30 Харьковский Институт Радиоэлектроники Им.Акад.М.К.Янгеля Устройство дл управлени пам тью видеоинформации
JPH073757B2 (ja) * 1987-02-25 1995-01-18 三菱電機株式会社 半導体記憶装置
US4817058A (en) * 1987-05-21 1989-03-28 Texas Instruments Incorporated Multiple input/output read/write memory having a multiple-cycle write mask
JPH0760594B2 (ja) * 1987-06-25 1995-06-28 富士通株式会社 半導体記憶装置
JP2793184B2 (ja) * 1987-07-27 1998-09-03 日本電気アイシーマイコンシステム株式会社 半導体記憶装置

Also Published As

Publication number Publication date
FR2661770B1 (fr) 1994-01-28
SE512454C2 (sv) 2000-03-20
RU2109330C1 (ru) 1998-04-20
NL194899B (nl) 2003-02-03
DE4021600C2 (de) 1994-04-07
NL9001613A (nl) 1991-12-02
KR910020557A (ko) 1991-12-20
IT9020650A1 (it) 1991-12-15
GB2243700B (en) 1994-02-02
GB2243700A (en) 1991-11-06
SE9002149L (sv) 1991-11-05
JPH0414695A (ja) 1992-01-20
IT1248855B (it) 1995-01-30
NL194899C (nl) 2003-06-04
CN1019238B (zh) 1992-11-25
GB9014079D0 (en) 1990-08-15
SE9002149D0 (sv) 1990-06-15
JPH073747B2 (ja) 1995-01-18
FR2661770A1 (fr) 1991-11-08
KR920003269B1 (ko) 1992-04-27
CN1056361A (zh) 1991-11-20
DE4021600A1 (de) 1991-11-07

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970625