IT9019902A0 - Stadio d'uscita dati,del tipo cosiddetto buffer,a ridotto rumore e per circuiti logici di tipo cmos - Google Patents

Stadio d'uscita dati,del tipo cosiddetto buffer,a ridotto rumore e per circuiti logici di tipo cmos

Info

Publication number
IT9019902A0
IT9019902A0 IT9019902A IT1990290A IT9019902A0 IT 9019902 A0 IT9019902 A0 IT 9019902A0 IT 9019902 A IT9019902 A IT 9019902A IT 1990290 A IT1990290 A IT 1990290A IT 9019902 A0 IT9019902 A0 IT 9019902A0
Authority
IT
Italy
Prior art keywords
data output
output stage
logic circuits
reduced noise
called buffer
Prior art date
Application number
IT9019902A
Other languages
English (en)
Other versions
IT9019902A1 (it
IT1239988B (it
Inventor
Marco Dallabora
Paolo Rolandi
Marco Maccalli
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT19902A priority Critical patent/IT1239988B/it
Publication of IT9019902A0 publication Critical patent/IT9019902A0/it
Priority to EP91104218A priority patent/EP0452684A1/en
Priority to JP3085966A priority patent/JPH0590941A/ja
Publication of IT9019902A1 publication Critical patent/IT9019902A1/it
Application granted granted Critical
Publication of IT1239988B publication Critical patent/IT1239988B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
IT19902A 1990-03-30 1990-03-30 Stadio d'uscita dati,del tipo cosiddetto buffer,a ridotto rumore e per circuiti logici di tipo cmos IT1239988B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT19902A IT1239988B (it) 1990-03-30 1990-03-30 Stadio d'uscita dati,del tipo cosiddetto buffer,a ridotto rumore e per circuiti logici di tipo cmos
EP91104218A EP0452684A1 (en) 1990-03-30 1991-03-19 A reduced noise, data output stage of the buffer type for logic circuits of the CMOS type
JP3085966A JPH0590941A (ja) 1990-03-30 1991-03-27 Ｃｍｏｓ論理回路用データ出力装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT19902A IT1239988B (it) 1990-03-30 1990-03-30 Stadio d'uscita dati,del tipo cosiddetto buffer,a ridotto rumore e per circuiti logici di tipo cmos

Publications (3)

Publication Number Publication Date
IT9019902A0 true IT9019902A0 (it) 1990-03-30
IT9019902A1 IT9019902A1 (it) 1991-09-30
IT1239988B IT1239988B (it) 1993-11-27

Family

ID=11162199

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19902A IT1239988B (it) 1990-03-30 1990-03-30 Stadio d'uscita dati,del tipo cosiddetto buffer,a ridotto rumore e per circuiti logici di tipo cmos

Country Status (3)

Country Link
EP (1) EP0452684A1 (it)
JP (1) JPH0590941A (it)
IT (1) IT1239988B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9224685D0 (en) * 1992-11-25 1993-01-13 Inmos Ltd Controlled impedance transistor switch circuit
FR2716758B1 (fr) * 1994-02-28 1996-05-31 Sgs Thomson Microelectronics Circuit de polarisation pour transistor dans une cellule de mémorisation.
GB2305082B (en) * 1995-09-06 1999-10-06 At & T Corp Wave shaping transmit circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900000830B1 (ko) * 1984-06-25 1990-02-17 후지쑤 가부시끼가이샤 상보형(相補型) Bi-MIS 게이트 회로
JPS635553A (ja) * 1986-06-25 1988-01-11 Fujitsu Ltd バツフア回路
JPS6382122A (ja) * 1986-09-26 1988-04-12 Toshiba Corp 論理回路
JPS63234623A (ja) * 1987-03-23 1988-09-29 Toshiba Corp 半導体集積回路

Also Published As

Publication number Publication date
EP0452684A1 (en) 1991-10-23
JPH0590941A (ja) 1993-04-09
IT9019902A1 (it) 1991-09-30
IT1239988B (it) 1993-11-27

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329