DE69232600D1 - Ausgangsschaltung mit Puffer - Google Patents

Ausgangsschaltung mit Puffer

Info

Publication number
DE69232600D1
DE69232600D1 DE69232600T DE69232600T DE69232600D1 DE 69232600 D1 DE69232600 D1 DE 69232600D1 DE 69232600 T DE69232600 T DE 69232600T DE 69232600 T DE69232600 T DE 69232600T DE 69232600 D1 DE69232600 D1 DE 69232600D1
Authority
DE
Germany
Prior art keywords
buffer
output circuit
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69232600T
Other languages
English (en)
Other versions
DE69232600T2 (de
Inventor
Yukihisa Orisaka
Junji Tanaka
Yoshiki Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69232600D1 publication Critical patent/DE69232600D1/de
Application granted granted Critical
Publication of DE69232600T2 publication Critical patent/DE69232600T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE69232600T 1991-10-14 1992-10-13 Ausgangsschaltung mit Puffer Expired - Lifetime DE69232600T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3295018A JP2761136B2 (ja) 1991-10-14 1991-10-14 出力回路

Publications (2)

Publication Number Publication Date
DE69232600D1 true DE69232600D1 (de) 2002-06-13
DE69232600T2 DE69232600T2 (de) 2002-11-07

Family

ID=17815270

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232600T Expired - Lifetime DE69232600T2 (de) 1991-10-14 1992-10-13 Ausgangsschaltung mit Puffer

Country Status (4)

Country Link
US (1) US5289063A (de)
EP (1) EP0537970B1 (de)
JP (1) JP2761136B2 (de)
DE (1) DE69232600T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417903B2 (en) * 2005-09-29 2008-08-26 Hynix Semiconductor Inc. Core voltage generator and method for generating core voltage in semiconductor memory device
JP4676507B2 (ja) * 2008-02-21 2011-04-27 Ｏｋｉセミコンダクタ株式会社 負荷容量の駆動回路
DE102010043484A1 (de) * 2010-11-05 2012-05-10 Robert Bosch Gmbh Vorrichtung und Verfahren zur seriellen Datenübertragung mit hoher Datenrate
US9385718B1 (en) 2013-10-18 2016-07-05 Altera Corporation Input-output buffer circuit with a gate bias generator

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3393325A (en) * 1965-07-26 1968-07-16 Gen Micro Electronics Inc High speed inverter
US3395291A (en) * 1965-09-07 1968-07-30 Gen Micro Electronics Inc Circuit employing a transistor as a load element
US3479523A (en) * 1966-09-26 1969-11-18 Ibm Integrated nor logic circuit
JPS59140725A (ja) * 1983-01-31 1984-08-13 Nec Corp 論理回路
US4642491A (en) * 1983-06-24 1987-02-10 International Business Machines Corporation Single transistor driver circuit
JPS63199507A (ja) * 1987-02-13 1988-08-18 Nec Corp 出力段回路
JP2619415B2 (ja) * 1987-09-24 1997-06-11 株式会社日立製作所 半導体論理回路
JPH0229115A (ja) * 1988-07-19 1990-01-31 Toshiba Corp 出力回路
JPH0777345B2 (ja) * 1988-11-04 1995-08-16 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
JP2761136B2 (ja) 1998-06-04
EP0537970A3 (en) 1993-08-18
EP0537970A2 (de) 1993-04-21
US5289063A (en) 1994-02-22
JPH05110406A (ja) 1993-04-30
DE69232600T2 (de) 2002-11-07
EP0537970B1 (de) 2002-05-08

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R071 Expiry of right

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