IT8720623A0 - Circuito di controllo di orologio per il controllo di fase. - Google Patents

Circuito di controllo di orologio per il controllo di fase.

Info

Publication number
IT8720623A0
IT8720623A0 IT8720623A IT2062387A IT8720623A0 IT 8720623 A0 IT8720623 A0 IT 8720623A0 IT 8720623 A IT8720623 A IT 8720623A IT 2062387 A IT2062387 A IT 2062387A IT 8720623 A0 IT8720623 A0 IT 8720623A0
Authority
IT
Italy
Prior art keywords
control circuit
clock
control
phase
phase control
Prior art date
Application number
IT8720623A
Other languages
English (en)
Other versions
IT1205668B (it
Inventor
Gary Joe Grimes
Christopher Lanzafame
Bryan Scott Moffitt
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Publication of IT8720623A0 publication Critical patent/IT8720623A0/it
Application granted granted Critical
Publication of IT1205668B publication Critical patent/IT1205668B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
IT20623/87A 1986-05-23 1987-05-21 Circuito di controllo di orologio per il controllo di fase IT1205668B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/866,374 US4672299A (en) 1986-05-23 1986-05-23 Clock control circuit for phase control

Publications (2)

Publication Number Publication Date
IT8720623A0 true IT8720623A0 (it) 1987-05-21
IT1205668B IT1205668B (it) 1989-03-31

Family

ID=25347473

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20623/87A IT1205668B (it) 1986-05-23 1987-05-21 Circuito di controllo di orologio per il controllo di fase

Country Status (5)

Country Link
US (1) US4672299A (it)
JP (1) JPS62286320A (it)
KR (1) KR870011522A (it)
CA (1) CA1270552A (it)
IT (1) IT1205668B (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4815109A (en) * 1987-06-25 1989-03-21 Racal Data Communications Inc. Sampling clock synchronization
JP2578817B2 (ja) * 1987-07-27 1997-02-05 日本電気株式会社 マイクロプロセツサ
FR2623042A1 (fr) * 1987-11-09 1989-05-12 Js Telecommunications Circuit de base de temps
JP2554705B2 (ja) * 1988-04-25 1996-11-13 三菱電機株式会社 位相同期回路
US4965524A (en) * 1988-06-09 1990-10-23 National Semiconductor Corp. Glitch free clock select
US4914404A (en) * 1988-08-02 1990-04-03 Siemens Aktiengesellschaft Method for synchronization of a signal frequency to interference-prone reference signal frequencies
FR2643205B1 (it) * 1989-02-16 1991-05-17 Telecommunications Sa
US5081705A (en) * 1989-06-29 1992-01-14 Rockwell International Corp. Communication system with external reference signal processing capability
US5065413A (en) * 1989-12-09 1991-11-12 Sony Corporation Phase locked loop circuit
JP2674295B2 (ja) * 1990-10-05 1997-11-12 日本電気株式会社 速度変換回路
EP0588050B1 (de) * 1992-08-18 1997-12-29 Siemens Aktiengesellschaft Anordnung zur Erzeugung eines Taktsignals mit bitgenauen Lücken
US5450458A (en) * 1994-08-05 1995-09-12 International Business Machines Corporation Method and apparatus for phase-aligned multiple frequency synthesizer with synchronization window decoder
DE4431415C2 (de) * 1994-08-24 1997-01-23 Deutsche Telephonwerk Kabel Verfahren zum Synchronisieren der Ausgangsfrequenzen eines Taktgenerators
SE504920C2 (sv) 1995-09-29 1997-05-26 Ericsson Telefon Ab L M Förfarande och system för redundant klockdistribution till telekommunikationsutrustningar i vilka byte av vald klocksignal bland de inkommande klocksignalerna ständigt sker
SE506739C2 (sv) 1995-09-29 1998-02-09 Ericsson Telefon Ab L M Drift och underhåll av klockdistributionsnät med redundans
SE505403C2 (sv) * 1995-11-30 1997-08-18 Ericsson Telefon Ab L M Förfarande för reducering av transienter i ett redundant klocksignalgenererande system
US6204732B1 (en) 1999-02-09 2001-03-20 Eci Telecom Ltd Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units
SE9901655L (sv) * 1999-05-06 2001-01-03 Net Insight Ab Synkroniseringsförfarande och -anordning
WO2000069106A1 (en) * 1999-05-06 2000-11-16 Net Insight Ab Synchronization method and apparatus
SE9901654L (sv) 1999-05-06 2001-01-03 Net Insight Ab Synkroniseringsförfarande och -anordning
US6675307B1 (en) * 2000-03-28 2004-01-06 Juniper Networks, Inc. Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal
US20010032323A1 (en) * 2000-04-06 2001-10-18 Konica Corporation Clock generating device
DE10023166A1 (de) * 2000-05-11 2001-11-15 Alcatel Sa Mehrrechner-System
JP2002055130A (ja) * 2000-08-14 2002-02-20 Nec Microsystems Ltd 周波数判定回路、データ処理装置
KR20090074412A (ko) * 2008-01-02 2009-07-07 삼성전자주식회사 분주회로 및 이를 이용한 위상 동기 루프

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414639A (en) * 1981-04-30 1983-11-08 Dranetz Engineering Laboratories, Inc. Sampling network analyzer with sampling synchronization by means of phase-locked loop
JPS58107715A (ja) * 1981-12-22 1983-06-27 Sony Corp 選局装置
US4464771A (en) * 1982-04-02 1984-08-07 Motorola, Inc. Phase-locked loop circuit arrangement
US4495473A (en) * 1982-07-19 1985-01-22 Rockwell International Corporation Digital phase shifting apparatus which compensates for change of frequency of an input signal to be phase shifted

Also Published As

Publication number Publication date
CA1270552A (en) 1990-06-19
IT1205668B (it) 1989-03-31
JPS62286320A (ja) 1987-12-12
US4672299A (en) 1987-06-09
KR870011522A (ko) 1987-12-24

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