IT8468199A0 - Circuito per la precarica di busper componenti integrati in tecnologia mos - Google Patents

Circuito per la precarica di busper componenti integrati in tecnologia mos

Info

Publication number
IT8468199A0
IT8468199A0 IT8468199A IT6819984A IT8468199A0 IT 8468199 A0 IT8468199 A0 IT 8468199A0 IT 8468199 A IT8468199 A IT 8468199A IT 6819984 A IT6819984 A IT 6819984A IT 8468199 A0 IT8468199 A0 IT 8468199A0
Authority
IT
Italy
Prior art keywords
busper
charging
circuit
components integrated
mos technology
Prior art date
Application number
IT8468199A
Other languages
English (en)
Other versions
IT1180149B (it
IT8468199A1 (it
Inventor
Marco Gandini
Guido Ghisio
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT68199/84A priority Critical patent/IT1180149B/it
Publication of IT8468199A0 publication Critical patent/IT8468199A0/it
Priority to JP60268410A priority patent/JPS61136318A/ja
Priority to EP85115264A priority patent/EP0188709A1/en
Publication of IT8468199A1 publication Critical patent/IT8468199A1/it
Application granted granted Critical
Publication of IT1180149B publication Critical patent/IT1180149B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
IT68199/84A 1984-12-04 1984-12-04 Circuito per la precarica di bus per componenti integrati in tecnologia mos IT1180149B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT68199/84A IT1180149B (it) 1984-12-04 1984-12-04 Circuito per la precarica di bus per componenti integrati in tecnologia mos
JP60268410A JPS61136318A (ja) 1984-12-04 1985-11-30 Ｍｏｓ集積部品用バス予備充電回路
EP85115264A EP0188709A1 (en) 1984-12-04 1985-12-02 Bus-precharge circuit for MOS integrated components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT68199/84A IT1180149B (it) 1984-12-04 1984-12-04 Circuito per la precarica di bus per componenti integrati in tecnologia mos

Publications (3)

Publication Number Publication Date
IT8468199A0 true IT8468199A0 (it) 1984-12-04
IT8468199A1 IT8468199A1 (it) 1986-06-04
IT1180149B IT1180149B (it) 1987-09-23

Family

ID=11308449

Family Applications (1)

Application Number Title Priority Date Filing Date
IT68199/84A IT1180149B (it) 1984-12-04 1984-12-04 Circuito per la precarica di bus per componenti integrati in tecnologia mos

Country Status (3)

Country Link
EP (1) EP0188709A1 (it)
JP (1) JPS61136318A (it)
IT (1) IT1180149B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003100974A2 (en) * 2002-05-28 2003-12-04 Igor Anatolievich Abrosimov Pull up for high speed structures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522156A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Push-pull buffer circuit
JPS53102660A (en) * 1977-02-21 1978-09-07 Hitachi Ltd Push pull buffer circuit
US4489246A (en) * 1980-12-24 1984-12-18 Fujitsu Limited Field effect transistor logic circuit having high operating speed and low power consumption
JPS5970022A (ja) * 1982-10-13 1984-04-20 Mitsubishi Electric Corp ダイナミツク型半導体装置

Also Published As

Publication number Publication date
IT1180149B (it) 1987-09-23
JPS61136318A (ja) 1986-06-24
IT8468199A1 (it) 1986-06-04
EP0188709A1 (en) 1986-07-30

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