IT8423283A0 - Processo planox a becco ridotto per la formazione di componenti elettronici integrati. - Google Patents

Processo planox a becco ridotto per la formazione di componenti elettronici integrati.

Info

Publication number
IT8423283A0
IT8423283A0 IT8423283A IT2328384A IT8423283A0 IT 8423283 A0 IT8423283 A0 IT 8423283A0 IT 8423283 A IT8423283 A IT 8423283A IT 2328384 A IT2328384 A IT 2328384A IT 8423283 A0 IT8423283 A0 IT 8423283A0
Authority
IT
Italy
Prior art keywords
formation
electronic components
integrated electronic
reduced nose
planox
Prior art date
Application number
IT8423283A
Other languages
English (en)
Other versions
IT1213230B (it
Inventor
Livio Baldi
Daniela Beardo
Marco Icardi
Adriana Rebora
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8423283A priority Critical patent/IT1213230B/it
Publication of IT8423283A0 publication Critical patent/IT8423283A0/it
Priority to GB08524041A priority patent/GB2165992B/en
Priority to NL8502733A priority patent/NL193393C/nl
Priority to DE3537047A priority patent/DE3537047C2/de
Priority to JP60234661A priority patent/JPS61101047A/ja
Priority to FR858515760A priority patent/FR2572217B1/fr
Priority to US07/124,440 priority patent/US4897365A/en
Application granted granted Critical
Publication of IT1213230B publication Critical patent/IT1213230B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
IT8423283A 1984-10-23 1984-10-23 Processo planox a becco ridotto per la formazione di componenti elettronici integrati. IT1213230B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8423283A IT1213230B (it) 1984-10-23 1984-10-23 Processo planox a becco ridotto per la formazione di componenti elettronici integrati.
GB08524041A GB2165992B (en) 1984-10-23 1985-09-30 Reduced-beak planox process for the formation of integrated electronic components
NL8502733A NL193393C (nl) 1984-10-23 1985-10-07 Werkwijze voor de vervaardiging van een halfgeleiderinrichting.
DE3537047A DE3537047C2 (de) 1984-10-23 1985-10-17 Verfahren zur lokalen Oxidation von Silizium
JP60234661A JPS61101047A (ja) 1984-10-23 1985-10-22 集積電子構成要素を形成するためのビーク部の形成が低減されたプラノツクス法
FR858515760A FR2572217B1 (fr) 1984-10-23 1985-10-23 Procede planox a bec reduit pour la formation de composants electroniques integres
US07/124,440 US4897365A (en) 1984-10-23 1987-11-23 Reduced-beak planox process for the formation of integrated electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8423283A IT1213230B (it) 1984-10-23 1984-10-23 Processo planox a becco ridotto per la formazione di componenti elettronici integrati.

Publications (2)

Publication Number Publication Date
IT8423283A0 true IT8423283A0 (it) 1984-10-23
IT1213230B IT1213230B (it) 1989-12-14

Family

ID=11205638

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8423283A IT1213230B (it) 1984-10-23 1984-10-23 Processo planox a becco ridotto per la formazione di componenti elettronici integrati.

Country Status (7)

Country Link
US (1) US4897365A (it)
JP (1) JPS61101047A (it)
DE (1) DE3537047C2 (it)
FR (1) FR2572217B1 (it)
GB (1) GB2165992B (it)
IT (1) IT1213230B (it)
NL (1) NL193393C (it)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
WO1996016437A1 (en) * 1994-11-18 1996-05-30 Advanced Micro Devices, Inc. Silicon nitride etch process with critical dimension gain
US5983828A (en) * 1995-10-13 1999-11-16 Mattson Technology, Inc. Apparatus and method for pulsed plasma processing of a semiconductor substrate
US6794301B2 (en) 1995-10-13 2004-09-21 Mattson Technology, Inc. Pulsed plasma processing of semiconductor substrates
US6253704B1 (en) 1995-10-13 2001-07-03 Mattson Technology, Inc. Apparatus and method for pulsed plasma processing of a semiconductor substrate
US5861339A (en) * 1995-10-27 1999-01-19 Integrated Device Technology, Inc. Recessed isolation with double oxidation
US5882993A (en) 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
KR19980064466A (ko) * 1996-12-23 1998-10-07 윌리엄비.켐플러 이산화탄소로 실리콘 산화물을 에칭하는 공정
US5926730A (en) * 1997-02-19 1999-07-20 Micron Technology, Inc. Conductor layer nitridation
US5962914A (en) * 1998-01-14 1999-10-05 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
JPH11214355A (ja) * 1998-01-20 1999-08-06 Nec Corp 異方性ドライエッチング方法
US6531364B1 (en) 1998-08-05 2003-03-11 Advanced Micro Devices, Inc. Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer
US20050287916A1 (en) * 2004-01-23 2005-12-29 Sheltman David A Pneumatically actuated stunt device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080718A (en) * 1976-12-14 1978-03-28 Smc Standard Microsystems Corporation Method of modifying electrical characteristics of MOS devices using ion implantation
US4283249A (en) * 1979-05-02 1981-08-11 International Business Machines Corporation Reactive ion etching
JPS5691446A (en) * 1979-12-25 1981-07-24 Seiko Epson Corp Forming of element segregation region of semiconductor integrated circuit
JPS56114319A (en) * 1980-02-14 1981-09-08 Fujitsu Ltd Method for forming contact hole
EP0040081B1 (en) * 1980-05-12 1984-09-12 Fujitsu Limited Method and apparatus for plasma etching
JPS56158873A (en) * 1980-05-14 1981-12-07 Hitachi Ltd Dry etching method
US4324611A (en) * 1980-06-26 1982-04-13 Branson International Plasma Corporation Process and gas mixture for etching silicon dioxide and silicon nitride
NL8004005A (nl) * 1980-07-11 1982-02-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
JPS5775429A (en) * 1980-10-28 1982-05-12 Toshiba Corp Manufacture of semiconductor device
US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4376672A (en) * 1981-10-26 1983-03-15 Applied Materials, Inc. Materials and methods for plasma etching of oxides and nitrides of silicon
US4563227A (en) * 1981-12-08 1986-01-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing a semiconductor device
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4551910A (en) * 1984-11-27 1985-11-12 Intel Corporation MOS Isolation processing

Also Published As

Publication number Publication date
FR2572217B1 (fr) 1990-03-30
GB8524041D0 (en) 1985-11-06
US4897365A (en) 1990-01-30
GB2165992B (en) 1988-11-09
GB2165992A (en) 1986-04-23
DE3537047A1 (de) 1986-04-24
IT1213230B (it) 1989-12-14
NL193393C (nl) 1999-08-03
JPS61101047A (ja) 1986-05-19
NL8502733A (nl) 1986-05-16
FR2572217A1 (fr) 1986-04-25
NL193393B (nl) 1999-04-01
DE3537047C2 (de) 1995-06-01

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Effective date: 19971030