IT8123736A0 - Metodo per fare circuiti integrati. - Google Patents

Metodo per fare circuiti integrati.

Info

Publication number
IT8123736A0
IT8123736A0 IT8123736A IT2373681A IT8123736A0 IT 8123736 A0 IT8123736 A0 IT 8123736A0 IT 8123736 A IT8123736 A IT 8123736A IT 2373681 A IT2373681 A IT 2373681A IT 8123736 A0 IT8123736 A0 IT 8123736A0
Authority
IT
Italy
Prior art keywords
integrated circuits
making integrated
making
circuits
integrated
Prior art date
Application number
IT8123736A
Other languages
English (en)
Other versions
IT1138548B (it
Inventor
Tat-Sing Paul Chow
Mario Ghezzo
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of IT8123736A0 publication Critical patent/IT8123736A0/it
Application granted granted Critical
Publication of IT1138548B publication Critical patent/IT1138548B/it

Links

Classifications

    • H10P50/691—
    • H10P14/61—
    • H10P50/692—
    • H10W10/0121—
    • H10W10/13—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/086—Isolated zones
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
IT23736/81A 1980-09-15 1981-09-02 Metodo per fare circuiti integrati IT1138548B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/187,501 US4333965A (en) 1980-09-15 1980-09-15 Method of making integrated circuits

Publications (2)

Publication Number Publication Date
IT8123736A0 true IT8123736A0 (it) 1981-09-02
IT1138548B IT1138548B (it) 1986-09-17

Family

ID=22689247

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23736/81A IT1138548B (it) 1980-09-15 1981-09-02 Metodo per fare circuiti integrati

Country Status (6)

Country Link
US (1) US4333965A (it)
JP (1) JPS5780743A (it)
DE (1) DE3136009A1 (it)
FR (1) FR2490403B1 (it)
GB (1) GB2083947B (it)
IT (1) IT1138548B (it)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1165014A (en) * 1981-04-13 1984-04-03 Kei Kurosawa Method for manufacturing semiconductor device
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
US4390393A (en) * 1981-11-12 1983-06-28 General Electric Company Method of forming an isolation trench in a semiconductor substrate
US4361600A (en) * 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
US4429011A (en) 1982-03-29 1984-01-31 General Electric Company Composite conductive structures and method of making same
JPS58173870A (ja) * 1982-04-05 1983-10-12 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 半導体装置の製造方法
US4587540A (en) * 1982-04-05 1986-05-06 International Business Machines Corporation Vertical MESFET with mesa step defining gate length
US4398992A (en) * 1982-05-20 1983-08-16 Hewlett-Packard Company Defect free zero oxide encroachment process for semiconductor fabrication
CA1204525A (en) * 1982-11-29 1986-05-13 Tetsu Fukano Method for forming an isolation region for electrically isolating elements
JPS59132141A (ja) * 1983-01-17 1984-07-30 Mitsubishi Electric Corp 半導体装置の製造方法
JPS59214237A (ja) * 1983-05-20 1984-12-04 Toshiba Corp 半導体装置の製造方法
US4604162A (en) * 1983-06-13 1986-08-05 Ncr Corporation Formation and planarization of silicon-on-insulator structures
US4583281A (en) * 1985-03-13 1986-04-22 General Electric Company Method of making an integrated circuit
US4646424A (en) * 1985-08-02 1987-03-03 General Electric Company Deposition and hardening of titanium gate electrode material for use in inverted thin film field effect transistors
US4909897A (en) * 1986-06-17 1990-03-20 Plessey Overseas Limited Local oxidation of silicon process
US4862232A (en) * 1986-09-22 1989-08-29 General Motors Corporation Transistor structure for high temperature logic circuits with insulation around source and drain regions
US4797718A (en) * 1986-12-08 1989-01-10 Delco Electronics Corporation Self-aligned silicon MOS device
US4714685A (en) * 1986-12-08 1987-12-22 General Motors Corporation Method of fabricating self-aligned silicon-on-insulator like devices
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US4903107A (en) * 1986-12-29 1990-02-20 General Electric Company Buried oxide field isolation structure with composite dielectric
US4714518A (en) * 1987-01-14 1987-12-22 Polaroid Corporation Dual layer encapsulation coating for III-V semiconductor compounds
DE3884151T2 (de) * 1987-06-15 1994-04-07 Ncr Int Inc Verfahren zur herstellung eines halbleiterfeldoxids.
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
US4923563A (en) * 1987-06-15 1990-05-08 Ncr Corporation Semiconductor field oxide formation process using a sealing sidewall of consumable nitride
US4942449A (en) * 1988-03-28 1990-07-17 General Electric Company Fabrication method and structure for field isolation in field effect transistors on integrated circuit chips
NL8800903A (nl) * 1988-04-08 1989-11-01 Koninkl Philips Electronics Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden.
US7666735B1 (en) * 2005-02-10 2010-02-23 Advanced Micro Devices, Inc. Method for forming semiconductor devices with active silicon height variation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US4110125A (en) * 1977-03-03 1978-08-29 International Business Machines Corporation Method for fabricating semiconductor devices
JPS5494196A (en) * 1977-12-30 1979-07-25 Ibm Metallic layer removing method

Also Published As

Publication number Publication date
FR2490403A1 (fr) 1982-03-19
DE3136009A1 (de) 1982-04-15
GB2083947A (en) 1982-03-31
JPS5780743A (en) 1982-05-20
US4333965A (en) 1982-06-08
FR2490403B1 (fr) 1987-02-27
IT1138548B (it) 1986-09-17
GB2083947B (en) 1984-07-25

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