IT1138548B - Metodo per fare circuiti integrati - Google Patents

Metodo per fare circuiti integrati

Info

Publication number
IT1138548B
IT1138548B IT23736/81A IT2373681A IT1138548B IT 1138548 B IT1138548 B IT 1138548B IT 23736/81 A IT23736/81 A IT 23736/81A IT 2373681 A IT2373681 A IT 2373681A IT 1138548 B IT1138548 B IT 1138548B
Authority
IT
Italy
Prior art keywords
integrated circuits
making integrated
making
circuits
integrated
Prior art date
Application number
IT23736/81A
Other languages
English (en)
Other versions
IT8123736A0 (it
Inventor
Paul Chow Tat-Sing
Ghezzo Mario
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of IT8123736A0 publication Critical patent/IT8123736A0/it
Application granted granted Critical
Publication of IT1138548B publication Critical patent/IT1138548B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/086Isolated zones
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/114Nitrides of silicon
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/117Oxidation, selective

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
IT23736/81A 1980-09-15 1981-09-02 Metodo per fare circuiti integrati IT1138548B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/187,501 US4333965A (en) 1980-09-15 1980-09-15 Method of making integrated circuits

Publications (2)

Publication Number Publication Date
IT8123736A0 IT8123736A0 (it) 1981-09-02
IT1138548B true IT1138548B (it) 1986-09-17

Family

ID=22689247

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23736/81A IT1138548B (it) 1980-09-15 1981-09-02 Metodo per fare circuiti integrati

Country Status (6)

Country Link
US (1) US4333965A (it)
JP (1) JPS5780743A (it)
DE (1) DE3136009A1 (it)
FR (1) FR2490403B1 (it)
GB (1) GB2083947B (it)
IT (1) IT1138548B (it)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1165014A (en) * 1981-04-13 1984-04-03 Kei Kurosawa Method for manufacturing semiconductor device
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
US4390393A (en) * 1981-11-12 1983-06-28 General Electric Company Method of forming an isolation trench in a semiconductor substrate
US4361600A (en) * 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
JPS58173870A (ja) * 1982-04-05 1983-10-12 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン 半導体装置の製造方法
US4587540A (en) * 1982-04-05 1986-05-06 International Business Machines Corporation Vertical MESFET with mesa step defining gate length
US4398992A (en) * 1982-05-20 1983-08-16 Hewlett-Packard Company Defect free zero oxide encroachment process for semiconductor fabrication
CA1204525A (en) * 1982-11-29 1986-05-13 Tetsu Fukano Method for forming an isolation region for electrically isolating elements
JPS59132141A (ja) * 1983-01-17 1984-07-30 Mitsubishi Electric Corp 半導体装置の製造方法
JPS59214237A (ja) * 1983-05-20 1984-12-04 Toshiba Corp 半導体装置の製造方法
US4604162A (en) * 1983-06-13 1986-08-05 Ncr Corporation Formation and planarization of silicon-on-insulator structures
US4583281A (en) * 1985-03-13 1986-04-22 General Electric Company Method of making an integrated circuit
US4646424A (en) * 1985-08-02 1987-03-03 General Electric Company Deposition and hardening of titanium gate electrode material for use in inverted thin film field effect transistors
US4909897A (en) * 1986-06-17 1990-03-20 Plessey Overseas Limited Local oxidation of silicon process
US4862232A (en) * 1986-09-22 1989-08-29 General Motors Corporation Transistor structure for high temperature logic circuits with insulation around source and drain regions
US4797718A (en) * 1986-12-08 1989-01-10 Delco Electronics Corporation Self-aligned silicon MOS device
US4714685A (en) * 1986-12-08 1987-12-22 General Motors Corporation Method of fabricating self-aligned silicon-on-insulator like devices
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US4903107A (en) * 1986-12-29 1990-02-20 General Electric Company Buried oxide field isolation structure with composite dielectric
US4714518A (en) * 1987-01-14 1987-12-22 Polaroid Corporation Dual layer encapsulation coating for III-V semiconductor compounds
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
US4923563A (en) * 1987-06-15 1990-05-08 Ncr Corporation Semiconductor field oxide formation process using a sealing sidewall of consumable nitride
JP2747563B2 (ja) * 1987-06-15 1998-05-06 ヒュンダイ エレクトロニクス アメリカ 半導体のフイールド酸化物形成方法
US4942449A (en) * 1988-03-28 1990-07-17 General Electric Company Fabrication method and structure for field isolation in field effect transistors on integrated circuit chips
NL8800903A (nl) * 1988-04-08 1989-11-01 Koninkl Philips Electronics Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumsubstraat met geheel of gedeeltelijk verzonken veldoxide-gebieden.
US7666735B1 (en) 2005-02-10 2010-02-23 Advanced Micro Devices, Inc. Method for forming semiconductor devices with active silicon height variation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US4110125A (en) * 1977-03-03 1978-08-29 International Business Machines Corporation Method for fabricating semiconductor devices
JPS5494196A (en) * 1977-12-30 1979-07-25 Ibm Metallic layer removing method

Also Published As

Publication number Publication date
JPS5780743A (en) 1982-05-20
FR2490403A1 (fr) 1982-03-19
DE3136009A1 (de) 1982-04-15
GB2083947A (en) 1982-03-31
FR2490403B1 (fr) 1987-02-27
US4333965A (en) 1982-06-08
IT8123736A0 (it) 1981-09-02
GB2083947B (en) 1984-07-25

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