IT7820203A0 - Procedimento per l'iscrizione di un transistor memorizzatore comprendente un doppio strato di dielettrico di porta. - Google Patents

Procedimento per l'iscrizione di un transistor memorizzatore comprendente un doppio strato di dielettrico di porta.

Info

Publication number
IT7820203A0
IT7820203A0 IT7820203A IT2020378A IT7820203A0 IT 7820203 A0 IT7820203 A0 IT 7820203A0 IT 7820203 A IT7820203 A IT 7820203A IT 2020378 A IT2020378 A IT 2020378A IT 7820203 A0 IT7820203 A0 IT 7820203A0
Authority
IT
Italy
Prior art keywords
entering
procedure
gate dielectric
double layer
transistor including
Prior art date
Application number
IT7820203A
Other languages
English (en)
Other versions
IT1092733B (it
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Publication of IT7820203A0 publication Critical patent/IT7820203A0/it
Application granted granted Critical
Publication of IT1092733B publication Critical patent/IT1092733B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
IT20203/78A 1977-02-25 1978-02-13 Procedimento per l'iscrizione di un trasnsistor memorizzatore comprendente un doppio strato di dielettrico di porta IT1092733B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772708101 DE2708101A1 (de) 1977-02-25 1977-02-25 Verfahren zum schreiben eines speichertransistors mit gate-isolierdoppelschicht

Publications (2)

Publication Number Publication Date
IT7820203A0 true IT7820203A0 (it) 1978-02-13
IT1092733B IT1092733B (it) 1985-07-12

Family

ID=6002106

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20203/78A IT1092733B (it) 1977-02-25 1978-02-13 Procedimento per l'iscrizione di un trasnsistor memorizzatore comprendente un doppio strato di dielettrico di porta

Country Status (5)

Country Link
JP (1) JPS53106583A (it)
DE (1) DE2708101A1 (it)
FR (1) FR2382074A1 (it)
GB (1) GB1545880A (it)
IT (1) IT1092733B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456978A (en) * 1980-02-12 1984-06-26 General Instrument Corp. Electrically alterable read only memory semiconductor device made by low pressure chemical vapor deposition process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES404184A1 (es) * 1971-07-06 1975-06-01 Ibm Una disposicion de celula de memoria de acceso casual para calculadoras digitales.
US3882469A (en) * 1971-11-30 1975-05-06 Texas Instruments Inc Non-volatile variable threshold memory cell

Also Published As

Publication number Publication date
DE2708101A1 (de) 1978-08-31
IT1092733B (it) 1985-07-12
JPS53106583A (en) 1978-09-16
FR2382074A1 (fr) 1978-09-22
GB1545880A (en) 1979-05-16

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