JPS53106583A - Method of writing memory transistor of gate induction double layer - Google Patents

Method of writing memory transistor of gate induction double layer

Info

Publication number
JPS53106583A
JPS53106583A JP2082678A JP2082678A JPS53106583A JP S53106583 A JPS53106583 A JP S53106583A JP 2082678 A JP2082678 A JP 2082678A JP 2082678 A JP2082678 A JP 2082678A JP S53106583 A JPS53106583 A JP S53106583A
Authority
JP
Japan
Prior art keywords
double layer
memory transistor
writing memory
gate induction
induction double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2082678A
Other languages
English (en)
Japanese (ja)
Inventor
Birumusumeiyaa Kurausu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of JPS53106583A publication Critical patent/JPS53106583A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP2082678A 1977-02-25 1978-02-24 Method of writing memory transistor of gate induction double layer Pending JPS53106583A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772708101 DE2708101A1 (de) 1977-02-25 1977-02-25 Verfahren zum schreiben eines speichertransistors mit gate-isolierdoppelschicht

Publications (1)

Publication Number Publication Date
JPS53106583A true JPS53106583A (en) 1978-09-16

Family

ID=6002106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2082678A Pending JPS53106583A (en) 1977-02-25 1978-02-24 Method of writing memory transistor of gate induction double layer

Country Status (5)

Country Link
JP (1) JPS53106583A (it)
DE (1) DE2708101A1 (it)
FR (1) FR2382074A1 (it)
GB (1) GB1545880A (it)
IT (1) IT1092733B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456978A (en) * 1980-02-12 1984-06-26 General Instrument Corp. Electrically alterable read only memory semiconductor device made by low pressure chemical vapor deposition process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES404184A1 (es) * 1971-07-06 1975-06-01 Ibm Una disposicion de celula de memoria de acceso casual para calculadoras digitales.
US3882469A (en) * 1971-11-30 1975-05-06 Texas Instruments Inc Non-volatile variable threshold memory cell

Also Published As

Publication number Publication date
FR2382074A1 (fr) 1978-09-22
IT1092733B (it) 1985-07-12
GB1545880A (en) 1979-05-16
IT7820203A0 (it) 1978-02-13
DE2708101A1 (de) 1978-08-31

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