IT1319614B1 - Metodo per programmare una pluralita' di celle di memoria collegate inparallelo e relativo circuito di programmazione - Google Patents

Metodo per programmare una pluralita' di celle di memoria collegate inparallelo e relativo circuito di programmazione

Info

Publication number
IT1319614B1
IT1319614B1 IT2000MI002807A ITMI20002807A IT1319614B1 IT 1319614 B1 IT1319614 B1 IT 1319614B1 IT 2000MI002807 A IT2000MI002807 A IT 2000MI002807A IT MI20002807 A ITMI20002807 A IT MI20002807A IT 1319614 B1 IT1319614 B1 IT 1319614B1
Authority
IT
Italy
Prior art keywords
program
memory cells
parallel connected
connected memory
programming circuit
Prior art date
Application number
IT2000MI002807A
Other languages
English (en)
Inventor
Marco Pasotti
Giovanni Guaitini
Sandre Guido De
David Iezzi
Marco Poles
Pierluigi Rolandi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000MI002807A priority Critical patent/IT1319614B1/it
Priority to US10/036,337 priority patent/US6687159B2/en
Publication of ITMI20002807A1 publication Critical patent/ITMI20002807A1/it
Application granted granted Critical
Publication of IT1319614B1 publication Critical patent/IT1319614B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
IT2000MI002807A 2000-12-22 2000-12-22 Metodo per programmare una pluralita' di celle di memoria collegate inparallelo e relativo circuito di programmazione IT1319614B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000MI002807A IT1319614B1 (it) 2000-12-22 2000-12-22 Metodo per programmare una pluralita' di celle di memoria collegate inparallelo e relativo circuito di programmazione
US10/036,337 US6687159B2 (en) 2000-12-22 2001-12-19 Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000MI002807A IT1319614B1 (it) 2000-12-22 2000-12-22 Metodo per programmare una pluralita' di celle di memoria collegate inparallelo e relativo circuito di programmazione

Publications (2)

Publication Number Publication Date
ITMI20002807A1 ITMI20002807A1 (it) 2002-06-22
IT1319614B1 true IT1319614B1 (it) 2003-10-20

Family

ID=11446309

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000MI002807A IT1319614B1 (it) 2000-12-22 2000-12-22 Metodo per programmare una pluralita' di celle di memoria collegate inparallelo e relativo circuito di programmazione

Country Status (2)

Country Link
US (1) US6687159B2 (it)
IT (1) IT1319614B1 (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932090B2 (en) * 2004-08-05 2011-04-26 3M Innovative Properties Company Sample processing device positioning apparatus and methods
US7313019B2 (en) * 2004-12-21 2007-12-25 Intel Corporation Step voltage generation
US7339834B2 (en) 2005-06-03 2008-03-04 Sandisk Corporation Starting program voltage shift with cycling of non-volatile memory
US7233528B2 (en) * 2005-07-25 2007-06-19 Atmel Corporation Reduction of programming time in electrically programmable devices
US7352626B1 (en) * 2005-08-29 2008-04-01 Spansion Llc Voltage regulator with less overshoot and faster settling time
US8358543B1 (en) 2005-09-20 2013-01-22 Spansion Llc Flash memory programming with data dependent control of source lines
US7551489B2 (en) * 2005-12-28 2009-06-23 Intel Corporation Multi-level memory cell sensing
KR101333503B1 (ko) * 2006-02-03 2013-11-28 삼성전자주식회사 프로그램 셀의 수에 따라 프로그램 전압을 조절하는 반도체메모리 장치 및 그것의 프로그램 방법
US7639540B2 (en) * 2007-02-16 2009-12-29 Mosaid Technologies Incorporated Non-volatile semiconductor memory having multiple external power supplies
US7532515B2 (en) * 2007-05-14 2009-05-12 Intel Corporation Voltage reference generator using big flash cell
KR101043824B1 (ko) * 2008-02-04 2011-06-22 주식회사 하이닉스반도체 펌핑전압 발생장치 및 그 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4797856A (en) * 1987-04-16 1989-01-10 Intel Corporation Self-limiting erase scheme for EEPROM
ITMI981193A1 (it) * 1998-05-29 1999-11-29 St Microelectronics Srl Dispositivo circuitale e relativo metodo per la propgrammazione di una cella di memoria non volatile a singola tensione di

Also Published As

Publication number Publication date
ITMI20002807A1 (it) 2002-06-22
US6687159B2 (en) 2004-02-03
US20020105835A1 (en) 2002-08-08

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