DE60039587D1 - Schaltungsanordnung zum Programmieren von Daten in Referenzzellen einer nichtflüchtigen Multibitspeicheranordnung - Google Patents

Schaltungsanordnung zum Programmieren von Daten in Referenzzellen einer nichtflüchtigen Multibitspeicheranordnung

Info

Publication number
DE60039587D1
DE60039587D1 DE60039587T DE60039587T DE60039587D1 DE 60039587 D1 DE60039587 D1 DE 60039587D1 DE 60039587 T DE60039587 T DE 60039587T DE 60039587 T DE60039587 T DE 60039587T DE 60039587 D1 DE60039587 D1 DE 60039587D1
Authority
DE
Germany
Prior art keywords
arrangement
bit memory
reference cells
programming data
volatile multi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60039587T
Other languages
English (en)
Inventor
Paolo Rolandi
Massimo Montanaro
Giorgio Oddone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60039587D1 publication Critical patent/DE60039587D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
DE60039587T 2000-05-31 2000-05-31 Schaltungsanordnung zum Programmieren von Daten in Referenzzellen einer nichtflüchtigen Multibitspeicheranordnung Expired - Lifetime DE60039587D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00830392A EP1160794B1 (de) 2000-05-31 2000-05-31 Schaltungsanordnung zum Programmieren von Daten in Referenzzellen einer nichtflüchtigen Multibitspeicheranordnung

Publications (1)

Publication Number Publication Date
DE60039587D1 true DE60039587D1 (de) 2008-09-04

Family

ID=8175352

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60039587T Expired - Lifetime DE60039587D1 (de) 2000-05-31 2000-05-31 Schaltungsanordnung zum Programmieren von Daten in Referenzzellen einer nichtflüchtigen Multibitspeicheranordnung

Country Status (3)

Country Link
US (1) US6507517B2 (de)
EP (1) EP1160794B1 (de)
DE (1) DE60039587D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1473739A1 (de) * 2003-04-29 2004-11-03 Dialog Semiconductor GmbH Flash-Speicher mit Datenverlust-Früherkennung
EP1750281B1 (de) * 2005-07-29 2011-07-06 STMicroelectronics Srl Nichtflüchtiger Halbleiterspeicher mit Referenzzellen und entspechendes Steuerverfahren
US7180795B1 (en) * 2005-08-05 2007-02-20 Atmel Corporation Method of sensing an EEPROM reference cell
US7817467B2 (en) 2007-09-07 2010-10-19 Micron Technology, Inc. Memory controller self-calibration for removing systemic influence
KR101883629B1 (ko) 2010-01-20 2018-07-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102189824B1 (ko) * 2014-08-04 2020-12-11 삼성전자주식회사 메모리 장치의 단위 어레이, 이를 포함하는 메모리 장치 및 메모리 시스템
WO2018033834A1 (en) 2016-08-19 2018-02-22 Semiconductor Energy Laboratory Co., Ltd. Method for controlling power supply in semiconductor device
CN109034382A (zh) * 2017-10-30 2018-12-18 上海寒武纪信息科技有限公司 场景或物体的识别方法及相关产品

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3324129B2 (ja) 1991-12-27 2002-09-17 株式会社日立製作所 半導体多値メモリ
US5444656A (en) * 1994-06-02 1995-08-22 Intel Corporation Apparatus for fast internal reference cell trimming
WO1995034075A1 (en) 1994-06-02 1995-12-14 Intel Corporation Sensing schemes for flash memory with multilevel cells
EP0753859B1 (de) * 1995-07-14 2000-01-26 STMicroelectronics S.r.l. Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle
US5687114A (en) * 1995-10-06 1997-11-11 Agate Semiconductor, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US5629892A (en) 1995-10-16 1997-05-13 Advanced Micro Devices, Inc. Flash EEPROM memory with separate reference array
EP0798727B1 (de) * 1996-03-29 2004-05-26 STMicroelectronics S.r.l. Datenleseverwaltungsarchitektur für eine Speichervorrichtung, besonders für nichtflüchtige Speicher
EP0805454A1 (de) * 1996-04-30 1997-11-05 STMicroelectronics S.r.l. Abtastschaltung zum Lesen und Nachprüfen eines Speicherzelleninhalts
US5774395A (en) 1996-11-27 1998-06-30 Advanced Micro Devices, Inc. Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels
JP3990485B2 (ja) * 1997-12-26 2007-10-10 株式会社ルネサステクノロジ 半導体不揮発性記憶装置
JP3237610B2 (ja) * 1998-05-19 2001-12-10 日本電気株式会社 不揮発性半導体記憶装置
EP0978844B1 (de) 1998-08-07 2005-11-02 STMicroelectronics S.r.l. Ausleseanordnung für Multibit-Halbleiterspeicheranordnung
US5936906A (en) 1998-10-29 1999-08-10 Winbond Electronics Corp. Multilevel sense device for a flash memory
KR100346991B1 (ko) * 1999-07-13 2002-07-31 산요 덴키 가부시키가이샤 반도체 기억 장치

Also Published As

Publication number Publication date
US6507517B2 (en) 2003-01-14
US20020015326A1 (en) 2002-02-07
EP1160794A1 (de) 2001-12-05
EP1160794B1 (de) 2008-07-23

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