IT1318978B1 - Struttura di controllo e temporizzazione per una memoria - Google Patents

Struttura di controllo e temporizzazione per una memoria

Info

Publication number
IT1318978B1
IT1318978B1 IT2000MI002163A ITMI20002163A IT1318978B1 IT 1318978 B1 IT1318978 B1 IT 1318978B1 IT 2000MI002163 A IT2000MI002163 A IT 2000MI002163A IT MI20002163 A ITMI20002163 A IT MI20002163A IT 1318978 B1 IT1318978 B1 IT 1318978B1
Authority
IT
Italy
Prior art keywords
timing
memory
control structure
control
Prior art date
Application number
IT2000MI002163A
Other languages
English (en)
Inventor
Luigi Pascucci
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000MI002163A priority Critical patent/IT1318978B1/it
Publication of ITMI20002163A0 publication Critical patent/ITMI20002163A0/it
Priority to US09/972,753 priority patent/US6549485B2/en
Publication of ITMI20002163A1 publication Critical patent/ITMI20002163A1/it
Application granted granted Critical
Publication of IT1318978B1 publication Critical patent/IT1318978B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
IT2000MI002163A 2000-10-06 2000-10-06 Struttura di controllo e temporizzazione per una memoria IT1318978B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000MI002163A IT1318978B1 (it) 2000-10-06 2000-10-06 Struttura di controllo e temporizzazione per una memoria
US09/972,753 US6549485B2 (en) 2000-10-06 2001-10-05 Control and timing structure for a memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000MI002163A IT1318978B1 (it) 2000-10-06 2000-10-06 Struttura di controllo e temporizzazione per una memoria

Publications (3)

Publication Number Publication Date
ITMI20002163A0 ITMI20002163A0 (it) 2000-10-06
ITMI20002163A1 ITMI20002163A1 (it) 2002-04-06
IT1318978B1 true IT1318978B1 (it) 2003-09-19

Family

ID=11445921

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000MI002163A IT1318978B1 (it) 2000-10-06 2000-10-06 Struttura di controllo e temporizzazione per una memoria

Country Status (2)

Country Link
US (1) US6549485B2 (it)
IT (1) IT1318978B1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009026370A (ja) * 2007-07-19 2009-02-05 Spansion Llc 同期型記憶装置及びその制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261064A (en) * 1989-10-03 1993-11-09 Advanced Micro Devices, Inc. Burst access memory
JP3380050B2 (ja) * 1994-07-14 2003-02-24 富士通株式会社 半導体記憶装置のデータ読み出し方法

Also Published As

Publication number Publication date
ITMI20002163A0 (it) 2000-10-06
ITMI20002163A1 (it) 2002-04-06
US20020067655A1 (en) 2002-06-06
US6549485B2 (en) 2003-04-15

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