DE69937611D1 - Intelligenter Puffer-Speicher - Google Patents
Intelligenter Puffer-SpeicherInfo
- Publication number
- DE69937611D1 DE69937611D1 DE69937611T DE69937611T DE69937611D1 DE 69937611 D1 DE69937611 D1 DE 69937611D1 DE 69937611 T DE69937611 T DE 69937611T DE 69937611 T DE69937611 T DE 69937611T DE 69937611 D1 DE69937611 D1 DE 69937611D1
- Authority
- DE
- Germany
- Prior art keywords
- buffer memory
- intelligent buffer
- intelligent
- memory
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture
- G06F2212/251—Local memory within processor subsystem
- G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99403042A EP1107123B1 (de) | 1999-12-06 | 1999-12-06 | Intelligenter Puffer-Speicher |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69937611D1 true DE69937611D1 (de) | 2008-01-03 |
DE69937611T2 DE69937611T2 (de) | 2008-10-23 |
Family
ID=8242200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69937611T Expired - Lifetime DE69937611T2 (de) | 1999-12-06 | 1999-12-06 | Intelligenter Puffer-Speicher |
Country Status (5)
Country | Link |
---|---|
US (1) | US6826652B1 (de) |
EP (1) | EP1107123B1 (de) |
JP (1) | JP2001297037A (de) |
KR (1) | KR100805974B1 (de) |
DE (1) | DE69937611T2 (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6584546B2 (en) * | 2001-01-16 | 2003-06-24 | Gautam Nag Kavipurapu | Highly efficient design of storage array for use in first and second cache spaces and memory subsystems |
US7653787B2 (en) * | 2001-05-07 | 2010-01-26 | Alcatel-Lucent Usa Inc. | System for storing web site names and caching audio resources of the most visited web sites |
US7278136B2 (en) * | 2002-07-09 | 2007-10-02 | University Of Massachusetts | Reducing processor energy consumption using compile-time information |
US6934865B2 (en) * | 2002-07-09 | 2005-08-23 | University Of Massachusetts | Controlling a processor resource based on a compile-time prediction of number of instructions-per-cycle that will be executed across plural cycles by the processor |
US7493607B2 (en) | 2002-07-09 | 2009-02-17 | Bluerisc Inc. | Statically speculative compilation and execution |
EP1387274A3 (de) * | 2002-07-31 | 2004-08-11 | Texas Instruments Incorporated | Speicherverwaltung für lokale Variablen |
JP4713077B2 (ja) * | 2003-03-26 | 2011-06-29 | パナソニック株式会社 | 半導体装置 |
US7069390B2 (en) * | 2003-09-04 | 2006-06-27 | International Business Machines Corporation | Implementation of a pseudo-LRU algorithm in a partitioned cache |
US7114035B2 (en) * | 2003-09-04 | 2006-09-26 | International Business Machines Corporation | Software-controlled cache set management with software-generated class identifiers |
US7120748B2 (en) * | 2003-09-04 | 2006-10-10 | International Business Machines Corporation | Software-controlled cache set management |
US7055004B2 (en) * | 2003-09-04 | 2006-05-30 | International Business Machines Corporation | Pseudo-LRU for a locking cache |
US20050114850A1 (en) | 2003-10-29 | 2005-05-26 | Saurabh Chheda | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
US8607209B2 (en) | 2004-02-04 | 2013-12-10 | Bluerisc Inc. | Energy-focused compiler-assisted branch prediction |
US7543113B2 (en) * | 2004-07-02 | 2009-06-02 | Hewlett-Packard Development Company, L.P. | Cache memory system and method capable of adaptively accommodating various memory line sizes |
EP1622009A1 (de) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM-Architektur und Systeme |
US8110868B2 (en) | 2005-07-27 | 2012-02-07 | Infineon Technologies Austria Ag | Power semiconductor component with a low on-state resistance |
US8461648B2 (en) | 2005-07-27 | 2013-06-11 | Infineon Technologies Austria Ag | Semiconductor component with a drift region and a drift control region |
US20080126766A1 (en) | 2006-11-03 | 2008-05-29 | Saurabh Chheda | Securing microprocessors against information leakage and physical tampering |
KR100868585B1 (ko) | 2007-05-29 | 2008-11-12 | 주식회사 아모텍 | 서지 흡수기 및 그의 제조방법 |
KR200451794Y1 (ko) * | 2010-03-19 | 2011-01-12 | 주식회사 케이피 | 힌지 보강구조가 부착된 선박 가구용 하드코어 보강재 |
US8832508B2 (en) * | 2010-11-18 | 2014-09-09 | Advanced Micro Devices, Inc. | Apparatus and methods for testing writability and readability of memory cell arrays |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5014195A (en) * | 1990-05-10 | 1991-05-07 | Digital Equipment Corporation, Inc. | Configurable set associative cache with decoded data element enable lines |
US5410669A (en) * | 1993-04-05 | 1995-04-25 | Motorola, Inc. | Data processor having a cache memory capable of being used as a linear ram bank |
JPH07271672A (ja) * | 1994-03-30 | 1995-10-20 | Toshiba Corp | マルチウェイセットアソシアティブキャッシュシステム |
JPH0877072A (ja) * | 1994-08-31 | 1996-03-22 | Oki Electric Ind Co Ltd | キャッシュメモリ装置 |
US5822755A (en) * | 1996-01-25 | 1998-10-13 | International Business Machines Corporation | Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache |
US5966737A (en) * | 1996-06-26 | 1999-10-12 | Compaq Computer, Corp. | Apparatus and method for serialized set prediction |
JP3088303B2 (ja) * | 1996-09-09 | 2000-09-18 | 日本電気アイシーマイコンシステム株式会社 | キャッシュ・メモリ・バンク制御装置 |
US5809528A (en) * | 1996-12-24 | 1998-09-15 | International Business Machines Corporation | Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory |
US6334173B1 (en) * | 1997-11-17 | 2001-12-25 | Hyundai Electronics Industries Co. Ltd. | Combined cache with main memory and a control method thereof |
US6185657B1 (en) * | 1998-04-20 | 2001-02-06 | Motorola Inc. | Multi-way cache apparatus and method |
US6415353B1 (en) * | 1998-10-01 | 2002-07-02 | Monolithic System Technology, Inc. | Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same |
EP1387274A3 (de) * | 2002-07-31 | 2004-08-11 | Texas Instruments Incorporated | Speicherverwaltung für lokale Variablen |
-
1999
- 1999-12-06 DE DE69937611T patent/DE69937611T2/de not_active Expired - Lifetime
- 1999-12-06 EP EP99403042A patent/EP1107123B1/de not_active Expired - Lifetime
-
2000
- 2000-06-09 US US09/591,537 patent/US6826652B1/en not_active Expired - Lifetime
- 2000-12-06 JP JP2000403912A patent/JP2001297037A/ja active Pending
- 2000-12-06 KR KR1020000073829A patent/KR100805974B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2001297037A (ja) | 2001-10-26 |
DE69937611T2 (de) | 2008-10-23 |
EP1107123B1 (de) | 2007-11-21 |
KR100805974B1 (ko) | 2008-02-25 |
US6826652B1 (en) | 2004-11-30 |
KR20010062173A (ko) | 2001-07-07 |
EP1107123A1 (de) | 2001-06-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |