IT1293536B1 - Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore - Google Patents

Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore

Info

Publication number
IT1293536B1
IT1293536B1 IT97RM000431A ITRM970431A IT1293536B1 IT 1293536 B1 IT1293536 B1 IT 1293536B1 IT 97RM000431 A IT97RM000431 A IT 97RM000431A IT RM970431 A ITRM970431 A IT RM970431A IT 1293536 B1 IT1293536 B1 IT 1293536B1
Authority
IT
Italy
Prior art keywords
semiconductor devices
metallization process
multilevel metallization
high planarization
planarization
Prior art date
Application number
IT97RM000431A
Other languages
English (en)
Italian (it)
Inventor
Felice Russo
Giuseppe Miccoli
Natale Nardi
Marco Ricotti
Alfredo Franchina
Original Assignee
Consorzio Eagle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consorzio Eagle filed Critical Consorzio Eagle
Priority to IT97RM000431A priority Critical patent/IT1293536B1/it
Publication of ITRM970431A0 publication Critical patent/ITRM970431A0/it
Priority to JP10232206A priority patent/JPH11233515A/ja
Priority to EP98305603A priority patent/EP0897193A3/en
Priority to KR1019980028388A priority patent/KR19990013850A/ko
Publication of ITRM970431A1 publication Critical patent/ITRM970431A1/it
Application granted granted Critical
Publication of IT1293536B1 publication Critical patent/IT1293536B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
IT97RM000431A 1997-07-14 1997-07-14 Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore IT1293536B1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT97RM000431A IT1293536B1 (it) 1997-07-14 1997-07-14 Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore
JP10232206A JPH11233515A (ja) 1997-07-14 1998-07-14 半導体装置の多層配線平坦化方法
EP98305603A EP0897193A3 (en) 1997-07-14 1998-07-14 Process of making a multilevel metallization scheme with high planarization degree
KR1019980028388A KR19990013850A (ko) 1997-07-14 1998-07-14 반도체 장치에 대한 고 평탄화 멀티 레벨 금속화 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97RM000431A IT1293536B1 (it) 1997-07-14 1997-07-14 Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore

Publications (3)

Publication Number Publication Date
ITRM970431A0 ITRM970431A0 (https=) 1997-07-14
ITRM970431A1 ITRM970431A1 (it) 1999-01-14
IT1293536B1 true IT1293536B1 (it) 1999-03-01

Family

ID=11405176

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97RM000431A IT1293536B1 (it) 1997-07-14 1997-07-14 Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore

Country Status (4)

Country Link
EP (1) EP0897193A3 (https=)
JP (1) JPH11233515A (https=)
KR (1) KR19990013850A (https=)
IT (1) IT1293536B1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120261401B (zh) * 2025-05-30 2025-09-26 合肥晶合集成电路股份有限公司 半导体结构及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5366911A (en) * 1994-05-11 1994-11-22 United Microelectronics Corporation VLSI process with global planarization
JP2836529B2 (ja) * 1995-04-27 1998-12-14 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR19990013850A (ko) 1999-02-25
ITRM970431A0 (https=) 1997-07-14
EP0897193A2 (en) 1999-02-17
EP0897193A3 (en) 1999-08-04
ITRM970431A1 (it) 1999-01-14
JPH11233515A (ja) 1999-08-27

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