IT1289933B1 - Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione - Google Patents

Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione

Info

Publication number
IT1289933B1
IT1289933B1 IT97MI000357A ITMI970357A IT1289933B1 IT 1289933 B1 IT1289933 B1 IT 1289933B1 IT 97MI000357 A IT97MI000357 A IT 97MI000357A IT MI970357 A ITMI970357 A IT MI970357A IT 1289933 B1 IT1289933 B1 IT 1289933B1
Authority
IT
Italy
Prior art keywords
matrix
manufacturing procedure
triple well
related manufacturing
memory device
Prior art date
Application number
IT97MI000357A
Other languages
English (en)
Inventor
Roberto Bez
Alberto Modelli
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT97MI000357A priority Critical patent/IT1289933B1/it
Priority to US09/027,343 priority patent/US5990526A/en
Publication of ITMI970357A1 publication Critical patent/ITMI970357A1/it
Application granted granted Critical
Publication of IT1289933B1 publication Critical patent/IT1289933B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
IT97MI000357A 1997-02-20 1997-02-20 Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione IT1289933B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT97MI000357A IT1289933B1 (it) 1997-02-20 1997-02-20 Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione
US09/027,343 US5990526A (en) 1997-02-20 1998-02-20 Memory device with a cell array in triple well, and related manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97MI000357A IT1289933B1 (it) 1997-02-20 1997-02-20 Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione

Publications (2)

Publication Number Publication Date
ITMI970357A1 ITMI970357A1 (it) 1998-08-20
IT1289933B1 true IT1289933B1 (it) 1998-10-19

Family

ID=11376088

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97MI000357A IT1289933B1 (it) 1997-02-20 1997-02-20 Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione

Country Status (2)

Country Link
US (1) US5990526A (it)
IT (1) IT1289933B1 (it)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL125604A (en) 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6633496B2 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Symmetric architecture for memory cells having widely spread metal bit lines
US6633499B1 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Method for reducing voltage drops in symmetric array architectures
US6430077B1 (en) 1997-12-12 2002-08-06 Saifun Semiconductors Ltd. Method for regulating read voltage level at the drain of a cell in a symmetric array
JP3523521B2 (ja) * 1998-04-09 2004-04-26 松下電器産業株式会社 Ｍｏｓトランジスタ対装置
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6826107B2 (en) 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
EP1746645A3 (en) 2005-07-18 2009-01-21 Saifun Semiconductors Ltd. Memory array with sub-minimum feature size word line spacing and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933736A (en) * 1982-04-12 1990-06-12 North American Philips Corporation, Signetics Division Programmable read-only memory
JPS63278248A (ja) * 1987-03-13 1988-11-15 Fujitsu Ltd ゲ−トアレイの基本セル
US5396100A (en) * 1991-04-05 1995-03-07 Hitachi, Ltd. Semiconductor integrated circuit device having a compact arrangement of SRAM cells
KR0135798B1 (ko) * 1994-08-17 1998-04-24 김광호 전류증폭형 마스크-롬

Also Published As

Publication number Publication date
US5990526A (en) 1999-11-23
ITMI970357A1 (it) 1998-08-20

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