IT1293644B1 - Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash - Google Patents

Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash

Info

Publication number
IT1293644B1
IT1293644B1 IT97TO000667A ITTO970667A IT1293644B1 IT 1293644 B1 IT1293644 B1 IT 1293644B1 IT 97TO000667 A IT97TO000667 A IT 97TO000667A IT TO970667 A ITTO970667 A IT TO970667A IT 1293644 B1 IT1293644 B1 IT 1293644B1
Authority
IT
Italy
Prior art keywords
cells
reading
circuit
analog memory
memory matrix
Prior art date
Application number
IT97TO000667A
Other languages
English (en)
Inventor
Danilo Gerna
Roberto Canegallo
Ernestina Chioffi
Marco Pasotti
Pier Luigi Rolandi
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT97TO000667A priority Critical patent/IT1293644B1/it
Priority to US09/121,024 priority patent/US5973959A/en
Publication of ITTO970667A1 publication Critical patent/ITTO970667A1/it
Application granted granted Critical
Publication of IT1293644B1 publication Critical patent/IT1293644B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5645—Multilevel memory with current-mirror arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
IT97TO000667A 1997-07-25 1997-07-25 Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash IT1293644B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT97TO000667A IT1293644B1 (it) 1997-07-25 1997-07-25 Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash
US09/121,024 US5973959A (en) 1997-07-25 1998-07-22 Circuit and method of reading cells of an analog memory array, in particular of the flash type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97TO000667A IT1293644B1 (it) 1997-07-25 1997-07-25 Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash

Publications (2)

Publication Number Publication Date
ITTO970667A1 ITTO970667A1 (it) 1999-01-25
IT1293644B1 true IT1293644B1 (it) 1999-03-08

Family

ID=11415890

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97TO000667A IT1293644B1 (it) 1997-07-25 1997-07-25 Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash

Country Status (2)

Country Link
US (1) US5973959A (it)
IT (1) IT1293644B1 (it)

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ITMI981193A1 (it) * 1998-05-29 1999-11-29 St Microelectronics Srl Dispositivo circuitale e relativo metodo per la propgrammazione di una cella di memoria non volatile a singola tensione di
US6195289B1 (en) * 1998-07-22 2001-02-27 Stmicroelectronics, S.R.L. Device for reading analog nonvolatile memory cells, in particular flash cells
IT1307687B1 (it) * 1999-04-13 2001-11-14 St Microelectronics Srl Circuito e metodo di regolazione automatica della durata dellaequalizzazione nella fase di lettura di una memoria non volatile.
KR100301817B1 (ko) * 1999-06-29 2001-11-01 김영환 레퍼런스 메모리셀의 초기화 회로 및 그를 이용한 초기화 방법
US6400644B1 (en) * 1999-07-21 2002-06-04 Matsushita Electric Industrial Co., Ltd. Semiconductor control unit
IT1308857B1 (it) * 1999-10-29 2002-01-11 St Microelectronics Srl Metodo e circuito di lettura per una memoria non volatile.
FI107478B (fi) * 1999-12-03 2001-08-15 Nokia Networks Oy Digitaalinen ramppigeneraattori, jossa on lähtötehon säädin
JP3611497B2 (ja) * 2000-03-02 2005-01-19 松下電器産業株式会社 電流センスアンプ
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
DE10062124C1 (de) * 2000-12-13 2002-06-27 Infineon Technologies Ag Schaltungsanordnung zum Auslesen von Speicherzellen von Speicherbauelementen
US6307783B1 (en) * 2001-02-26 2001-10-23 Advanced Micro Devices, Inc. Descending staircase read technique for a multilevel cell NAND flash memory device
US6586987B2 (en) * 2001-06-14 2003-07-01 Maxim Integrated Products, Inc. Circuit with source follower output stage and adaptive current mirror bias
JP2003203488A (ja) * 2001-12-28 2003-07-18 Mitsubishi Electric Corp 不揮発性半導体メモリ
JP2004055012A (ja) * 2002-07-18 2004-02-19 Renesas Technology Corp 不揮発性半導体メモリ
ITTO20030121A1 (it) * 2003-02-18 2004-08-19 St Microelectronics Srl Amplificatore di lettura di celle di memoria non volatili a
US7237074B2 (en) * 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US20050010284A1 (en) * 2003-07-10 2005-01-13 Gregory Kenton W. Method for decreasing bioprosthetic implant failure
US6937518B1 (en) * 2003-07-10 2005-08-30 Advanced Micro Devices, Inc. Programming of a flash memory cell
US7301807B2 (en) 2003-10-23 2007-11-27 Sandisk Corporation Writable tracking cells
ITVA20040019A1 (it) * 2004-05-04 2004-08-04 St Microelectronics Srl Metodo e circuito di verifica ed eventuale sostituzione di celle di riferimento difettose di una memoria
KR100604871B1 (ko) * 2004-06-17 2006-07-31 삼성전자주식회사 상보형 불휘발성 메모리 소자와 그 동작 방법과 그 제조 방법과 그를 포함하는 논리소자 및 반도체 장치
ITTO20040470A1 (it) * 2004-07-08 2004-10-08 St Microelectronics Srl Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.
DE602004021599D1 (de) * 2004-09-28 2009-07-30 St Microelectronics Srl Leseschaltung und Leseverfahren für eine nichtflüchtige Speichervorrichtung
US8331203B2 (en) * 2006-07-27 2012-12-11 Stmicroelectronics S.A. Charge retention circuit for a time measurement
EP2047475B1 (fr) * 2006-07-27 2010-06-16 Stmicroelectronics SA Circuit de lecture d'un element de retention de charges pour mesure temporelle
FR2904464A1 (fr) * 2006-07-27 2008-02-01 St Microelectronics Sa Circuit eeprom de retention de charges pour mesure temporelle
FR2904463A1 (fr) * 2006-07-27 2008-02-01 St Microelectronics Sa Programmation d'un circuit de retention de charges pour mesure temporelle
KR100827700B1 (ko) * 2007-01-17 2008-05-07 삼성전자주식회사 불휘발성 메모리 장치에서의 내부 고전압 측정 방법 및전압 출력회로
US8068367B2 (en) * 2007-06-15 2011-11-29 Micron Technology, Inc. Reference current sources
JP5331031B2 (ja) * 2010-02-25 2013-10-30 ラピスセミコンダクタ株式会社 電流検出回路
CN112349316A (zh) * 2019-08-06 2021-02-09 北京知存科技有限公司 用于存储单元阵列的读出单元以及包括其的存算一体芯片

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JPH0346197A (ja) * 1989-07-13 1991-02-27 Fujitsu Ltd 半導体記憶装置
JP2586722B2 (ja) * 1990-10-11 1997-03-05 日本電気株式会社 半導体記憶装置
US5335198A (en) * 1993-05-06 1994-08-02 Advanced Micro Devices, Inc. Flash EEPROM array with high endurance
EP0735542A1 (en) * 1995-03-31 1996-10-02 STMicroelectronics S.r.l. Reading circuit for multilevel non-volatile memory cell devices
FR2734390B1 (fr) * 1995-05-19 1997-06-13 Sgs Thomson Microelectronics Circuit de detection de courant pour la lecture d'une memoire en circuit integre
US5712815A (en) * 1996-04-22 1998-01-27 Advanced Micro Devices, Inc. Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
US5805500A (en) * 1997-06-18 1998-09-08 Sgs-Thomson Microelectronics S.R.L. Circuit and method for generating a read reference signal for nonvolatile memory cells

Also Published As

Publication number Publication date
ITTO970667A1 (it) 1999-01-25
US5973959A (en) 1999-10-26

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