IT1283846B1 - Procedimento per la disposizione di piste conduttrici sulla superficie di un elemento a semiconduttore - Google Patents
Procedimento per la disposizione di piste conduttrici sulla superficie di un elemento a semiconduttoreInfo
- Publication number
- IT1283846B1 IT1283846B1 IT96MI001797A ITMI961797A IT1283846B1 IT 1283846 B1 IT1283846 B1 IT 1283846B1 IT 96MI001797 A IT96MI001797 A IT 96MI001797A IT MI961797 A ITMI961797 A IT MI961797A IT 1283846 B1 IT1283846 B1 IT 1283846B1
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- arrangement
- semiconductor element
- conductive tracks
- tracks
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/926—Dummy metallization
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19531651A DE19531651C2 (de) | 1995-08-29 | 1995-08-29 | Verfahren zur Anordnung von Leiterbahnen auf der Oberfläche eines Halbleiterbauelements |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI961797A0 ITMI961797A0 (it) | 1996-08-28 |
ITMI961797A1 ITMI961797A1 (it) | 1998-02-28 |
IT1283846B1 true IT1283846B1 (it) | 1998-04-30 |
Family
ID=7770610
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT96MI001797A IT1283846B1 (it) | 1995-08-29 | 1996-08-28 | Procedimento per la disposizione di piste conduttrici sulla superficie di un elemento a semiconduttore |
Country Status (4)
Country | Link |
---|---|
US (1) | US5888893A (it) |
DE (1) | DE19531651C2 (it) |
FR (1) | FR2738672B1 (it) |
IT (1) | IT1283846B1 (it) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19936862C1 (de) * | 1999-08-05 | 2001-01-25 | Siemens Ag | Kontaktierung von Metalleiterbahnen eines integrierten Halbleiterchips |
US6621721B2 (en) * | 2002-01-31 | 2003-09-16 | The Boeing Company | Direct conversion programmable power source controller: three-phase input with programmable single-phase output |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55163859A (en) * | 1979-06-07 | 1980-12-20 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH01154531A (ja) * | 1987-12-11 | 1989-06-16 | Hitachi Ltd | 自動束配線方式 |
JPH06105710B2 (ja) * | 1990-02-14 | 1994-12-21 | 株式会社東芝 | 半導体装置 |
FR2668300B1 (fr) * | 1990-10-18 | 1993-01-29 | Sagem | Procede de realisation de circuits integres a double connectique. |
US5494853A (en) * | 1994-07-25 | 1996-02-27 | United Microelectronics Corporation | Method to solve holes in passivation by metal layout |
US5521434A (en) * | 1994-10-17 | 1996-05-28 | International Business Machines Corporation | Semiconductor chip and electronic module with integrated surface interconnects/components |
-
1995
- 1995-08-29 DE DE19531651A patent/DE19531651C2/de not_active Expired - Fee Related
-
1996
- 1996-08-14 FR FR9610215A patent/FR2738672B1/fr not_active Expired - Fee Related
- 1996-08-28 IT IT96MI001797A patent/IT1283846B1/it active IP Right Grant
- 1996-08-29 US US08/705,355 patent/US5888893A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
ITMI961797A0 (it) | 1996-08-28 |
US5888893A (en) | 1999-03-30 |
FR2738672A1 (fr) | 1997-03-14 |
FR2738672B1 (fr) | 1998-08-07 |
ITMI961797A1 (it) | 1998-02-28 |
DE19531651A1 (de) | 1997-03-06 |
DE19531651C2 (de) | 2001-09-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted |