IT1272345B - "procedimento per la levigatura dello spigolo di fette di semiconduttori". - Google Patents

"procedimento per la levigatura dello spigolo di fette di semiconduttori".

Info

Publication number
IT1272345B
IT1272345B ITRM940495A ITRM940495A IT1272345B IT 1272345 B IT1272345 B IT 1272345B IT RM940495 A ITRM940495 A IT RM940495A IT RM940495 A ITRM940495 A IT RM940495A IT 1272345 B IT1272345 B IT 1272345B
Authority
IT
Italy
Prior art keywords
smoothing
procedure
edge
semiconductor slices
slices
Prior art date
Application number
ITRM940495A
Other languages
English (en)
Inventor
Anton Huber
Joachim Junge
Original Assignee
Wacker Chemitronic
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wacker Chemitronic filed Critical Wacker Chemitronic
Publication of ITRM940495A0 publication Critical patent/ITRM940495A0/it
Publication of ITRM940495A1 publication Critical patent/ITRM940495A1/it
Application granted granted Critical
Publication of IT1272345B publication Critical patent/IT1272345B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02021Edge treatment, chamfering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02024Mirror polishing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
ITRM940495A 1993-07-29 1994-07-27 "procedimento per la levigatura dello spigolo di fette di semiconduttori". IT1272345B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4325518A DE4325518A1 (de) 1993-07-29 1993-07-29 Verfahren zur Glättung der Kante von Halbleiterscheiben

Publications (3)

Publication Number Publication Date
ITRM940495A0 ITRM940495A0 (it) 1994-07-27
ITRM940495A1 ITRM940495A1 (it) 1996-01-27
IT1272345B true IT1272345B (it) 1997-06-16

Family

ID=6494026

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM940495A IT1272345B (it) 1993-07-29 1994-07-27 "procedimento per la levigatura dello spigolo di fette di semiconduttori".

Country Status (7)

Country Link
JP (1) JPH0760624A (it)
KR (1) KR950004435A (it)
CN (1) CN1103511A (it)
DE (1) DE4325518A1 (it)
IT (1) IT1272345B (it)
MY (1) MY130149A (it)
TW (1) TW260812B (it)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11245151A (ja) * 1998-02-27 1999-09-14 Speedfam Co Ltd ワークの外周研磨装置
JP3197253B2 (ja) * 1998-04-13 2001-08-13 株式会社日平トヤマ ウエーハの面取り方法
JP2000158315A (ja) * 1998-11-27 2000-06-13 Speedfam-Ipec Co Ltd 端面研磨装置におけるノッチ研磨装置のノッチ研磨方法
KR20000076987A (ko) * 1999-03-31 2000-12-26 다구마시로오 피가공물 연삭방법 및 장치
JP3510584B2 (ja) * 2000-11-07 2004-03-29 スピードファム株式会社 円板形ワークの外周研磨装置
JP2002329687A (ja) * 2001-05-02 2002-11-15 Speedfam Co Ltd デバイスウエハの外周研磨装置及び研磨方法
JP3949941B2 (ja) * 2001-11-26 2007-07-25 株式会社東芝 半導体装置の製造方法および研磨装置
JP5112703B2 (ja) * 2007-01-18 2013-01-09 ダイトエレクトロン株式会社 ウェーハ面取り加工方法およびその装置
DE102009030294B4 (de) 2009-06-24 2013-04-25 Siltronic Ag Verfahren zur Politur der Kante einer Halbleiterscheibe
JP2011194561A (ja) * 2010-02-26 2011-10-06 Nakamura Tome Precision Ind Co Ltd 円盤状ワークの面取装置
CN102642253B (zh) * 2012-05-04 2014-12-10 上海华力微电子有限公司 一种硅片切边方法及其装置
CN104284755B (zh) * 2012-05-07 2016-09-21 信越半导体股份有限公司 圆板形工件用外周研磨装置
DE102013210057A1 (de) 2013-05-29 2014-12-04 Siltronic Ag Verfahren zur Politur der Kante einer Halbleiterscheibe
CN113182971B (zh) * 2021-05-12 2022-11-25 四川雅吉芯电子科技有限公司 一种单晶硅外延片高精度磨边装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57184662A (en) * 1981-05-09 1982-11-13 Hitachi Ltd Chamfering method and device of wafer
JPS5958827A (ja) * 1982-09-28 1984-04-04 Toshiba Corp 半導体ウエ−ハ、半導体ウエ−ハの製造方法及び半導体ウエ−ハの製造装置
JP2719855B2 (ja) * 1991-05-24 1998-02-25 信越半導体株式会社 ウエーハ外周の鏡面面取り装置
US5128281A (en) * 1991-06-05 1992-07-07 Texas Instruments Incorporated Method for polishing semiconductor wafer edges
DE4120003A1 (de) * 1991-06-18 1992-12-24 Mueller Georg Nuernberg Vorrichtung und verfahren zum kantenverrunden von halbleiterronden
US5185965A (en) * 1991-07-12 1993-02-16 Daito Shoji Co., Ltd. Method and apparatus for grinding notches of semiconductor wafer

Also Published As

Publication number Publication date
DE4325518A1 (de) 1995-02-02
ITRM940495A0 (it) 1994-07-27
MY130149A (en) 2007-06-29
TW260812B (it) 1995-10-21
KR950004435A (ko) 1995-02-18
CN1103511A (zh) 1995-06-07
ITRM940495A1 (it) 1996-01-27
JPH0760624A (ja) 1995-03-07

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970828