IT1251004B - METHOD FOR FORMING A MICRO MODEL UNDER THE RESOLUTION LIMIT OF A PHOTOLITHOGRAPHIC PROCESS - Google Patents

METHOD FOR FORMING A MICRO MODEL UNDER THE RESOLUTION LIMIT OF A PHOTOLITHOGRAPHIC PROCESS

Info

Publication number
IT1251004B
IT1251004B ITMI912235A ITMI912235A IT1251004B IT 1251004 B IT1251004 B IT 1251004B IT MI912235 A ITMI912235 A IT MI912235A IT MI912235 A ITMI912235 A IT MI912235A IT 1251004 B IT1251004 B IT 1251004B
Authority
IT
Italy
Prior art keywords
layer
resolution limit
photoresist
forming
photolithographic process
Prior art date
Application number
ITMI912235A
Other languages
Italian (it)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI912235A0 publication Critical patent/ITMI912235A0/en
Publication of ITMI912235A1 publication Critical patent/ITMI912235A1/en
Application granted granted Critical
Publication of IT1251004B publication Critical patent/IT1251004B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

Un metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico comprende le fasi di spalmare uno strato di fotoresist (11) su un materiale da incidere (10), esporre lo strato di fotoresist (11) usando una maschera sulla quale è formato un modello avente una larghezza di linea e una spaziatura sotto il limite di risoluzione dello strato di fotoresist (11), sviluppare lo strato di fotoresist esposto per formare scanalature (13) sulle superfici dello strato di fotoresist esposto, riempire le scanalature (13) con un materiale bloccante l'incisione (12) che è resistente all'incisione a ioni ossigeno-reattivi, incidere lo strato di fotoresist (11) mediante incisione a ioni ossigenoreattivi usando il materiale bloccante l'incisione (12) riempiente le scanalature (13) come maschera, e incidere il materiale usando il modello, che è fatto di uno strato di fotoresist e formato mediante il processo di incisione, come maschera.A method of forming a micromodel under the resolution limit of a photolithographic process includes the steps of spreading a layer of photoresist (11) on a material to be engraved (10), exposing the layer of photoresist (11) using a mask on which it is formed a pattern having a line width and spacing below the resolution limit of the photoresist layer (11), developing the exposed photoresist layer to form grooves (13) on the surfaces of the exposed photoresist layer, filling the grooves (13) with an incision blocking material (12) which is resistant to oxygen-reactive ion etching, etch the photoresist layer (11) by oxygen-reactive ion etching using the incision blocking material (12) filling the grooves (13 ) as a mask, and engrave the material using the model, which is made of a layer of photoresist and formed by the etching process, as a mask.

ITMI912235A 1991-01-30 1991-08-09 METHOD FOR FORMING A MICRO MODEL UNDER THE RESOLUTION LIMIT OF A PHOTOLITHOGRAPHIC PROCESS IT1251004B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001578A KR920015482A (en) 1991-01-30 1991-01-30 Micropattern forming method below the limit resolution of optical lithography

Publications (3)

Publication Number Publication Date
ITMI912235A0 ITMI912235A0 (en) 1991-08-09
ITMI912235A1 ITMI912235A1 (en) 1993-02-09
IT1251004B true IT1251004B (en) 1995-04-28

Family

ID=19310487

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI912235A IT1251004B (en) 1991-01-30 1991-08-09 METHOD FOR FORMING A MICRO MODEL UNDER THE RESOLUTION LIMIT OF A PHOTOLITHOGRAPHIC PROCESS

Country Status (6)

Country Link
JP (1) JPH04249311A (en)
KR (1) KR920015482A (en)
DE (1) DE4126635A1 (en)
FR (1) FR2672138A1 (en)
GB (1) GB2252449A (en)
IT (1) IT1251004B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236609A1 (en) * 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
GB2284300B (en) * 1993-11-10 1997-11-19 Hyundai Electronics Ind Process for forming fine pattern of semiconductor device
KR100229611B1 (en) * 1996-06-12 1999-11-15 구자홍 Manufacturing method of liquid crystal display device
JP2000156377A (en) 1998-11-19 2000-06-06 Murata Mfg Co Ltd Resist pattern, its forming method and forming method of wiring pattern
JP5655443B2 (en) * 2010-09-06 2015-01-21 住友電気工業株式会社 Inorganic compound film etching method and semiconductor optical device manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4634645A (en) * 1984-04-13 1987-01-06 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
JPS63114214A (en) * 1986-09-11 1988-05-19 フェアチャイルド　セミコンダクタ　コーポレーション Plasma etching employing double-layer mask
US4878993A (en) * 1988-12-22 1989-11-07 North American Philips Corporation Method of etching thin indium tin oxide films

Also Published As

Publication number Publication date
FR2672138A1 (en) 1992-07-31
KR920015482A (en) 1992-08-27
ITMI912235A0 (en) 1991-08-09
DE4126635A1 (en) 1992-08-13
JPH04249311A (en) 1992-09-04
ITMI912235A1 (en) 1993-02-09
GB2252449A (en) 1992-08-05
GB9117267D0 (en) 1991-09-25

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