GB2252449A - Forming micropatterns in semiconductor substrates - Google Patents

Forming micropatterns in semiconductor substrates Download PDF

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Publication number
GB2252449A
GB2252449A GB9117267A GB9117267A GB2252449A GB 2252449 A GB2252449 A GB 2252449A GB 9117267 A GB9117267 A GB 9117267A GB 9117267 A GB9117267 A GB 9117267A GB 2252449 A GB2252449 A GB 2252449A
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United Kingdom
Prior art keywords
photoresist layer
micropattern
resolution limit
layer
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9117267A
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GB9117267D0 (en
Inventor
Woo-Sung Han
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9117267D0 publication Critical patent/GB9117267D0/en
Publication of GB2252449A publication Critical patent/GB2252449A/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

A method for forming a micropattern with a line width and spacing below the resolution limit of a photolithographic process comprises the steps of covering a photoresist layer (11) over a material 10 to be etched, exposing the photoresist layer (11) using a mask on which a pattern is formed having a linewidth and spacing below the resolution limit of the photoresist layer (11), developing the exposed photoresist layer to form grooves in the surface of the exposed photoresist layer, filling the grooves with an etch-blocking material (12) which is resistant to oxygen reactive ion etching, etching the photoresist layer (11) by oxygen reactive ion etching using the etch blocking material (12) filling the grooves as a mask, and etching the material 10 using the pattern which is made of a photoresist layer and formed by the etching process, as a mask. <IMAGE>

Description

4 1 METHOD FOR FORMING A MICROPATTERN BELOW THE RESOLUTION LIMIT OF A
PHOTOLITHOGRAPHY PROCESS The present invention relates to a method f or forming a 'micropattern below the resolution limit of a photolithography process.
16M DRAMs having a 0.5gm, design rule, produced in preparation for commercial application, have passed performance tests in recent years, and will soon be available with a speedy arrangement for mass production. Along with this trend, studies are focusing on the succeeding generations of 64M DRAMs and 256M DRAMs. The design rule required for 64M DRAMs and 256M DRAMs are 0.3 to 0.4,4m and 0.2gm, respectively. Thus, it is reasonably certain that the development of these succeeding generations of DRAMs having higher packing densities will depend on developing high resolution photolithographic techniques which are capable of forming a micropattern below half-micron dimensions.
During the processing of 0.5Am DRAM devices, the wavelength used in photolithographic techniques has advanced from the g-line (436nm) to the shorter wavelength i-line (365nm). Also, a high resolutionconstant resist which is commonly used for the g-line and the i-line, and a chemically amplified-type resist i 4 2 have been presented for the photolithographic process. In addition, the formation technique of the multiplelevel resist structure instead of single resist structure has been introduced to obtain high contrast ratio.
However, during the processing of these devices at 0.5gm, the phenomenon of light diffraction in the photolithographic technique impedes the formation of a micropattern with linewidth and spacing below 0. 4gm. Therefore, KrF excimer laser apparatuses with a wavelength of 248nm, ArF excimer laser apparatuses of 193nm, and the like are presently being introduced to manuf acture 64M DRAMs with a f eature size of 0. 4 to 0. 3gm. The research in f orming micropatterns below the half -micron level using electron or X-ray beams is an intense area of activity, and necessitates the replacement of commonly used apparatus f or creating 0. 5gm devices with expensive new ones.
The present invention aims to provide a method for forming a micropattern below the resolution limit of a conventional photo 1 ithog raphic process, and in particular one which is capable of forming a micropattern at 0. 35gm, without changing the conventional photolithographic techniques or apparatus used in the formation of 0.5Am devices.
Another aim of the present invention is to 0.
1 3 provide a method for forming a micropattern below the resolution limit of a photolithographic process, which is economical due to the ability to form a micropattern without replacing the conventional photolithography apparatus used to form devices of 0. 5t4M.
Still another aim of the present invention is to provide a method for forming a micropattern below the resolution limit of a photolithographic process, which is capable of f orming a micropattern for succeeding generations of devices having higher packing densities using apparatus f or photolithography which are in common use.
According to present invention, there is provided a method for forming a micropattern below the resolution limit of a photolithographic process comprising the steps of:
covering a photoresist layer over a material to be etched; exposing said photoresist layer using a mask on which a pattern is f ormed having a linewidth and spacing below the resolution limit of said photoresist layer, and developing said exposed photoresist layer to form grooves in the superf icial portion of said exposed photoresist layer; filling said grooves with an etch-blocking 1 4 material which is resistant to oxygen reactive ion etching; etching said photoresist layer by oxygen reactive ion etching, using said etch-blocking material filling said grooves as a mask; and etching said material to be etched using said pattern as a mask which is made of a photoresist layer and formed by said oxygen reactive ion etching process.
Therefore, since a micropattern below the resolution limit can be formed using conventional apparatus for photolithography without their replacement, the method for forming a micropattern according to the present invention is very economical and overcomes the resolution limit.
For a better understanding of the invention, and to show how the same may be carried into ef f ect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:
Figure 1 is a graph showing the relationship between mask pattern size and photoresist pattern size; Figures 2A through 2D are SEM (Scanning Electron Micrograph) photographs of patterns of which the linewidths and spacings are 0.5gm, 0.45gm, 0.4gm and 0.35gm, respectively, obtained when the i-line (NA=0.45) is used; and Figures 3A through 3G illustrate a process for forming a micropattern below the resolution limit of a photolithographic process according to the present invention.
Figure 1 is a graph showing the linewidth linearity of mask pattern size versus photoresist pattern size which was obtained in practical application. As illustrated in Figure 1, the photoresist pattern in a conventional photoresist process was, for all practical purposes, completely transferred for mask patterns ranging in size from 1.Opm down to 0.6gm. However, the size of the photoresist pattern obtained with mask patterns having sizes from 0.5 to 0.4Am increased with respect to the mask pattern size, while the photoresist pattern was not formed for mask pattern sizes below 0.4Am.
Figures 2A through 2D are SEM photographs showing photoresist pattern configurations formed in practice, with linewidths and spacings of each pattern formed on the mask at 0.5Am, 0.45Am, 0.4Am and 0.35Am, respectively. As seen in Figure 2D, with mask linewidth and spacing at 0. 35Am, the photoresist pattern was imperfect.
In the present invention, when an imperfect pattern is formed below resolution limits as i.
1 6 illustrated, the incompletely formed pattern is covered with an organic/inorganic material other than a photoresist. Then the resultant surface is levelled by an etchback process. Thereafter, part of the remaining photoresist layer is removed by dry etching using the organic/ inorganic material which was not removed by the etchback process as a mask. Therefore, the imperfect pattern becomes completely formed. That is, the micropattern can be formed with dimensions below the resolution limit using the method of the present invention in which the imperfect pattern, below the resolution limit and lacking linewidth linearity caused by the restrictions of conventional photolithography facilities and processing, is completed by an etchback process and dry etching the photoresist.
The method of the present invention will now be described in more detail with reference to Figures 3A through 3G.
Referring to Figure 3A, the material to be etched, e.g., a semiconductor substrate 10, is first covered with a photoresist layer 11 having a predetermined thickness. Here, the material used to f orm the photoresist layer 11 may be a high-resolution photoresist including naphthoquinone compounds and novolac. resins, the latter being base resins, such as 1 A 7 is TSMR-V3 (Tokyo -Ohka-Kogyo, Co.), PFR GX100 (Nippon Synthetic Chemical Industry Co.), FH-6300 (Fuji Hunt, Co.), and MCPR 3000 (Mitsubishi Chemical, Co.) for the g-line (436nm), and for the i-line (365nm), TSMR365i and TSMR-i11OO (Tokyo-ohka-Kogyo, Co.). A chemically amplified-type photoresist can also be used.
Referring to Figure 3B, the photoresist layer 11 is then exposed through a mask 15 on which a pattern is formed having linewidth and spacing of dimensions below the resolution limit of the photoresist layer 11. According to the photoresist type used, a g-line stepper, an i-line stepper, a wideband (250nm to 460nm) stepper, an electron beam exposometer, an X-ray exposometer, or an excimer laser stepper may be used during the exposure. It is widely known that with current g-line steppers (NA=0.45), the resolution limit is 0.45gm, 0.40gm in the i-line stepper (NA=0.45), and 0.35gm in the excimer laser stepper (NA-0.45). Thus, when the g-line stepper (NA=0.45) is used, linewidth and spacing down to 0.3gm can be achieved, and with the excimer laser stepper (NA=0. 45), down to 0.2Am. Briefly, an imperfect pattern in the present invention is sufficient, provided that it has the desired linewidth and spacing in the superficial layer of the photoresist layer.
Referring to Figure 3C, the exposed photoresist i- A 8 layer 11 is next developed to f orm the imperfect pattern 14 with grooves 13 having the desired linewidth and spacing in the superficial layer of the photoresist layer 11.
Referring to Figure 3D, a layer of etch-blocking material 12 having a predetermined thickness is laid down on the photoresist layer 11 in which the grooves 13 are formed, to give a generally flat surface. Here, the etch-blocking material has a different etch rate from that of the photoresist layer 11 with respect to dry etching. For example, when an oxygen reactive ion etching method is used to etch the photoresist layer 11, the material is resistant to the oxygen reactive ion etching such as SOG (Spin-OnGlass) layer, a TEOS (Tetra-Ethyl-Ortho-Silicate) layer, or a PE-Oxide (Plasma Enhanced Oxide) layer. If the SOG layer is used as the etch-blocking material, it is preferable to bake and harden the photoresist layer 11 at a predetermined temperature of an optimum period of time, bef ore coating the SPG layer. With regard to the thickness of the etchblocking material it is sufficient for it to be more than approximately 3000A thick in the case of the SPG layer, and more than approximately 10001 thick in the case of the TEOS layer or the PE-Oxide layer.
Referring to Figure 3E, the layer of etch- 0.
1 9 blocking material 12 is then etched by a reactive ion etching method which is arranged to selectively etch the layer of the etch-blocking material, so that the etch-blocking material is removed down to the surface of the photoresist layer 11 but remains in the grooves 13.
Referring to Figure 3F, the uncovered photoresist layer 11 is dry-etched by a reactive ion etching method, using the etch-blocking material 12 filling the grooves 13 as a mask, thereby forming the desired micropattern below the photoresist resolution limit.
Finally, referring to Figure 3G, the material to be etched, e.g., the semiconductor substrate, is etched using the above-obtained micropattern as a mask, thereby forming the intended final micropattern. The following example is provided to further illustrate the present invention.
A photoresist layer of TSMR-i11OO (supplied from Tokyo-Ohka-Kogyo, Co.) was covered over a semiconductor substrate. The resolution limit of the TSMR-i11OO is about 0.5Am.
Then, an i-line (365nm) stepper with a numerical aperture value of 0.45 was used to expose the photoresist layer, using a mask on which a pattern was formed having a linewidth and spacing of 0.3gm. As a result of developing the exposed photoresist layer, 0.
i 1 3 grooves with a width of 0.351zm were formed in the superficial layer of the photoresist layer.
The grooved photoresist layer was baked and hardened at 2000C in a hot plate oven for 60 seconds.
Successively, an SOG layer with a thickness of 5000K was coated over the photoresist layer, then was baked and hardened at 1800C for 60 seconds.
The hard baked SOG layer was etched down to the surf ace of the photoresist layer, and remaining in the grooves only, by a reactive ion etching method where carbon tetraf luoride (CF4) was used as a main ingredient.
The photoresist layer was etched by oxygen reactive ion etching, using the SOG layer filling the grooves as a mask. Finally, a micropattern below resolution limit having a linewidth and spacing of 0.35Am was formed.
As described above, since a finer pattern, one below the micropattern at resolution limit formed by conventional photolithography facilities and processing, can be completed without replacing the facilities and processing, the method for forming the micropattern according to the present invention is very economical. For example, the techniques and facilities for forming a 0.5Am micropattern needed for 16M/DRAMS can also be used for 64M DRAMs requiring a I 11 0.35Am micropattern. Further, the present invention allows for the formation of a 0.2gm micropattern needed for 256M DRAMs, using a 0-35Am excimer laser stepper.
There are described above novel features which the skilled man will appreciate give rise to advantages. These are each independent aspects of the invention to be covered by the present application, irrespective of whether or not they are included within the scope of the following claims.
12

Claims (13)

CLAIMS:
1. A method f or f orming a micropattern below the resolution limit of a photolithographic process comprising the steps of: covering a photoresist layer over a material to be etched; exposing said photoresist layer using a mask on which a pattern is f ormed having a linewidth and spacing below the resolution limit of said photoresist layer, and developing said exposed photoresist layer to form grooves in the superf icial portion of said exposed photoresist layer; filling said grooves with an etchblocking material which is resistant to oxygen reactive ion etching; etching said photoresist layer by oxygen reactive ion etching, using said etch blocking material f illing said grooves as a mask; and etching said material to be etched using said pattern as a mask which is made of a photoresist layer and formed by said oxygen reactive ion etching process.
2. A method for forming a micropattern below the resolution limit of a photolithographic process as 1 1---- --- 13 claimed in claim 1, wherein said photoresist layer is formed of a high resolution photoresist having a resolution limit below sub-micron level.
3. A method f or f orming a micropattern below the resolution limit of a photolithographic process as claimed in claim 1, wherein novolac resins are used for forming said photoresist layer.
4. A method for forming a micropattern below the resolution limit of a photolithographic process as claimed in claim 1, wherein said photoresist layer is exposed by any one of a g-line (436nm), an i-line (365nm), and a wideband infrared ray of 250= to 460nn.
5. A method for forming a micropattern below the resolution limit of a photolithographic process as claimed in claim 1, wherein said photoresist layer is formed of a chemically amplified-type resist.
6. A method for forming a micropattern below the resolution limit of a photolithographic process as claimed in claim 1, wherein said photoresist layer is exposed by any one of an electron beam, an X-ray, and an excimer laser.
1 14
7. A method f or f orming a micropattern below the resolution limit of a photolithographic process as claimed in claim 1, wherein said layer of etchblocking material is any one of an SOG layer, a TEOS layer, and a PE- Oxide layer.
S. A method for forming a micropattern below the resolution limit of a photolithographic process as claimed in claim 1, wherein the step for filling said grooves is performed by covering said photoresist layer having said grooves thereon with an etchblocking material, to have a generally flattened surface, then removing said etch-blocking material by an etchback process down to the surface of said photoresist layer while leaving said etch-blocking material in said grooves only.
9. A method f or f orming a micropattern below the resolution limit of a photolithographic process comprising the steps of: covering a photoresist layer over a material to be etched; exposing said photoresist layer using a mask on which a pattern is formed having a linewidth and spacing below the resolution limit of said photoresist 0- i layer, and developing said exposed photoresist layer to form grooves in the superf icial portion of said exposed photoresist layer; covering said photoresist layer having grooves with an etch-blocking material, which is resistant to a first dry etching step, to a predetermined thickness and so as to have, a generally flattened surface; etching said etch-blocking material by a second dry etching step down to the surface of the photoresist layer while not etching in said grooves; etching said photoresist layer by an oxygen reactive ion etching method, using said etch-blocking material filling said grooves as a mask; and etching said material to be etched, using said pattern which is made of a photoresist layer and formed by said oxygen reactive ion etching process, as a mask.
10. A method for forming a micropattern below the resolution limit of a photolithographic process as claimed in claim 9, wherein said layer of etchblocking material is an SOG layer having a thickness of 30001 or more.
11. A semiconductor substrate manufactured in accordance with the method of any preceding claim.
i.
A 16
12. A method f or f orming a micropattern in a substrate using a photolithographic process, the micropattern having dimensions below the resolution limit of that process, wherein the method comprises the steps of covering the substrate with a photoresist layer, exposing the photoresist layer through a first mask having a pattern with dimensions smaller than the process resolution limit, developing the exposed photoresist to form a preliminary pattern in the superficial portion of the photoresist layer, using the preliminary pattern to f orm a correspondingly patterned second mask and removing the unmasked photoresist layer to expose the underlying substrate to thereby allow etching of said micropattern therein.
13. A method f or f orming a micropattern below the resolution limit of a photolithographic process substantially as hereinbef ore described with reference to Figure 3 of the accompanying drawings.
GB9117267A 1991-01-30 1991-08-09 Forming micropatterns in semiconductor substrates Withdrawn GB2252449A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001578A KR920015482A (en) 1991-01-30 1991-01-30 Micropattern forming method below the limit resolution of optical lithography

Publications (2)

Publication Number Publication Date
GB9117267D0 GB9117267D0 (en) 1991-09-25
GB2252449A true GB2252449A (en) 1992-08-05

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GB9117267A Withdrawn GB2252449A (en) 1991-01-30 1991-08-09 Forming micropatterns in semiconductor substrates

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JP (1) JPH04249311A (en)
KR (1) KR920015482A (en)
DE (1) DE4126635A1 (en)
FR (1) FR2672138A1 (en)
GB (1) GB2252449A (en)
IT (1) IT1251004B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4440230A1 (en) * 1993-11-10 1995-05-11 Hyundai Electronics Ind Method of forming fine semiconductor device patterns
GB2314209A (en) * 1996-06-12 1997-12-17 Lg Electronics Inc Method of forming a thin film transistor electrode with a tapered edge

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236609A1 (en) * 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
JP2000156377A (en) 1998-11-19 2000-06-06 Murata Mfg Co Ltd Resist pattern, its forming method and forming method of wiring pattern
JP5655443B2 (en) * 2010-09-06 2015-01-21 住友電気工業株式会社 Inorganic compound film etching method and semiconductor optical device manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260201A2 (en) * 1986-09-11 1988-03-16 Fairchild Semiconductor Corporation Plasma etching using a bilayer mask
EP0375066A1 (en) * 1988-12-22 1990-06-27 Koninklijke Philips Electronics N.V. A method of etching thin indium tin oxide films

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4634645A (en) * 1984-04-13 1987-01-06 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260201A2 (en) * 1986-09-11 1988-03-16 Fairchild Semiconductor Corporation Plasma etching using a bilayer mask
EP0375066A1 (en) * 1988-12-22 1990-06-27 Koninklijke Philips Electronics N.V. A method of etching thin indium tin oxide films

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4440230A1 (en) * 1993-11-10 1995-05-11 Hyundai Electronics Ind Method of forming fine semiconductor device patterns
GB2284300A (en) * 1993-11-10 1995-05-31 Hyundai Electronics Ind Process for forming fine patterns in semiconductor devices
GB2284300B (en) * 1993-11-10 1997-11-19 Hyundai Electronics Ind Process for forming fine pattern of semiconductor device
DE4440230C2 (en) * 1993-11-10 1999-03-18 Hyundai Electronics Ind Process for forming fine structures of a semiconductor device
GB2314209A (en) * 1996-06-12 1997-12-17 Lg Electronics Inc Method of forming a thin film transistor electrode with a tapered edge
GB2314209B (en) * 1996-06-12 1999-01-27 Lg Electronics Inc Liquid crystal displays
US6395457B1 (en) 1996-06-12 2002-05-28 Lg Electronics, Inc. Method for manufacturing a semiconductor device

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Publication number Publication date
ITMI912235A0 (en) 1991-08-09
IT1251004B (en) 1995-04-28
FR2672138A1 (en) 1992-07-31
GB9117267D0 (en) 1991-09-25
DE4126635A1 (en) 1992-08-13
KR920015482A (en) 1992-08-27
ITMI912235A1 (en) 1993-02-09
JPH04249311A (en) 1992-09-04

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