IT1250098B - RAM ABSORPTION REGULATION CIRCUIT FOR STATIC MEMORIES OF THE RAM TYPE. - Google Patents

RAM ABSORPTION REGULATION CIRCUIT FOR STATIC MEMORIES OF THE RAM TYPE.

Info

Publication number
IT1250098B
IT1250098B ITRM910698A ITRM910698A IT1250098B IT 1250098 B IT1250098 B IT 1250098B IT RM910698 A ITRM910698 A IT RM910698A IT RM910698 A ITRM910698 A IT RM910698A IT 1250098 B IT1250098 B IT 1250098B
Authority
IT
Italy
Prior art keywords
voltage
ram
unit
regulation circuit
current
Prior art date
Application number
ITRM910698A
Other languages
Italian (it)
Inventor
Su-Chul Lee
Chung-Geun Kwak
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITRM910698A0 publication Critical patent/ITRM910698A0/en
Publication of ITRM910698A1 publication Critical patent/ITRM910698A1/en
Application granted granted Critical
Publication of IT1250098B publication Critical patent/IT1250098B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Viene illustrato un circuito di regolazione di corrente per l'impiego in una schiera di celle di una memoria statiche RAM per ridurre il consumo di corrente e per consumare una corrente normale anche sotto condizioni di elevata temperatura ed alta tensione. Il circuito regolatore di corrente comprende una prima unità collegata in serie tra il terminale della sorgente di tensione di alimentazione ed il terminale di tensione di massa, per produrre una prima ed una seconda tensione in risposta ad un livello di tensione di sorgente di alimentazione, ed una seconda unità che viene accoppiata tra il terminale di sorgente di tensione di alimentazione e l'elemento di carico, per ricevere la prima o seconda tensione a seconda del fatto che la seconda unità lavori in una zona lineare quando viene erogata la prima tensione, e la seconda unità lavori in una zona di saturazione quando viene applicata la seconda tensione.A current regulating circuit for use in an array of cells of a static RAM memory is illustrated to reduce current consumption and to consume a normal current even under conditions of high temperature and high voltage. The current regulator circuit comprises a first unit connected in series between the supply voltage source terminal and the ground voltage terminal, to produce a first and a second voltage in response to a power source voltage level, and a second unit which is coupled between the supply voltage source terminal and the load element, to receive the first or second voltage depending on whether the second unit works in a linear zone when the first voltage is supplied, and the second unit works in a saturation zone when the second voltage is applied.

ITRM910698A 1990-09-19 1991-09-18 RAM ABSORPTION REGULATION CIRCUIT FOR STATIC MEMORIES OF THE RAM TYPE. IT1250098B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900014828A KR920006985A (en) 1990-09-19 1990-09-19 Static load control circuit

Publications (3)

Publication Number Publication Date
ITRM910698A0 ITRM910698A0 (en) 1991-09-18
ITRM910698A1 ITRM910698A1 (en) 1993-03-18
IT1250098B true IT1250098B (en) 1995-03-30

Family

ID=19303774

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM910698A IT1250098B (en) 1990-09-19 1991-09-18 RAM ABSORPTION REGULATION CIRCUIT FOR STATIC MEMORIES OF THE RAM TYPE.

Country Status (6)

Country Link
JP (1) JPH04132080A (en)
KR (1) KR920006985A (en)
DE (1) DE4037207A1 (en)
FR (1) FR2666913B1 (en)
GB (1) GB2248131A (en)
IT (1) IT1250098B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001143476A (en) 1999-11-15 2001-05-25 Mitsubishi Electric Corp Static semiconductor memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5828679B2 (en) * 1979-04-25 1983-06-17 富士通株式会社 Write circuit for semiconductor memory device
DE3004565C2 (en) * 1980-02-07 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Integrated digital semiconductor circuit
JPS57162181A (en) * 1981-03-31 1982-10-05 Fujitsu Ltd Semiconductor memory device
JPS58161195A (en) * 1982-03-19 1983-09-24 Fujitsu Ltd Static type semiconductor storage device
JPS5922295A (en) * 1982-06-30 1984-02-04 Fujitsu Ltd Semiconductor storage device
US4758994A (en) * 1986-01-17 1988-07-19 Texas Instruments Incorporated On chip voltage regulator for common collector matrix programmable memory array
US4857772A (en) * 1987-04-27 1989-08-15 Fairchild Semiconductor Corporation BIPMOS decoder circuit
US4874967A (en) * 1987-12-15 1989-10-17 Xicor, Inc. Low power voltage clamp circuit
KR910004736B1 (en) * 1988-12-15 1991-07-10 삼성전자 주식회사 Power voltage control circuit of static memory device
JPH02177084A (en) * 1988-12-27 1990-07-10 Mitsubishi Electric Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
DE4037207C2 (en) 1993-08-19
FR2666913A1 (en) 1992-03-20
KR920006985A (en) 1992-04-28
FR2666913B1 (en) 1993-12-10
GB9111468D0 (en) 1991-07-17
GB2248131A (en) 1992-03-25
DE4037207A1 (en) 1992-04-02
JPH04132080A (en) 1992-05-06
ITRM910698A1 (en) 1993-03-18
ITRM910698A0 (en) 1991-09-18

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Legal Events

Date Code Title Description
0001 Granted