GB2248131A - Current limiting circuit for a static ram - Google Patents
Current limiting circuit for a static ram Download PDFInfo
- Publication number
- GB2248131A GB2248131A GB9111468A GB9111468A GB2248131A GB 2248131 A GB2248131 A GB 2248131A GB 9111468 A GB9111468 A GB 9111468A GB 9111468 A GB9111468 A GB 9111468A GB 2248131 A GB2248131 A GB 2248131A
- Authority
- GB
- United Kingdom
- Prior art keywords
- voltage
- regulating
- limiting circuit
- current limiting
- regulating means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Abstract
A currents limiting circuit 20 for a static random access memory device having a plurality of high resistance cells 10 has a first regulating means 27 connected to the voltage source (Vcc) and a second regulating means 25 connected between the voltage source and the load element (memory cells 10). A regulating voyage is generated by said first regulating means if the source voltage is greater than a predetermined level (determined by the number and threshold of FRT0 21, 22) and upon receiving the regulating voltage, the second regulating means limits current supplied to the load elements. <IMAGE>
Description
CURRENT LIMITING CIRCUIT FOR A STATIC RAM
The present invention relates to a current limiting circuit for a static random access memory device, referred to herein as a RAM.
A typical static RAM is fabricated from a plurality of memory cells, wherein each cell includes two transistors for passing data, two transistors for charging and discharging and a load element supplying power from a voltage source, to memory nodes.
Referring to Figure 1, a high resistance load-type static RAM cell having the aforesaid elements is illustrated, in which the data passing transistors 3, 4 are connected to a word line WL, and bit lines BL are connected to memory nodes 13, 14 respectively. The gates and a channel of the charging and discharging transistors 1 and 2 are cross-coupled in the form of a flip-flop and are also connected to the memory nodes 13, 14. Since the transistors 1 and 2 form a latch circuit, the potential of the memory nodes 13, 14 is constant at all times. Bteween the memory nodes 13, 14 and a power source voltage terminal 11, resistors 5 and 6, used as load elements, are coupled; resistors 5 and 6 usually have a very high resistance.
A conventional cell array, formed by arranging a plurality of static
RAM cells of the type shown in Figure 1, is illustrated in Figure 2. The overall current consumption of the array, when the memory chip is in a standy-by condition, may be derived by multiplying the current Vcc/R (where
Vcc is the power source voltage and R is the value of the resistors 5 and 6) flowing to the ground terminal 12 through the resistors 5 and 6 and the channel of the transistors 1 or 2 in the static RAM cell of Figure 1, by the number of cells.
When the chip operates at a low temperature, the current consumption decreases because the resistance R is high, however, the resistance decreases when the temperature rises and, consequently, current consumption increases when the resistance decreases. In addition, the current consumption will also increase with increases in the level of the supply voltage.
In order to solve this problem, it is known to increase the load resistance, however, such an approach becomes detrimental to the effectiveness of the device's data storage capabilities. Furthermore, such a solution is not very effective at higher operating temperatures.
According to a first aspect of the invention, there is provided a current limiting circuit for a static random access memory device (RAM), said RAM having a plurality of load elements in the form of high resistance cells and a voltage source; said circuit comprising a first regulating means connected to said voltage source, a second regulating means connected between said voltage source and said load elements, wherein a regulating voltage is generated by said first regulating means if said source voltage is greater than a predetermined level and said second regulating means limits current supply to said load elements upon receiving said regulating voltage.
Preferably, said second regulating means operates substantially linearly under normal operating conditions and said second regulating means operates substantially non-linearly on receiving said regulating voltage. In a preferred embodimentj- said second regulating means is a metal oxide silicon (MOS) transistor, which may be arranged to operate in its saturated region when said regulating voltage is generated.
According to a second aspect of the invention, there is provided a static
RAM cell array, comprising: a plurality of memory cells having a load element of high resistance connected to a power source voltage; and a circuit coupled between said power source voltage and a load element, for adjusting current flowing through said load element.
In a preferred embodiment, said current adjusting circuit comprises voltage dropping means and a pull-down resistor coupled in series between said power source voltage and ground voltage; a node coupled between said voltage dropping means and said pull-down resistor; and a P-MOS transistor, wherein the gate of said transistor is connected to said node and the channel of said transistor is connected between said load element and the power source voltage.
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example only, to the accompanying diagrammatic drawings in which:
Figure 1 is a circuit diagram of a known arrangement of static RAM cells;
Figure 2 is a schematic diagram of a known memory cell array;
Figure 3 is a block diagram showing the construction of a memory cell array embodying the present invention, having a current adjusting circuit;
Figure 4 details the current adjusting circuit shown in Figure 3, having a P-MOS transistor; and,
Figure 5 illustrates the operating characteristics of the transistor shown in Figure 4.
Figure 3 is a block diagram showing the construction of a memory cell array embodying the present invention, in which a plurality of static RAM cells 10 are arranged in a matrix and a current limiting circuit 20 is disposed between a power source voltage terminal 11 and memory cells 10. The current limiting circuit 20 limits the supply of current by adjusting the power source voltage applied to all memory cells 10, thus compensating for fluctuations in the power source voltage.
Referring to Figure 4, in which the current limiting circuit 20 of Figure 3 is illustrated in detail and includes a voltage dropping unit 27, in which a number of diode N-MOS transistors 21, 22, having respective gates and drains cownmonly connected to the power source voltage terminal 11, tare complected in series. A pull-down resistor 24 is connected between the source of the N
MOS transistor 22, located at the end of the voltage dropping unit 27 and ground voltage terminal 12. A node 23 is located between the source of the
N-MOS transistor 22 and the pull-down resistor 24 and is coupled to a gate of a P-MOS transistor 25.The source and substrate of the P-MOS transistor 25 are connected to the power source voltage terminal 11 and a drain of the
P-MOS transistor 25 is connected to the resistors 5, 6 of Figure 1, to the internal voltage terminal 26.
The N-MOS transistors 21, 22 of the voltage dropping unit 27 function like diodes, by connecting gates to drains and sources to the bulk regions of the substrates. Since these N-MOS transistors 21, 22 are for power source voltage dropping, they can also be formed from other elements. Similarly, since the P-MOS transistor 25 is for restricting the amount of current flowing through the channel in response to the amount of voltage applied to the gate, it can also be formed of other elements which are functionally suitable therefor.
Figure 5 is a graph showing the current-voltage characteristics of the
P-MOS transistor 25 shown in Figure 4 and shows a relationship between drain-source voltage VDS and drain-source current IDS on a gate-source voltage Vas curve. Current restriction or adjustment according to the present invention will be described with reference to the structure described above and to the graph shown in Figure 5.
The diode N-MOS transistors 21, 22, of the voltage dropping unit 27 connected to the power source voltage terminal 11, drop the power source voltage Vcc by as much as the sum of the threshold voltages VTH of all of the transistors present. Thus, if N N-MOS transistors are connected in series, the potential of the node 23 amounts to: (vice - N) x VTH
Therefore, when the level of the power source voltage is lower than N
X Vm, node 23 is cut off from the power source voltage terminal, so that the node 23 is connected to ground through the pull-down resistor 24, pulling the gate-source voltage VGS to - Vcc, on curve 51 of Figure 5.At this position, the P-MOS transistor 25 is operating in its linear region L51,therefore as voltage increases, linear current IDSL through internal voltage terminal 26 also increases. This result is produced by the property of the gate-source voltage V05 of the P-MOS transistor 25 that is to say, the more it goes to negative voltage linearly, the more it lets channel current flow. In this case, the drainsource current IDSL of the P-MOS transistor 25 will increase until it reaches a saturation region S51 on the curve 51.
Conversely, when the level of the power source voltage is higher than
N x Vm, the potential of the node 23 attains to Vcc - N x VTH, and the gatesource voltage Vos of the P-MOS transistor 25 attains to - N x Vm (on curve 52 of Figure 5) because the voltage at the source terminal is Vcc. As this voltage is enough to operate the P-MOS transistor 25 into the saturation region S52, it makes almost no more drain-source current (saturation current Ides) flow. In other words, when the level of the power source voltage which comes in from the outside is low, the amount of current which is applied to the inside memory cells is increased by operating the P-MOS transistor 25 in its linear region.However, when the level of the power source voltage is high, no additional current flows by the operation of the P-MOS transistor 25 in its saturated region, so that a stable internal voltage will be applied to the resistors 5, 6 of Figure 1.
The amount of voltage drop by the voltage dropping unit 27 and the margin of current restriction by the P-MOS transistor 25 can be adjusted by the number and size of corresponding transistors. Although a P-MOS transistor 25 is used for current adjustment in the preferred embodiment, an
N-MOS transistor can also be used.
As previously stated, there are also instances when the temperature of the integrated circuit rises. This is largely due to the level of power source voltage rising and the resistor of resistance lines within the circuit becoming overheated. The present invention will be conducive to the stabilisation of internally operating voltages necessary for memory cells when the power source voltage rises and the temperature goes up.
As described hereinabove, the present invention has the effect of reducing unnecessary current consumption and maintaining internally operating voltages on a stabilised basis, even in the case where outside power source voltage and temperature rise in a static RAM cell array.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (12)
1. A current limiting circuit for a static random access memory device (RAM), said RAM having a plurality of load elements in the form of high resistance cells and a voltage source;
said circuit comprising:
a first regulating means connected to said voltage source,
a second regulating means connected between said voltage source and said load elements,
wherein a regulating voltage is generated by said first regulating means if said source voltage is greater than a predetermined level
and said second regulating means limits current supply to said load elements upon receiving said regulating voltage.
2. A current limiting circuit according to Claim 1, wherein said second regulating means operates substantially linearly under normal operating conditions and said second regulating means operates substantially non-linearly upon receiving said regulating voJ.^age.
3. A current limiting circuit according to Claim 2, wherein said second regulating means operates in a saturated region of its operating characteristic when said regulating voltage is generated.
4. A current limiting circuit according to any of Claims 1 to 3, wherein said second regulating means is a metal oxide silcon (MOS) transistor.
5. A current limiting circuit according to Claim 4, wherein said MOS transistor is a P-MOS transistor.
6. A current limiting circuit according to any of Claims 1 to 5, wherein said first regulating means is a voltage threshold detecting means arranged to generate a regulating voltage when the supply voltage exceeds a predetermined threshold.
7. A current limiting circuit according to Claim 6, wherein said voltage threshold detector is a series of forwardly biased semiconductor devices arranged to provide a voltage drop equivalent to said threshold.
8. A static RAM cell array, comprising:
a plurality of memory cells having a load element of high resistance connected to a power source voltage; and
a circuit coupled between said power source voltage and a load element, for adjusting current flowing through said load element.
9. A static RAM cell array according to Claim 8, wherein said current adjusting circuit comprises:
voltage dropping means and a pull-down resistor coupled in series between said power source voltage and ground voltage;
a node coupled between said voltage dropping means and said pulldown resistor; and
a P-MOS transistor, wherein the gate of said transistor is connected to said node and the channel of said transistor is connected between said node element and the power source voltage.
10. A static RAM cell array according to Claim 9, wherein said node produces a first voltage when a level of said power source voltage is lower than a predetermined value and said node produces a second voltage when the level of said power source voltage is higher than said predetermined value.
11. A static RAM cell array according to Claim 9, wherein said P
MOS transistor operates in a linear region when a potential of said node is of the first voltage and operates in a saturation region when the potential of said node is of the second voltage.
12. A current limiting circuit for a static random access memory device, substantially as herein described with reference to Figures 3 and 4.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900014828A KR920006985A (en) | 1990-09-19 | 1990-09-19 | Static load control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9111468D0 GB9111468D0 (en) | 1991-07-17 |
| GB2248131A true GB2248131A (en) | 1992-03-25 |
Family
ID=19303774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9111468A Withdrawn GB2248131A (en) | 1990-09-19 | 1991-05-28 | Current limiting circuit for a static ram |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH04132080A (en) |
| KR (1) | KR920006985A (en) |
| DE (1) | DE4037207A1 (en) |
| FR (1) | FR2666913B1 (en) |
| GB (1) | GB2248131A (en) |
| IT (1) | IT1250098B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316812B1 (en) | 1999-11-15 | 2001-11-13 | Mitsubishi Denki Kabushiki Kaisha | Static semiconductor memory device with expanded operating voltage range |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0034712A2 (en) * | 1980-02-07 | 1981-09-02 | Siemens Aktiengesellschaft | Integrated digital semi-conductor circuit |
| US4758994A (en) * | 1986-01-17 | 1988-07-19 | Texas Instruments Incorporated | On chip voltage regulator for common collector matrix programmable memory array |
| WO1989006068A1 (en) * | 1987-12-15 | 1989-06-29 | Xicor, Inc. | Low power voltage clamp circuit |
| NL8902985A (en) * | 1988-12-15 | 1990-07-02 | Samsung Electronics Co Ltd | STATIC ANY ACCESSIBLE MEMORY. |
| JPH02177084A (en) * | 1988-12-27 | 1990-07-10 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5828679B2 (en) * | 1979-04-25 | 1983-06-17 | 富士通株式会社 | Write circuit for semiconductor memory device |
| JPS57162181A (en) * | 1981-03-31 | 1982-10-05 | Fujitsu Ltd | Semiconductor memory device |
| JPS58161195A (en) * | 1982-03-19 | 1983-09-24 | Fujitsu Ltd | Static type semiconductor storage device |
| JPS5922295A (en) * | 1982-06-30 | 1984-02-04 | Fujitsu Ltd | Semiconductor storage device |
| US4857772A (en) * | 1987-04-27 | 1989-08-15 | Fairchild Semiconductor Corporation | BIPMOS decoder circuit |
-
1990
- 1990-09-19 KR KR1019900014828A patent/KR920006985A/en not_active IP Right Cessation
- 1990-11-22 DE DE4037207A patent/DE4037207A1/en active Granted
- 1990-11-26 FR FR9014733A patent/FR2666913B1/en not_active Expired - Fee Related
- 1990-11-28 JP JP2323353A patent/JPH04132080A/en active Pending
-
1991
- 1991-05-28 GB GB9111468A patent/GB2248131A/en not_active Withdrawn
- 1991-09-18 IT ITRM910698A patent/IT1250098B/en active IP Right Grant
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0034712A2 (en) * | 1980-02-07 | 1981-09-02 | Siemens Aktiengesellschaft | Integrated digital semi-conductor circuit |
| US4758994A (en) * | 1986-01-17 | 1988-07-19 | Texas Instruments Incorporated | On chip voltage regulator for common collector matrix programmable memory array |
| WO1989006068A1 (en) * | 1987-12-15 | 1989-06-29 | Xicor, Inc. | Low power voltage clamp circuit |
| NL8902985A (en) * | 1988-12-15 | 1990-07-02 | Samsung Electronics Co Ltd | STATIC ANY ACCESSIBLE MEMORY. |
| US4964084A (en) * | 1988-12-15 | 1990-10-16 | Samsung Electronics Co., Ltd. | Static random access memory device with voltage control circuit |
| JPH02177084A (en) * | 1988-12-27 | 1990-07-10 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316812B1 (en) | 1999-11-15 | 2001-11-13 | Mitsubishi Denki Kabushiki Kaisha | Static semiconductor memory device with expanded operating voltage range |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9111468D0 (en) | 1991-07-17 |
| JPH04132080A (en) | 1992-05-06 |
| ITRM910698A0 (en) | 1991-09-18 |
| DE4037207C2 (en) | 1993-08-19 |
| DE4037207A1 (en) | 1992-04-02 |
| IT1250098B (en) | 1995-03-30 |
| ITRM910698A1 (en) | 1993-03-18 |
| FR2666913A1 (en) | 1992-03-20 |
| KR920006985A (en) | 1992-04-28 |
| FR2666913B1 (en) | 1993-12-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |