IT1225631B - Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati. - Google Patents

Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati.

Info

Publication number
IT1225631B
IT1225631B IT8883682A IT8368288A IT1225631B IT 1225631 B IT1225631 B IT 1225631B IT 8883682 A IT8883682 A IT 8883682A IT 8368288 A IT8368288 A IT 8368288A IT 1225631 B IT1225631 B IT 1225631B
Authority
IT
Italy
Prior art keywords
tapering
holes
dielectric layers
integrated devices
form contacts
Prior art date
Application number
IT8883682A
Other languages
English (en)
Other versions
IT8883682A0 (it
Inventor
Pier Luigi Crotti
Nadia Iazzi
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8883682A priority Critical patent/IT1225631B/it
Publication of IT8883682A0 publication Critical patent/IT8883682A0/it
Priority to EP89830492A priority patent/EP0369953B1/en
Priority to DE68914099T priority patent/DE68914099T2/de
Priority to US07/435,890 priority patent/US5227014A/en
Priority to JP1298747A priority patent/JPH02183534A/ja
Application granted granted Critical
Publication of IT1225631B publication Critical patent/IT1225631B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
IT8883682A 1988-11-16 1988-11-16 Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati. IT1225631B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8883682A IT1225631B (it) 1988-11-16 1988-11-16 Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati.
EP89830492A EP0369953B1 (en) 1988-11-16 1989-11-13 Tapering of holes through dielectric layers for forming contacts in integrated devices
DE68914099T DE68914099T2 (de) 1988-11-16 1989-11-13 Flankenabschrägen von Löchern durch dielektrische Schichten zur Erzeugung von Kontakten in integrierten Schaltkreisen.
US07/435,890 US5227014A (en) 1988-11-16 1989-11-14 Tapering of holes through dielectric layers for forming contacts in integrated devices
JP1298747A JPH02183534A (ja) 1988-11-16 1989-11-16 集積デバイス中に接点を形成するために絶縁層を通してテーパー状のホールを形成する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8883682A IT1225631B (it) 1988-11-16 1988-11-16 Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati.

Publications (2)

Publication Number Publication Date
IT8883682A0 IT8883682A0 (it) 1988-11-16
IT1225631B true IT1225631B (it) 1990-11-22

Family

ID=11323793

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8883682A IT1225631B (it) 1988-11-16 1988-11-16 Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati.

Country Status (5)

Country Link
US (1) US5227014A (it)
EP (1) EP0369953B1 (it)
JP (1) JPH02183534A (it)
DE (1) DE68914099T2 (it)
IT (1) IT1225631B (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996167A (en) * 1990-06-29 1991-02-26 At&T Bell Laboratories Method of making electrical contacts to gate structures in integrated circuits
DE4331549A1 (de) * 1993-09-16 1995-04-13 Gold Star Electronics Verfahren zur Herstellung einer ULSI-Halbleitereinrichtung
US5756397A (en) * 1993-12-28 1998-05-26 Lg Semicon Co., Ltd. Method of fabricating a wiring in a semiconductor device
KR0151048B1 (ko) * 1995-05-24 1998-12-01 김광호 반도체 장치의 접촉창 형성방법
US5686354A (en) * 1995-06-07 1997-11-11 Advanced Micro Devices, Inc. Dual damascene with a protective mask for via etching
US5567270A (en) * 1995-10-16 1996-10-22 Winbond Electronics Corp. Process of forming contacts and vias having tapered sidewall
US6111319A (en) 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US5883006A (en) * 1997-12-12 1999-03-16 Kabushiki Kaisha Toshiba Method for making a semiconductor device using a flowable oxide film
TW449828B (en) * 1998-08-24 2001-08-11 United Microelectronics Corp Method for etching oxide layer with a medium/low plasma density
US7531367B2 (en) * 2006-01-18 2009-05-12 International Business Machines Corporation Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
JPS6058635A (ja) * 1983-09-12 1985-04-04 Toshiba Corp 半導体装置の製造方法
JPS6126240A (ja) * 1984-07-17 1986-02-05 Hitachi Ltd 絶縁分離方法
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
US4657628A (en) * 1985-05-01 1987-04-14 Texas Instruments Incorporated Process for patterning local interconnects
US4660278A (en) * 1985-06-26 1987-04-28 Texas Instruments Incorporated Process of making IC isolation structure
JPH0789562B2 (ja) * 1985-11-01 1995-09-27 富士通株式会社 集積回路の素子分離方法
US4755476A (en) * 1985-12-17 1988-07-05 Siemens Aktiengesellschaft Process for the production of self-adjusted bipolar transistor structures having a reduced extrinsic base resistance
US4707218A (en) * 1986-10-28 1987-11-17 International Business Machines Corporation Lithographic image size reduction
JPS63293946A (ja) * 1987-05-27 1988-11-30 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH02183534A (ja) 1990-07-18
EP0369953A1 (en) 1990-05-23
DE68914099D1 (de) 1994-04-28
US5227014A (en) 1993-07-13
DE68914099T2 (de) 1994-07-07
IT8883682A0 (it) 1988-11-16
EP0369953B1 (en) 1994-03-23

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129