IT1037558B - Metodo di fabbricazione di un dispositivo smemiconduttore - Google Patents

Metodo di fabbricazione di un dispositivo smemiconduttore

Info

Publication number
IT1037558B
IT1037558B IT22591/75A IT2259175A IT1037558B IT 1037558 B IT1037558 B IT 1037558B IT 22591/75 A IT22591/75 A IT 22591/75A IT 2259175 A IT2259175 A IT 2259175A IT 1037558 B IT1037558 B IT 1037558B
Authority
IT
Italy
Prior art keywords
smemiconducting
manufacturing
smemiconducting device
Prior art date
Application number
IT22591/75A
Other languages
English (en)
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Application granted granted Critical
Publication of IT1037558B publication Critical patent/IT1037558B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Photovoltaic Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT22591/75A 1974-04-25 1975-04-21 Metodo di fabbricazione di un dispositivo smemiconduttore IT1037558B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB18165/74A GB1501114A (en) 1974-04-25 1974-04-25 Method of making a semiconductor device

Publications (1)

Publication Number Publication Date
IT1037558B true IT1037558B (it) 1979-11-20

Family

ID=10107783

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22591/75A IT1037558B (it) 1974-04-25 1975-04-21 Metodo di fabbricazione di un dispositivo smemiconduttore

Country Status (10)

Country Link
US (1) US3980507A (it)
JP (1) JPS50145081A (it)
BE (1) BE828188A (it)
CA (1) CA1050866A (it)
DE (1) DE2517690B2 (it)
FR (1) FR2269199A1 (it)
GB (1) GB1501114A (it)
IN (1) IN144756B (it)
IT (1) IT1037558B (it)
SE (1) SE407307B (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026733A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for defining polycrystalline silicon patterns
NL7612883A (nl) * 1976-11-19 1978-05-23 Philips Nv Halfgeleiderinrichting, en werkwijze ter ver- vaardiging daarvan.
DE2751481C2 (de) * 1976-11-22 1986-10-23 Mostek Corp. (n.d.Ges.d.Staates Delaware), Carrollton, Tex. Lastimpedanz für eine statische Halbleiterspeicherzelle
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
US4050967A (en) * 1976-12-09 1977-09-27 Rca Corporation Method of selective aluminum diffusion
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
US4201603A (en) * 1978-12-04 1980-05-06 Rca Corporation Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon
US4249968A (en) * 1978-12-29 1981-02-10 International Business Machines Corporation Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
FR2472268A1 (fr) * 1979-12-21 1981-06-26 Thomson Csf Procede de formation de caisson dans des circuits integres
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
US4372803A (en) * 1980-09-26 1983-02-08 The United States Of America As Represented By The Secretary Of The Navy Method for etch thinning silicon devices
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
FR2515427A1 (fr) * 1981-10-27 1983-04-29 Efcis Procede de fabrication de resistances de forte valeur pour circuits integres
US4868631A (en) * 1985-11-18 1989-09-19 Texas Instruments Incorporated Bipolar transistor with shallow junctions and capable of high packing density
JPS63184364A (ja) * 1987-01-27 1988-07-29 Toshiba Corp 半導体装置の製造方法
KR900005871B1 (ko) * 1987-09-21 1990-08-13 삼성전자 주식회사 반도체 메모리소자의 제조방법
US5136344A (en) * 1988-11-02 1992-08-04 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
DE68903951T2 (de) * 1989-08-16 1993-07-08 Ibm Verfahren fuer die herstellung mikromechanischer messfuehler fuer afm/stm-profilometrie und mikromechanischer messfuehlerkopf.
KR0167271B1 (ko) * 1995-11-30 1998-12-15 문정환 비균등 도우프 채널 구조를 갖는 반도체소자의 제조방법
US5869399A (en) * 1997-08-07 1999-02-09 Mosel Vitelic Inc. Method for increasing utilizable surface of rugged polysilicon layer in semiconductor device
US7247578B2 (en) * 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
WO2017007554A2 (en) * 2015-06-09 2017-01-12 Georgia Tech Research Corporation Devices with organic semiconductor layers electrically-doped over a controlled depth

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3160539A (en) * 1958-09-08 1964-12-08 Trw Semiconductors Inc Surface treatment of silicon
US3675319A (en) * 1970-06-29 1972-07-11 Bell Telephone Labor Inc Interconnection of electrical devices
US3738880A (en) * 1971-06-23 1973-06-12 Rca Corp Method of making a semiconductor device
JPS498181A (it) * 1972-05-10 1974-01-24
US3846198A (en) * 1972-10-02 1974-11-05 Rca Corp Method of making semiconductor devices having thin active regions of the semiconductor material
US3847687A (en) * 1972-11-15 1974-11-12 Motorola Inc Methods of forming self aligned transistor structure having polycrystalline contacts
US3830665A (en) * 1972-12-07 1974-08-20 Motorola Inc Method for delineating semiconductor junctions

Also Published As

Publication number Publication date
CA1050866A (en) 1979-03-20
US3980507A (en) 1976-09-14
BE828188A (fr) 1975-08-18
FR2269199A1 (it) 1975-11-21
DE2517690B2 (de) 1979-05-17
SE7504757L (sv) 1975-10-27
SE407307B (sv) 1979-03-19
GB1501114A (en) 1978-02-15
JPS50145081A (it) 1975-11-21
DE2517690A1 (de) 1975-11-13
IN144756B (it) 1978-07-01

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