IT1034642B - Apparecchio per prova di reti logiche - Google Patents

Apparecchio per prova di reti logiche

Info

Publication number
IT1034642B
IT1034642B IT21728/75A IT2172875A IT1034642B IT 1034642 B IT1034642 B IT 1034642B IT 21728/75 A IT21728/75 A IT 21728/75A IT 2172875 A IT2172875 A IT 2172875A IT 1034642 B IT1034642 B IT 1034642B
Authority
IT
Italy
Prior art keywords
equipment
testing logic
logic networks
networks
testing
Prior art date
Application number
IT21728/75A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1034642B publication Critical patent/IT1034642B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
IT21728/75A 1974-05-08 1975-03-27 Apparecchio per prova di reti logiche IT1034642B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/468,108 US3961250A (en) 1974-05-08 1974-05-08 Logic network test system with simulator oriented fault test generator

Publications (1)

Publication Number Publication Date
IT1034642B true IT1034642B (it) 1979-10-10

Family

ID=23858461

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21728/75A IT1034642B (it) 1974-05-08 1975-03-27 Apparecchio per prova di reti logiche

Country Status (9)

Country Link
US (1) US3961250A (it)
JP (1) JPS5647509B2 (it)
AU (1) AU8053975A (it)
CA (1) CA1039813A (it)
DE (1) DE2515297A1 (it)
FR (1) FR2270596B1 (it)
GB (1) GB1478438A (it)
IT (1) IT1034642B (it)
NL (1) NL7505441A (it)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066882A (en) * 1976-08-16 1978-01-03 Grumman Aerospace Corporation Digital stimulus generating and response measuring means
JPS53119642A (en) * 1977-03-29 1978-10-19 Fujitsu Ltd Testing equipment for logic circuit
US4176780A (en) * 1977-12-06 1979-12-04 Ncr Corporation Method and apparatus for testing printed circuit boards
US4242751A (en) * 1978-08-28 1980-12-30 Genrad, Inc. Automatic fault-probing method and apparatus for checking electrical circuits and the like
US4228537A (en) * 1978-08-29 1980-10-14 Genrad, Inc. Method of and apparatus for automatic fault diagnosis of electrical circuits employing on-line simulation of faults in such circuits during diagnosis
US4204633A (en) * 1978-11-20 1980-05-27 International Business Machines Corporation Logic chip test system with path oriented decision making test pattern generator
JPS5585265A (en) * 1978-12-23 1980-06-27 Toshiba Corp Function test evaluation device for integrated circuit
US4459695A (en) * 1979-11-07 1984-07-10 Davy Mcgee (Sheffield) Limited Fault finding in an industrial installation by means of a computer
FR2498849B1 (fr) * 1981-01-26 1986-04-25 Commissariat Energie Atomique Generateur de signaux logiques combines
FR2501867A1 (fr) * 1981-03-11 1982-09-17 Commissariat Energie Atomique Systeme de test de la defaillance ou du bon fonctionnement d'un circuit a composants logiques
FR2531230A1 (fr) * 1982-07-27 1984-02-03 Rank Xerox Sa Ensemble destine au test automatique centralise de circuits imprimes et procede de test de circuits a microprocesseur faisant application de cet ensemble
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures
DE3485560D1 (de) * 1983-10-17 1992-04-16 British Telecomm System zur testerzeugung fuer digitalschaltungen.
US4594677A (en) * 1983-11-09 1986-06-10 International Business Machines Corporation System for detecting and diagnosing noise caused by simultaneous current switching
EP0177572A4 (en) * 1984-04-06 1986-09-22 Advanced Micro Devices Inc ACTIVE LEAK RESISTANCE CONTROL TO IMPROVE DIGITAL CONVERGENCE IN AN ELECTRONIC CIRCUIT SIMULATOR WHICH IS LOOKING FOR HYPERACTIVE CIRCUIT SOLUTIONS.
US4633417A (en) * 1984-06-20 1986-12-30 Step Engineering Emulator for non-fixed instruction set VLSI devices
JPS6142040A (ja) * 1984-08-03 1986-02-28 Nec Corp 論理シミユレ−タ
US4716564A (en) * 1985-11-15 1987-12-29 Tektronix, Inc. Method for test generation
JPH0743733B2 (ja) * 1985-12-11 1995-05-15 株式会社日立製作所 論理シミュレーション方法
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
US4726023A (en) * 1986-05-14 1988-02-16 International Business Machines Corporation Determination of testability of combined logic end memory by ignoring memory
US5126966A (en) * 1986-06-25 1992-06-30 Ikos Systems, Inc. High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
US4759019A (en) * 1986-07-10 1988-07-19 International Business Machines Corporation Programmable fault injection tool
FR2605112B1 (fr) * 1986-10-10 1989-04-07 Thomson Csf Dispositif et procede de generation de vecteurs de test et procede de test pour circuit integre
US4792913A (en) * 1986-11-03 1988-12-20 Grumman Aerospace Corporation Simulator for systems having analog and digital portions
EP0308660B1 (de) * 1987-09-22 1995-05-24 Siemens Aktiengesellschaft Vorrichtung zur Herstellung einer testkompatiblen, weitgehend fehlertoleranten Konfiguration von redundant implementierten systolischen VLSI-Systemen
US5257268A (en) * 1988-04-15 1993-10-26 At&T Bell Laboratories Cost-function directed search method for generating tests for sequential logic circuits
US5095483A (en) * 1989-04-28 1992-03-10 International Business Machines Corporation Signature analysis in physical modeling
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
DE69212673T2 (de) * 1991-03-14 1997-03-13 Matsushita Electric Ind Co Ltd Prüfmustererzeugungseinrichtung
US5602856A (en) * 1993-04-06 1997-02-11 Nippon Telegraph And Telephone Corporation Test pattern generation for logic circuits with reduced backtracking operations
JPH06334513A (ja) * 1993-05-13 1994-12-02 Intel Corp データ処理装置
US5633813A (en) * 1994-05-04 1997-05-27 Srinivasan; Seshan R. Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits
US5920485A (en) * 1996-12-05 1999-07-06 Hewlett-Packard Method of selecting gates for efficient code generation by a circuit compiler
US5896399A (en) * 1996-12-11 1999-04-20 International Business Machines Corporation System and method for testing self-timed memory arrays
JP2982741B2 (ja) * 1997-05-13 1999-11-29 日本電気株式会社 集積回路の故障診断装置及びその記録媒体
JPH11154103A (ja) * 1997-11-20 1999-06-08 Mitsubishi Electric Corp 半導体集積回路装置
JP4488595B2 (ja) * 2000-06-08 2010-06-23 株式会社アドバンテスト テストパターン生成方法
US6618826B1 (en) * 2000-10-26 2003-09-09 Cadence Design Systems, Inc. Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs
GB2377517A (en) * 2001-07-13 2003-01-15 Sun Microsystems Inc Apparatus and method for testing computer equipment for use in networks
WO2009050805A1 (ja) * 2007-10-18 2009-04-23 Fujitsu Limited 論理回路モデルの検証方法及び装置
JP7214440B2 (ja) * 2018-11-01 2023-01-30 三菱重工エンジニアリング株式会社 検証処理装置、検証処理方法及びプログラム

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614608A (en) * 1969-05-19 1971-10-19 Ibm Random number statistical logic test system

Also Published As

Publication number Publication date
JPS5647509B2 (it) 1981-11-10
GB1478438A (en) 1977-06-29
AU8053975A (en) 1976-10-28
US3961250A (en) 1976-06-01
FR2270596B1 (it) 1981-03-06
DE2515297A1 (de) 1975-11-20
NL7505441A (nl) 1975-11-11
CA1039813A (en) 1978-10-03
JPS515935A (it) 1976-01-19
FR2270596A1 (it) 1975-12-05

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