IN2014CN04993A - - Google Patents

Info

Publication number
IN2014CN04993A
IN2014CN04993A IN4993CHN2014A IN2014CN04993A IN 2014CN04993 A IN2014CN04993 A IN 2014CN04993A IN 4993CHN2014 A IN4993CHN2014 A IN 4993CHN2014A IN 2014CN04993 A IN2014CN04993 A IN 2014CN04993A
Authority
IN
India
Prior art keywords
wwl
field effect
low
channel field
effect transistors
Prior art date
Application number
Other languages
English (en)
Inventor
Joshua L Puckett
Manish Garg
Harish Shankar
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN04993A publication Critical patent/IN2014CN04993A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
IN4993CHN2014 2012-01-23 2013-01-23 IN2014CN04993A (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261589570P 2012-01-23 2012-01-23
US13/746,528 US9093125B2 (en) 2012-01-23 2013-01-22 Low voltage write speed bitcell
PCT/US2013/022777 WO2013126172A1 (fr) 2012-01-23 2013-01-23 Cellule binaire à vitesse d'écriture à basse tension perfectionnée

Publications (1)

Publication Number Publication Date
IN2014CN04993A true IN2014CN04993A (fr) 2015-09-18

Family

ID=48797076

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4993CHN2014 IN2014CN04993A (fr) 2012-01-23 2013-01-23

Country Status (8)

Country Link
US (1) US9093125B2 (fr)
EP (1) EP2807649B1 (fr)
JP (1) JP6038956B2 (fr)
KR (1) KR101601827B1 (fr)
CN (1) CN104067345B (fr)
IN (1) IN2014CN04993A (fr)
TW (1) TWI537945B (fr)
WO (1) WO2013126172A1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9335775B2 (en) * 2014-06-23 2016-05-10 International Business Machines Corporation Integrated circuit having regulated voltage island power system
US9384825B2 (en) * 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
US9251875B1 (en) 2014-09-26 2016-02-02 Qualcomm Incorporated Register file circuit and method for improving the minimum operating supply voltage
US9583180B2 (en) * 2015-06-05 2017-02-28 Cisco Technology, Inc. Low-power row-oriented memory write assist circuit
US9646681B1 (en) 2016-04-25 2017-05-09 Qualcomm Incorporated Memory cell with improved write margin
US9940999B2 (en) 2016-06-22 2018-04-10 Darryl G. Walker Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
US10163524B2 (en) 2016-06-22 2018-12-25 Darryl G. Walker Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
US9786364B1 (en) * 2016-12-16 2017-10-10 Stmicroelectronics International N.V. Low voltage selftime tracking circuitry for write assist based memory operation
KR102021601B1 (ko) * 2017-09-22 2019-09-16 경북대학교 산학협력단 초저전압 메모리 장치 및 그 동작 방법
US10446223B1 (en) * 2018-08-29 2019-10-15 Bitfury Group Limited Data storage apparatus, and related systems and methods
US11074966B2 (en) 2018-10-31 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd Method and system to balance ground bounce
US11183234B2 (en) * 2019-11-25 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Bitcell supporting bit-write-mask function
CN111951849A (zh) * 2020-08-20 2020-11-17 海光信息技术有限公司 存储单元、随机静态存储器及寄存器堆
US11972793B2 (en) 2021-09-15 2024-04-30 Mavagail Technology, LLC Integrated circuit device including an SRAM portion having end power select circuits

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JPS58122693A (ja) * 1982-01-14 1983-07-21 Nippon Telegr & Teleph Corp <Ntt> メモリ回路
JPH02108297A (ja) * 1988-10-18 1990-04-20 Nippon Telegr & Teleph Corp <Ntt> メモリセル回路
JP4198201B2 (ja) 1995-06-02 2008-12-17 株式会社ルネサステクノロジ 半導体装置
FR2793064B1 (fr) * 1999-04-30 2004-01-02 St Microelectronics Sa Memoire a courant de fuite reduit
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same
US7218549B2 (en) * 2005-01-31 2007-05-15 Kabushiki Kaisha Toshiba Memory cell with stability switch for stable read operation and improved write operation
JP2007172715A (ja) * 2005-12-20 2007-07-05 Fujitsu Ltd 半導体記憶装置およびその制御方法
JP5076462B2 (ja) * 2005-12-28 2012-11-21 ソニー株式会社 半導体メモリデバイス
US7269055B2 (en) 2006-02-13 2007-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM device with reduced leakage current
US7324368B2 (en) 2006-03-30 2008-01-29 Arm Limited Integrated circuit memory with write assist
US20070268740A1 (en) * 2006-05-12 2007-11-22 Aly Rami E Ultra low power SRAM cell design
US7512030B2 (en) * 2006-08-29 2009-03-31 Texas Instruments Incorporated Memory with low power mode for WRITE
US7460400B1 (en) 2007-08-22 2008-12-02 Nscore Inc. Nonvolatile memory utilizing MIS memory transistors with bit mask function
US7630228B2 (en) 2007-08-30 2009-12-08 Intel Corporation Methods and apparatuses for operating memory
US20090086556A1 (en) 2007-09-27 2009-04-02 Sapumal Wijeratne Methods and apparatuses for operating memory
US7718482B2 (en) * 2007-10-10 2010-05-18 Texas Instruments Incorporated CD gate bias reduction and differential N+ poly doping for CMOS circuits
TWI346338B (en) * 2007-10-23 2011-08-01 Nat Univ Tsing Hua Access unit for a static random accesss memory
US7852661B2 (en) * 2008-10-22 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Write-assist SRAM cell
US7839173B1 (en) 2009-08-11 2010-11-23 Xilinx, Inc. High speed, low power signal level shifter
US8320203B2 (en) 2010-03-26 2012-11-27 Intel Corporation Method and system to lower the minimum operating voltage of register files
JP2011248932A (ja) * 2010-05-21 2011-12-08 Panasonic Corp 半導体記憶装置
US8462542B2 (en) * 2010-06-24 2013-06-11 Texas Instruments Incorporated Bit-by-bit write assist for solid-state memory
US8406077B2 (en) 2010-07-01 2013-03-26 Qualcomm Incorporated Multi-voltage level, multi-dynamic circuit structure device
US8451652B2 (en) * 2010-12-02 2013-05-28 Lsi Corporation Write assist static random access memory cell

Also Published As

Publication number Publication date
EP2807649A1 (fr) 2014-12-03
JP6038956B2 (ja) 2016-12-07
TWI537945B (zh) 2016-06-11
JP2015504228A (ja) 2015-02-05
US9093125B2 (en) 2015-07-28
CN104067345B (zh) 2017-05-03
EP2807649B1 (fr) 2020-02-19
CN104067345A (zh) 2014-09-24
US20130188434A1 (en) 2013-07-25
KR20140120919A (ko) 2014-10-14
KR101601827B1 (ko) 2016-03-09
TW201346907A (zh) 2013-11-16
WO2013126172A1 (fr) 2013-08-29

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