IL309011A - Method for producing a semiconductor structure comprising a useful layer made of silicon carbide, with improved electrical properties - Google Patents

Method for producing a semiconductor structure comprising a useful layer made of silicon carbide, with improved electrical properties

Info

Publication number
IL309011A
IL309011A IL309011A IL30901123A IL309011A IL 309011 A IL309011 A IL 309011A IL 309011 A IL309011 A IL 309011A IL 30901123 A IL30901123 A IL 30901123A IL 309011 A IL309011 A IL 309011A
Authority
IL
Israel
Prior art keywords
semiconductor structure
layer
donor substrate
fabrication process
process according
Prior art date
Application number
IL309011A
Other languages
English (en)
Hebrew (he)
Inventor
Drouin Alexis
Gaudin Gweltaz
Rouchier S?Verin
Schwarzenbach Walter
WIDIEZ Julie
Rolland Emmanuel
Original Assignee
Soitec Silicon On Insulator
Commissariat Energie Atomique
Drouin Alexis
Gaudin Gweltaz
Rouchier S?Verin
Schwarzenbach Walter
WIDIEZ Julie
Rolland Emmanuel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Commissariat Energie Atomique, Drouin Alexis, Gaudin Gweltaz, Rouchier S?Verin, Schwarzenbach Walter, WIDIEZ Julie, Rolland Emmanuel filed Critical Soitec Silicon On Insulator
Publication of IL309011A publication Critical patent/IL309011A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
IL309011A 2021-06-03 2022-05-25 Method for producing a semiconductor structure comprising a useful layer made of silicon carbide, with improved electrical properties IL309011A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2105848A FR3123759B1 (fr) 2021-06-03 2021-06-03 Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees
PCT/FR2022/051000 WO2022254131A1 (fr) 2021-06-03 2022-05-25 Procede de fabrication d'une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees

Publications (1)

Publication Number Publication Date
IL309011A true IL309011A (en) 2024-01-01

Family

ID=77519224

Family Applications (1)

Application Number Title Priority Date Filing Date
IL309011A IL309011A (en) 2021-06-03 2022-05-25 Method for producing a semiconductor structure comprising a useful layer made of silicon carbide, with improved electrical properties

Country Status (9)

Country Link
US (1) US20240312831A1 (enExample)
EP (1) EP4348701B1 (enExample)
JP (1) JP7880901B2 (enExample)
KR (1) KR20240067221A (enExample)
CN (1) CN118302839A (enExample)
FR (1) FR3123759B1 (enExample)
IL (1) IL309011A (enExample)
TW (1) TW202303968A (enExample)
WO (1) WO2022254131A1 (enExample)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3655547B2 (ja) * 2000-05-10 2005-06-02 株式会社イオン工学研究所 半導体薄膜の形成方法
FR2871172B1 (fr) 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication
JP6387375B2 (ja) * 2016-07-19 2018-09-05 株式会社サイコックス 半導体基板
KR102481927B1 (ko) * 2017-02-16 2022-12-28 신에쓰 가가꾸 고교 가부시끼가이샤 화합물 반도체 적층 기판, 그 제조 방법, 및 반도체 소자

Also Published As

Publication number Publication date
FR3123759B1 (fr) 2023-06-23
US20240312831A1 (en) 2024-09-19
TW202303968A (zh) 2023-01-16
JP2024521573A (ja) 2024-06-03
EP4348701A1 (fr) 2024-04-10
KR20240067221A (ko) 2024-05-16
FR3123759A1 (fr) 2022-12-09
EP4348701B1 (fr) 2025-06-25
JP7880901B2 (ja) 2026-06-26
EP4348701C0 (fr) 2025-06-25
WO2022254131A1 (fr) 2022-12-08
CN118302839A (zh) 2024-07-05

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