IL164726A0 - Destructive-read random access memory system buffered with destructiveread memory cache - Google Patents
Destructive-read random access memory system buffered with destructiveread memory cacheInfo
- Publication number
- IL164726A0 IL164726A0 IL16472604A IL16472604A IL164726A0 IL 164726 A0 IL164726 A0 IL 164726A0 IL 16472604 A IL16472604 A IL 16472604A IL 16472604 A IL16472604 A IL 16472604A IL 164726 A0 IL164726 A0 IL 164726A0
- Authority
- IL
- Israel
- Prior art keywords
- destructiveread
- destructive
- random access
- read random
- cache
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/30—Providing cache or TLB in specific location of a processing system
- G06F2212/304—In main memory subsystem
- G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2245—Memory devices with an internal cache buffer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/063,466 US6801980B2 (en) | 2002-04-25 | 2002-04-25 | Destructive-read random access memory system buffered with destructive-read memory cache |
PCT/US2003/010746 WO2003091883A1 (en) | 2002-04-25 | 2003-04-07 | Destructive-read random access memory system buffered with destructive-read memory cache |
Publications (1)
Publication Number | Publication Date |
---|---|
IL164726A0 true IL164726A0 (en) | 2005-12-18 |
Family
ID=29248086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL16472604A IL164726A0 (en) | 2002-04-25 | 2004-10-20 | Destructive-read random access memory system buffered with destructiveread memory cache |
Country Status (10)
Country | Link |
---|---|
US (3) | US6801980B2 (ja) |
EP (1) | EP1497733B1 (ja) |
JP (1) | JP4150718B2 (ja) |
KR (1) | KR100772998B1 (ja) |
CN (1) | CN1296832C (ja) |
AT (1) | ATE513264T1 (ja) |
AU (1) | AU2003234695A1 (ja) |
IL (1) | IL164726A0 (ja) |
TW (1) | TW594740B (ja) |
WO (1) | WO2003091883A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100541366B1 (ko) * | 2002-07-19 | 2006-01-16 | 주식회사 하이닉스반도체 | 고속 데이터 억세스를 위한 디램 |
DE10317162B4 (de) * | 2003-04-14 | 2010-02-11 | Qimonda Ag | Speichervorrichtung mit kurzer Wortleitungszykluszeit und Leseverfahren hierzu |
US20040221117A1 (en) * | 2003-05-02 | 2004-11-04 | Shelor Charles F. | Logic and method for reading data from cache |
US20050114588A1 (en) * | 2003-11-26 | 2005-05-26 | Lucker Jonathan C. | Method and apparatus to improve memory performance |
JP2006190402A (ja) * | 2005-01-07 | 2006-07-20 | Renesas Technology Corp | 半導体装置 |
KR100672029B1 (ko) * | 2005-05-27 | 2007-01-19 | 삼성전자주식회사 | Dram히든 리프레쉬 동작 시 발생되는 동작 시간 지연을감소시킬 수 있는 장치와 방법 |
KR100970946B1 (ko) | 2008-02-05 | 2010-07-20 | 부경대학교 산학협력단 | 플래시 메모리 기반 임베디드 데이터베이스 시스템의지연쓰기 방법 및 그를 위한 시스템 |
US8266408B2 (en) * | 2009-03-17 | 2012-09-11 | Memoir Systems, Inc. | System and method for storing data in a virtualized high speed memory system |
US9442846B2 (en) * | 2009-03-17 | 2016-09-13 | Cisco Technology, Inc. | High speed memory systems and methods for designing hierarchical memory systems |
US8433880B2 (en) * | 2009-03-17 | 2013-04-30 | Memoir Systems, Inc. | System and method for storing data in a virtualized high speed memory system |
WO2011075167A1 (en) * | 2009-12-15 | 2011-06-23 | Memoir Systems,Inc. | System and method for reduced latency caching |
EP2580703A4 (en) * | 2010-06-11 | 2013-11-27 | Freescale Semiconductor Inc | METHOD OF PROTECTING DATA STORED IN A MEMORY ELEMENT AND INTEGRATED CIRCUIT DEVICE THEREOF |
KR101953088B1 (ko) | 2011-01-31 | 2019-03-04 | 에버스핀 테크놀러지스, 인크. | 스핀 토크 자기 랜덤 액세스 메모리에 대한 기록 방법 |
US8675442B2 (en) | 2011-10-04 | 2014-03-18 | Qualcomm Incorporated | Energy efficient memory with reconfigurable decoding |
CN104484239B (zh) * | 2014-12-05 | 2019-02-26 | 深圳市华宝电子科技有限公司 | 一种车载视频文件修复方法及装置 |
US10866897B2 (en) * | 2016-09-26 | 2020-12-15 | Samsung Electronics Co., Ltd. | Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer |
US10650899B2 (en) * | 2017-04-27 | 2020-05-12 | Everspin Technologies, Inc. | Delayed write-back in memory with calibration support |
JP2019079377A (ja) | 2017-10-26 | 2019-05-23 | 東芝メモリ株式会社 | 半導体記憶装置 |
KR102683747B1 (ko) | 2019-01-22 | 2024-07-11 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US11899590B2 (en) * | 2021-06-18 | 2024-02-13 | Seagate Technology Llc | Intelligent cache with read destructive memory cells |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4725945A (en) | 1984-09-18 | 1988-02-16 | International Business Machines Corp. | Distributed cache in dynamic rams |
US5434530A (en) * | 1990-05-02 | 1995-07-18 | Microelectronics & Computer Technology Corporation | Superconducting semiconducting cross-bar circuit |
US5544306A (en) | 1994-05-03 | 1996-08-06 | Sun Microsystems, Inc. | Flexible dram access in a frame buffer memory and system |
US6161208A (en) | 1994-05-06 | 2000-12-12 | International Business Machines Corporation | Storage subsystem including an error correcting cache and means for performing memory to memory transfers |
JPH08278916A (ja) * | 1994-11-30 | 1996-10-22 | Hitachi Ltd | マルチチャネルメモリシステム、転送情報同期化方法及び信号転送回路 |
US5629889A (en) * | 1995-12-14 | 1997-05-13 | Nec Research Institute, Inc. | Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions |
US5838943A (en) * | 1996-03-26 | 1998-11-17 | Advanced Micro Devices, Inc. | Apparatus for speculatively storing and restoring data to a cache memory |
US5809528A (en) | 1996-12-24 | 1998-09-15 | International Business Machines Corporation | Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory |
JP3816110B2 (ja) * | 1997-02-17 | 2006-08-30 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US5801996A (en) * | 1997-02-26 | 1998-09-01 | Micron Technology, Inc. | Data path for high speed high bandwidth DRAM |
US6018763A (en) | 1997-05-28 | 2000-01-25 | 3Com Corporation | High performance shared memory for a bridge router supporting cache coherency |
US6081872A (en) | 1997-07-07 | 2000-06-27 | International Business Machines Corporation | Cache reloading performance improvement through the use of early select techniques with and without pipelining |
US6205076B1 (en) | 1998-03-27 | 2001-03-20 | Fujitsu Limited | Destructive read type memory circuit, restoring circuit for the same and sense amplifier |
US6378110B1 (en) * | 1998-03-31 | 2002-04-23 | Synopsys, Inc. | Layer-based rule checking for an integrated circuit layout |
JP3786521B2 (ja) * | 1998-07-01 | 2006-06-14 | 株式会社日立製作所 | 半導体集積回路及びデータ処理システム |
JP3374967B2 (ja) | 1998-10-26 | 2003-02-10 | 日本電気株式会社 | 半導体集積回路 |
US6178479B1 (en) | 1999-02-22 | 2001-01-23 | Nband Communications | Cycle-skipping DRAM for power saving |
KR100326939B1 (ko) | 1999-09-02 | 2002-03-13 | 윤덕용 | 고속 열 사이클이 가능한 메모리의 파이프라인 구조 |
JP3863330B2 (ja) | 1999-09-28 | 2006-12-27 | 株式会社東芝 | 不揮発性半導体メモリ |
JP4427847B2 (ja) * | 1999-11-04 | 2010-03-10 | エルピーダメモリ株式会社 | ダイナミック型ramと半導体装置 |
JP4535563B2 (ja) | 2000-04-28 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US6697909B1 (en) | 2000-09-12 | 2004-02-24 | International Business Machines Corporation | Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory |
DE60136574D1 (de) * | 2000-12-20 | 2008-12-24 | Fujitsu Ltd | Multiportspeicher auf Basis von DRAM |
US6829682B2 (en) * | 2001-04-26 | 2004-12-07 | International Business Machines Corporation | Destructive read architecture for dynamic random access memories |
US6587388B2 (en) * | 2001-04-27 | 2003-07-01 | International Business Machines Corporation | Method and apparatus for reducing write operation time in dynamic random access memories |
US6711078B2 (en) * | 2002-07-01 | 2004-03-23 | International Business Machines Corporation | Writeback and refresh circuitry for direct sensed DRAM macro |
-
2002
- 2002-04-25 US US10/063,466 patent/US6801980B2/en not_active Expired - Fee Related
-
2003
- 2003-04-02 TW TW092107498A patent/TW594740B/zh not_active IP Right Cessation
- 2003-04-07 CN CNB038092697A patent/CN1296832C/zh not_active Expired - Fee Related
- 2003-04-07 KR KR1020047015299A patent/KR100772998B1/ko not_active IP Right Cessation
- 2003-04-07 JP JP2004500188A patent/JP4150718B2/ja not_active Expired - Fee Related
- 2003-04-07 WO PCT/US2003/010746 patent/WO2003091883A1/en active Application Filing
- 2003-04-07 EP EP03728351A patent/EP1497733B1/en not_active Expired - Lifetime
- 2003-04-07 AU AU2003234695A patent/AU2003234695A1/en not_active Abandoned
- 2003-04-07 AT AT03728351T patent/ATE513264T1/de not_active IP Right Cessation
-
2004
- 2004-06-23 US US10/710,169 patent/US6948028B2/en not_active Expired - Fee Related
- 2004-10-20 IL IL16472604A patent/IL164726A0/xx unknown
-
2005
- 2005-06-14 US US11/160,220 patent/US7203794B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005524146A (ja) | 2005-08-11 |
US20030204667A1 (en) | 2003-10-30 |
WO2003091883A1 (en) | 2003-11-06 |
TW594740B (en) | 2004-06-21 |
AU2003234695A1 (en) | 2003-11-10 |
JP4150718B2 (ja) | 2008-09-17 |
KR20040105805A (ko) | 2004-12-16 |
US7203794B2 (en) | 2007-04-10 |
ATE513264T1 (de) | 2011-07-15 |
TW200305882A (en) | 2003-11-01 |
US20040221097A1 (en) | 2004-11-04 |
CN1296832C (zh) | 2007-01-24 |
EP1497733A4 (en) | 2008-04-30 |
CN1650270A (zh) | 2005-08-03 |
US20050226083A1 (en) | 2005-10-13 |
EP1497733A1 (en) | 2005-01-19 |
KR100772998B1 (ko) | 2007-11-05 |
US6801980B2 (en) | 2004-10-05 |
US6948028B2 (en) | 2005-09-20 |
EP1497733B1 (en) | 2011-06-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IL164726A0 (en) | Destructive-read random access memory system buffered with destructiveread memory cache | |
TW200632916A (en) | Scratch pad block | |
GB2445495A (en) | Limited use data storing device | |
HK1048903A1 (zh) | 介質數據的規劃提取、存儲與訪問 | |
HK1081284A1 (en) | Data source management system and method for wireless devices | |
GB2384338B (en) | Memory system for data storage and retrieval | |
GB2379538A (en) | Non-volatile cache | |
GB0324934D0 (en) | Method and apparatus for improving reliability of write back cache information | |
GB0227692D0 (en) | Information storage and retrieval | |
GB0216770D0 (en) | Portable data storage device with layered memory architecture | |
GB2388216B (en) | Multi-bank scheduling to improve performance on tree accesses in a dram based random access memory subsystem | |
GB2443998A (en) | Memory device activation and deactivation | |
TW200634823A (en) | System and method for use of on-chip non-volatile memory write cache | |
EP1667024A3 (en) | Memory based cross compare for cross checked systems | |
AU2003213910A1 (en) | Certificate information storage system and method | |
TW200615752A (en) | System, method and storage medium for memory management | |
GB0227683D0 (en) | Information storage and retrieval | |
TW200708950A (en) | Memory management method and system | |
AU2003273284A1 (en) | Static random access memory with symmetric leakage-compensated bit line | |
ATE229219T1 (de) | Speicheranordnung mit adressverwürfelung | |
DE60333677D1 (de) | Inen speicher | |
EP2287849A3 (en) | Semiconductor memory having dual port cell supporting hidden refresh | |
GB0229072D0 (en) | Information storage and retrieval | |
GB0327571D0 (en) | A memory dump of a computer system | |
GB2333621B (en) | Data cache with data storage and tag logic with different clocks |