IL159699A0 - Inter-chip communication system - Google Patents

Inter-chip communication system

Info

Publication number
IL159699A0
IL159699A0 IL15969901A IL15969901A IL159699A0 IL 159699 A0 IL159699 A0 IL 159699A0 IL 15969901 A IL15969901 A IL 15969901A IL 15969901 A IL15969901 A IL 15969901A IL 159699 A0 IL159699 A0 IL 159699A0
Authority
IL
Israel
Prior art keywords
inter
communication system
chip communication
chip
communication
Prior art date
Application number
IL15969901A
Other languages
English (en)
Original Assignee
Axis Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Axis Systems Inc filed Critical Axis Systems Inc
Publication of IL159699A0 publication Critical patent/IL159699A0/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3308Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
IL15969901A 2001-07-06 2001-08-23 Inter-chip communication system IL159699A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/900,124 US20020152060A1 (en) 1998-08-31 2001-07-06 Inter-chip communication system
PCT/US2001/026625 WO2003005212A1 (fr) 2001-07-06 2001-08-23 Systeme de communication inter-puces

Publications (1)

Publication Number Publication Date
IL159699A0 true IL159699A0 (en) 2004-06-20

Family

ID=25412009

Family Applications (1)

Application Number Title Priority Date Filing Date
IL15969901A IL159699A0 (en) 2001-07-06 2001-08-23 Inter-chip communication system

Country Status (5)

Country Link
US (2) US20020152060A1 (fr)
EP (1) EP1415230A4 (fr)
CA (1) CA2452879A1 (fr)
IL (1) IL159699A0 (fr)
WO (1) WO2003005212A1 (fr)

Families Citing this family (174)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8412853B2 (en) 2004-10-25 2013-04-02 Texas Instruments Incorporated Two pin serial bus communication interface
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
WO2000077652A2 (fr) 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Partionnement de sequences dans des structures cellulaires
US6625783B2 (en) * 2000-02-16 2003-09-23 Logic Research Co., Ltd. State machine, semiconductor device using state machine, and method of design thereof
US7266490B2 (en) 2000-12-28 2007-09-04 Robert Marc Zeidman Apparatus and method for connecting hardware to a circuit simulation
US8160863B2 (en) 2000-03-28 2012-04-17 Ionipas Transfer Company, Llc System and method for connecting a logic circuit simulation to a network
US6587995B1 (en) * 2000-04-19 2003-07-01 Koninklijke Philips Electronics N.V. Enhanced programmable core model with integrated graphical debugging functionality
EP2226732A3 (fr) 2000-06-13 2016-04-06 PACT XPP Technologies AG Hiérarchie d'antémémoires pour un processeur multi-coeur
US7725860B1 (en) * 2000-06-19 2010-05-25 Herman Kwong Contact mapping using channel routing
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US20070016396A9 (en) * 2000-12-28 2007-01-18 Zeidman Robert M Apparatus and method for connecting a hardware emulator to a computer peripheral
AU2002234212A1 (en) 2001-01-03 2002-08-19 University Of Southern California System level applications of adaptive computing (slaac) technology
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US6957403B2 (en) * 2001-03-30 2005-10-18 Syntest Technologies, Inc. Computer-aided design system to automate scan synthesis at register-transfer level
US7640582B2 (en) 2003-04-16 2009-12-29 Silicon Graphics International Clustered filesystem for mix of trusted and untrusted nodes
US7996827B2 (en) * 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7224689B2 (en) * 2001-08-17 2007-05-29 Sun Microsystems, Inc. Method and apparatus for routing of messages in a cycle-based system
US7043596B2 (en) * 2001-08-17 2006-05-09 Sun Microsystems, Inc. Method and apparatus for simulation processor
JP2003068864A (ja) * 2001-08-30 2003-03-07 Hitachi Ltd 半導体集積回路装置
US7020716B2 (en) * 2001-08-31 2006-03-28 Adaptec, Inc. Method and system for verifying the hardware implementation of TCP/IP
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
JP2003091424A (ja) * 2001-09-18 2003-03-28 Matsushita Electric Ind Co Ltd 分散処理システムおよびジョブ分散処理方法
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
JP3848157B2 (ja) * 2001-12-27 2006-11-22 株式会社東芝 Lsi設計検証装置、lsi設計検証方法、及びlsi設計検証プログラム
DE10392560D2 (de) 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
US20030154063A1 (en) * 2002-02-08 2003-08-14 Martin Lu Active path extraction for HDL code
DE10390689D2 (de) 2002-02-18 2005-02-10 Pact Xpp Technologies Ag Bussysteme und Rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6938236B1 (en) * 2002-03-29 2005-08-30 Altera Corporation Method of creating a mask-programmed logic device from a pre-existing circuit design
US7206732B2 (en) * 2002-04-04 2007-04-17 International Business Machines Corporation C-API instrumentation for HDL models
US7373290B2 (en) 2002-04-04 2008-05-13 International Business Machines Corporation Method and system for reducing storage requirements of simulation data via keyword restrictions
US7194400B2 (en) * 2002-04-04 2007-03-20 International Business Machines Corporation Method and system for reducing storage and transmission requirements for simulation results
US7203633B2 (en) * 2002-04-04 2007-04-10 International Business Machines Corporation Method and system for selectively storing and retrieving simulation data utilizing keywords
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2005010632A2 (fr) * 2003-06-17 2005-02-03 Pact Xpp Technologies Ag Dispositif et procede de traitement de donnees
WO2004021176A2 (fr) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Procede et dispositif de traitement de donnees
US7212961B2 (en) 2002-08-30 2007-05-01 Lsi Logic Corporation Interface for rapid prototyping system
US7299427B2 (en) * 2002-08-30 2007-11-20 Lsi Corporation Radio prototyping system
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US20040059973A1 (en) * 2002-09-24 2004-03-25 Sherman Brent M. Apparatus for testing a device under test using a high speed bus and method therefor
DE10255768B3 (de) * 2002-11-28 2004-06-24 Infineon Technologies Ag Anordnung von konfigurierbaren Logik Blöcken
US7007254B1 (en) * 2003-01-17 2006-02-28 Synplicity, Inc. Method and apparatus for the design and analysis of digital circuits with time division multiplexing
US7237214B1 (en) * 2003-03-04 2007-06-26 Synplicity, Inc. Method and apparatus for circuit partitioning and trace assignment in circuit design
US8639487B1 (en) * 2003-03-25 2014-01-28 Cadence Design Systems, Inc. Method for multiple processor system-on-a-chip hardware and software cogeneration
FR2854703B1 (fr) * 2003-05-07 2005-06-24 Arteris Dispositif d'emulation d'une ou plusieurs puces de circuits integres
CA2523548C (fr) * 2003-05-23 2014-02-04 Washington University Systeme de stockage et de traitement de donnees intelligent utilisant des dispositifs fpga
TW200506733A (en) * 2003-08-15 2005-02-16 Via Tech Inc Apparatus and method for the co-simulation of CPU and DUT modules
EP1676208A2 (fr) 2003-08-28 2006-07-05 PACT XPP Technologies AG Dispositif et procede de traitement de donnees
JP2005084956A (ja) * 2003-09-09 2005-03-31 Nec Corp 論理回路の検証方法および検証システム
US7191111B2 (en) * 2003-09-11 2007-03-13 International Business Machines Corporation Method, apparatus, and computer program product for implementing dynamic cosimulation
US7236918B2 (en) 2003-12-31 2007-06-26 International Business Machines Corporation Method and system for selective compilation of instrumentation entities into a simulation model of a digital design
US7536288B2 (en) 2003-12-31 2009-05-19 International Business Machines Corporation Method, system and program product supporting user tracing in a simulator
US7093218B2 (en) * 2004-02-19 2006-08-15 International Business Machines Corporation Incremental, assertion-based design verification
US7617012B2 (en) * 2004-03-04 2009-11-10 Yamaha Corporation Audio signal processing system
US7937557B2 (en) * 2004-03-16 2011-05-03 Vns Portfolio Llc System and method for intercommunication between computers in an array
US7409670B1 (en) * 2004-04-01 2008-08-05 Altera Corporation Scheduling logic on a programmable device implemented using a high-level language
US7370311B1 (en) * 2004-04-01 2008-05-06 Altera Corporation Generating components on a programmable device using a high-level language
US7860703B2 (en) * 2004-04-19 2010-12-28 Iadea Corporation Timing control method of hardware-simulating program and application of the same
US7721036B2 (en) * 2004-06-01 2010-05-18 Quickturn Design Systems Inc. System and method for providing flexible signal routing and timing
US20060089826A1 (en) * 2004-10-21 2006-04-27 International Business Machines Corporation Method, system and program product for defining and recording minimum and maximum count events of a simulation
US7392169B2 (en) * 2004-10-21 2008-06-24 International Business Machines Corporation Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language
US7454325B2 (en) * 2004-12-07 2008-11-18 International Business Machines Corporation Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases
WO2006110952A1 (fr) * 2005-04-19 2006-10-26 Fairlight.Au Pty Ltd Systeme et procede de traitement de media
US7904695B2 (en) * 2006-02-16 2011-03-08 Vns Portfolio Llc Asynchronous power saving computer
US7552043B2 (en) * 2005-09-15 2009-06-23 International Business Machines Corporation Method, system and program product for selectively removing instrumentation logic from a simulation model
US7346863B1 (en) 2005-09-28 2008-03-18 Altera Corporation Hardware acceleration of high-level language code sequences on programmable devices
US7571086B2 (en) * 2005-11-04 2009-08-04 Springsoft Usa, Inc. Incremental circuit re-simulation system
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US7904615B2 (en) * 2006-02-16 2011-03-08 Vns Portfolio Llc Asynchronous computer communication
US7966481B2 (en) 2006-02-16 2011-06-21 Vns Portfolio Llc Computer system and method for executing port communications without interrupting the receiving computer
WO2007093218A1 (fr) * 2006-02-17 2007-08-23 Mentor Graphics Corp. Bus annulaire dans un environnement d'émulation
US7711537B2 (en) * 2006-05-03 2010-05-04 International Business Machines Corporation Signals for simulation result viewing
US7493248B2 (en) * 2006-05-08 2009-02-17 International Business Machines Corporation Method, system and program product supporting phase events in a simulation model of a digital system
US8619554B2 (en) * 2006-08-04 2013-12-31 Arm Limited Interconnecting initiator devices and recipient devices
US7761828B2 (en) * 2006-08-18 2010-07-20 Partition Design, Inc. Partitioning electronic circuit designs into simulation-ready blocks
US7448008B2 (en) * 2006-08-29 2008-11-04 International Business Machines Corporation Method, system, and program product for automated verification of gating logic using formal verification
US8229727B2 (en) * 2007-01-09 2012-07-24 International Business Machines Corporation System and method for incorporating design behavior and external stimulus in microprocessor emulation model feedback using a shared memory
US7912694B2 (en) * 2007-01-30 2011-03-22 International Business Machines Corporation Print events in the simulation of a digital system
US7966039B2 (en) * 2007-02-02 2011-06-21 Microsoft Corporation Bidirectional dynamic offloading of tasks between a host and a mobile device
US8199695B2 (en) 2007-04-10 2012-06-12 International Business Machines Corporation Clock signal synchronization among computers in a network
JP2008282314A (ja) * 2007-05-14 2008-11-20 Toshiba Corp シミュレータ、シミュレーション方法
US7809544B1 (en) * 2007-06-13 2010-10-05 Xilinx, Inc. Methods of detecting unwanted logic in designs for programmable logic devices
US8050902B2 (en) 2007-10-31 2011-11-01 International Business Machines Corporation Reporting temporal information regarding count events of a simulation
US8352235B1 (en) 2007-10-31 2013-01-08 Cadence Design Systems, Inc. Emulation of power shutoff behavior for integrated circuits
US7925489B2 (en) * 2007-10-31 2011-04-12 International Business Machines Corporation Defining and recording threshold-qualified count events of a simulation by testcases
US20100281235A1 (en) * 2007-11-17 2010-11-04 Martin Vorbach Reconfigurable floating-point and bit-level data processing unit
JP4901702B2 (ja) * 2007-11-27 2012-03-21 株式会社東芝 回路設計方法
EP2217999A2 (fr) * 2007-11-28 2010-08-18 Krass, Maren Traitement de l'information
JP5206063B2 (ja) * 2008-03-25 2013-06-12 日本電気株式会社 記述処理装置、記述処理方法およびプログラム
US8141084B2 (en) * 2008-04-07 2012-03-20 International Business Machines Corporation Managing preemption in a parallel computing system
US7912693B1 (en) * 2008-05-01 2011-03-22 Xilinx, Inc. Verifying configuration memory of a programmable logic device
KR101624868B1 (ko) * 2008-08-06 2016-06-07 삼성전자주식회사 가상화 장치의 제어방법 및 가상화 장치
US8868395B2 (en) * 2008-10-27 2014-10-21 Synopsys, Inc. Fast simulation method for integrated circuits with power management circuitry
US8503482B2 (en) * 2008-11-19 2013-08-06 Lsi Corporation Interconnects using self-timed time-division multiplexed bus
US9262303B2 (en) * 2008-12-05 2016-02-16 Altera Corporation Automated semiconductor design flaw detection system
US8160857B2 (en) 2008-12-16 2012-04-17 International Business Machines Corporation Selective compilation of a simulation model in view of unavailable higher level signals
US8453080B2 (en) * 2008-12-16 2013-05-28 International Business Machines Corporation Model build in the presence of a non-binding reference
US8191028B1 (en) * 2009-04-07 2012-05-29 Altera Corporation Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
US9477802B1 (en) 2009-06-09 2016-10-25 Cadence Design Systems, Inc. Isolating differences between revisions of a circuit design
US8532975B2 (en) * 2009-06-12 2013-09-10 Cadence Design Systems, Inc. System and method implementing a simulation acceleration capture buffer
US8473661B2 (en) * 2009-08-14 2013-06-25 Cadence Design Systems, Inc. System and method for providing multi-process protection using direct memory mapped control registers
US8327039B2 (en) 2009-08-14 2012-12-04 Cadence Design Systems, Inc. Integrated DMA processor and PCI express switch for a hardware-based functional verification system
US8302038B2 (en) * 2009-12-15 2012-10-30 Apple Inc. Engineering change order language for modifying integrated circuit design files for programmable logic device implementation
US8166437B2 (en) 2009-12-15 2012-04-24 Apple Inc. Automated pad ring generation for programmable logic device implementation of integrated circuit design
US8332795B2 (en) * 2009-12-15 2012-12-11 Apple Inc. Automated pin multiplexing for programmable logic device implementation of integrated circuit design
US8479135B2 (en) * 2009-12-15 2013-07-02 Apple Inc. Automated framework for programmable logic device implementation of integrated circuit design
US8680886B1 (en) 2010-05-13 2014-03-25 Altera Corporation Apparatus for configurable electronic circuitry and associated methods
US9780789B2 (en) 2010-05-13 2017-10-03 Altera Corporation Apparatus for automatically configured interface and associated methods
US8467218B1 (en) * 2010-12-13 2013-06-18 Altera Corporation System and apparatus with IC resource interconnect
US8812287B2 (en) * 2011-02-08 2014-08-19 International Business Machines Corporation Autonomous, scalable, digital system for emulation of wired-or hardware connection
US8843662B2 (en) * 2011-05-09 2014-09-23 Bae Systems Information And Electronic Systems Integration Inc. Peek/poke interface on radio system core engine modem to allow debug during system integration
US8793644B2 (en) 2011-06-02 2014-07-29 Qualcomm Technologies, Inc. Display and automatic improvement of timing and area in a network-on-chip
US20150073768A1 (en) * 2011-11-04 2015-03-12 Witricity Corporation Wireless energy transfer modeling tool
WO2013076173A1 (fr) * 2011-11-22 2013-05-30 Hms Industrial Networks Ab Système de sécurité
WO2013136248A1 (fr) * 2012-03-11 2013-09-19 Cigol Digital Systems Ltd. Compression de signal de circuit vlsi
US8739092B1 (en) 2012-04-25 2014-05-27 Jasper Design Automation, Inc. Functional property ranking
US9104478B2 (en) * 2012-06-15 2015-08-11 Freescale Semiconductor, Inc. System and method for improved job processing of a number of jobs belonging to communication streams within a data processor
US9286118B2 (en) 2012-06-15 2016-03-15 Freescale Semiconductor, Inc. System and method for improved job processing to reduce contention for shared resources
US9448967B2 (en) * 2012-10-31 2016-09-20 Mstar Semiconductor, Inc. Stream data processor
US9632977B2 (en) 2013-03-13 2017-04-25 Nxp Usa, Inc. System and method for ordering packet transfers in a data processor
US9438638B2 (en) * 2013-03-15 2016-09-06 Silicon Graphics International Corp. Method for transparently connecting augmented network socket operations
US9208008B2 (en) 2013-07-24 2015-12-08 Qualcomm Incorporated Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience
US10205666B2 (en) * 2013-07-29 2019-02-12 Ampere Computing Llc End-to-end flow control in system on chip interconnects
EP2858323A1 (fr) * 2013-10-01 2015-04-08 Enyx SA Procédé et dispositif permettant de décoder des flux de données dans des plates-formes reconfigurables
US9081927B2 (en) 2013-10-04 2015-07-14 Jasper Design Automation, Inc. Manipulation of traces for debugging a circuit design
US10503856B2 (en) 2013-12-05 2019-12-10 International Business Machines Corporation Phase algebra for specifying clocks and modes in hierarchical designs
US9916407B2 (en) 2013-12-05 2018-03-13 International Business Machines Corporation Phase algebra for analysis of hierarchical designs
US10318695B2 (en) 2013-12-05 2019-06-11 International Business Machines Corporation Phase algebra for virtual clock and mode extraction in hierarchical designs
US9268889B2 (en) 2013-12-05 2016-02-23 International Business Machines Corporation Verification of asynchronous clock domain crossings
US9935637B2 (en) * 2014-02-11 2018-04-03 National Instruments Corporation Systems and methods for FPGA development and operation
US9904749B2 (en) * 2014-02-13 2018-02-27 Synopsys, Inc. Configurable FPGA sockets
US9026966B1 (en) 2014-03-13 2015-05-05 Cadence Design Systems, Inc. Co-simulation methodology to address performance and runtime challenges of gate level simulations with, SDF timing using emulators
US9514093B2 (en) * 2014-09-26 2016-12-06 Intel Corporation Method and apparatus for stacking core and uncore dies having landing slots
US9171111B1 (en) * 2014-09-29 2015-10-27 Cadence Design Systems, Inc. Hardware emulation method and system using a port time shift register
US9760663B2 (en) * 2014-10-30 2017-09-12 Synopsys, Inc. Automatic generation of properties to assist hardware emulation
CN104378571B (zh) * 2014-11-27 2018-01-30 江西洪都航空工业集团有限责任公司 一种绝对时间的实时提取与叠加方法
US10140413B2 (en) * 2015-04-21 2018-11-27 Synopsys, Inc. Efficient resolution of latch race conditions in emulation
US10430215B1 (en) * 2015-06-25 2019-10-01 Cadence Design Systems, Inc. Method and system to transfer data between hardware emulator and host workstation
US10476545B2 (en) * 2015-09-25 2019-11-12 Intel Corporation Communication between integrated circuit packages using a millimeter-wave wireless radio fabric
US10310580B2 (en) * 2015-10-09 2019-06-04 Sandisk Technologies Llc Voltage level detection and analog circuit arrangements for memory systems
GB2544996B (en) 2015-12-02 2017-12-06 Advanced Risc Mach Ltd An apparatus and method for managing bounded pointers
US10060978B2 (en) * 2016-06-21 2018-08-28 International Business Machines Corporation Implementing prioritized compressed failure defects for efficient scan diagnostics
US10334334B2 (en) * 2016-07-22 2019-06-25 Intel Corporation Storage sled and techniques for a data center
US10229470B2 (en) * 2016-08-05 2019-03-12 Intel IP Corporation Mechanism to accelerate graphics workloads in a multi-core computing architecture
US10437946B1 (en) * 2016-09-01 2019-10-08 Xilinx, Inc. Using implemented core sources for simulation
US10169518B1 (en) * 2016-11-03 2019-01-01 Intel Corporation Methods for delaying register reset for retimed circuits
US10354038B1 (en) 2016-11-15 2019-07-16 Intel Corporation Methods for bounding the number of delayed reset clock cycles for retimed circuits
US10635766B2 (en) 2016-12-12 2020-04-28 International Business Machines Corporation Simulation employing level-dependent multitype events
EP3399425B1 (fr) 2017-05-05 2020-07-29 dSPACE digital signal processing and control engineering GmbH Procédé destiné à la détection d'une topologie de câblage
TWI627521B (zh) * 2017-06-07 2018-06-21 財團法人工業技術研究院 時序估算方法與模擬裝置
US20190146847A1 (en) * 2017-11-10 2019-05-16 Mentor Graphics Corporation Dynamic distributed resource management
US10528697B1 (en) * 2017-11-20 2020-01-07 Xilinx, Inc. Timing-closure methodology involving clock network in hardware designs
US11194943B2 (en) * 2017-12-12 2021-12-07 Synopsys, Inc. FPGA-based hardware emulator system with an inter-FPGA connection switch
GB201801572D0 (en) * 2018-01-31 2018-03-14 Nordic Semiconductor Asa Inter-processor communication
TWI681311B (zh) * 2018-04-27 2020-01-01 瑞昱半導體股份有限公司 電路設計系統與檢查方法
US10771982B2 (en) 2018-10-24 2020-09-08 Mentor Graphics Corporation Resource utilization of heterogeneous compute units in electronic design automation
US11231873B2 (en) * 2018-12-07 2022-01-25 Intel Corporation Apparatus and method for assigning velocities to write data
US10747928B2 (en) * 2018-12-29 2020-08-18 Intel IP Corporation Diagnostic testing of FPGAs for safety critical systems
CN112131174A (zh) 2019-06-25 2020-12-25 北京百度网讯科技有限公司 支持在多个芯片之间通信的方法、装置、电子设备和计算机存储介质
US10970442B1 (en) * 2019-10-24 2021-04-06 SK Hynix Inc. Method of debugging hardware and firmware of data storage
CN111125975B (zh) * 2019-12-09 2024-06-14 上海思尔芯技术股份有限公司 一种fpga时分复用多路数据传输的方法、存储介质及终端
US11461523B1 (en) * 2020-02-07 2022-10-04 Synopsys, Inc. Glitch analysis and glitch power estimation system
US11092646B1 (en) * 2020-02-18 2021-08-17 Qualcomm Incorporated Determining a voltage and/or frequency for a performance mode
US11693795B2 (en) * 2020-04-17 2023-07-04 Texas Instruments Incorporated Methods and apparatus to extend local buffer of a hardware accelerator
WO2022055490A1 (fr) * 2020-09-11 2022-03-17 Google Llc Dispositif de commande de sauvegarde et de restauration en fonction d'un matériel
CN112286863B (zh) 2020-11-18 2023-08-18 合肥沛睿微电子股份有限公司 处理暨存储电路
TWI786476B (zh) * 2020-11-25 2022-12-11 大陸商合肥沛睿微電子股份有限公司 處理暨儲存電路

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856553A (ja) * 1981-09-30 1983-04-04 Fujitsu Ltd 状態変化検出回路
DE3329228A1 (de) * 1983-08-12 1985-02-21 Siemens AG, 1000 Berlin und 8000 München Datenuebertragungsverfahren in einem digitalen uebertragungsnetzwerk und vorrichtung zur durchfuehrung des verfahrens
US5031095A (en) * 1987-02-20 1991-07-09 Matsushita Electric Industrial Co., Ltd. Data transmission apparatus
JPH0514365A (ja) 1991-06-28 1993-01-22 Nippon Steel Corp スキヤン伝送方式
US5423010A (en) * 1992-01-24 1995-06-06 C-Cube Microsystems Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words
US5948073A (en) * 1993-07-07 1999-09-07 Xerox Corporation Multiplexing bus controller with input conditioning
WO1995004402A1 (fr) * 1993-08-03 1995-02-09 Xilinx, Inc. Circuit fpga a microprocesseur
US5748917A (en) * 1994-03-18 1998-05-05 Apple Computer, Inc. Line data architecture and bus interface circuits and methods for dual-edge clocking of data to bus-linked limited capacity devices
JPH09200237A (ja) * 1996-01-23 1997-07-31 Furukawa Electric Co Ltd:The 多重伝送方法
US5748911A (en) * 1996-07-19 1998-05-05 Compaq Computer Corporation Serial bus system for shadowing registers
US5924121A (en) * 1996-12-23 1999-07-13 International Business Machines Corporation Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles
US6058443A (en) * 1997-02-18 2000-05-02 Advanced Micro Devices, Inc. System for partitioning PC chipset functions into logic and port integrated circuits
US6014720A (en) * 1997-05-05 2000-01-11 Intel Corporation Dynamically sizing a bus transaction for dual bus size interoperability based on bus transaction signals

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WO2003005212A1 (fr) 2003-01-16
US20020152060A1 (en) 2002-10-17
US20050102125A1 (en) 2005-05-12
US7512728B2 (en) 2009-03-31
EP1415230A4 (fr) 2006-05-17
CA2452879A1 (fr) 2003-01-16

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