IL144680A - Method for initiating a retrieval procedure in virtual ground arrays - Google Patents

Method for initiating a retrieval procedure in virtual ground arrays

Info

Publication number
IL144680A
IL144680A IL14468000A IL14468000A IL144680A IL 144680 A IL144680 A IL 144680A IL 14468000 A IL14468000 A IL 14468000A IL 14468000 A IL14468000 A IL 14468000A IL 144680 A IL144680 A IL 144680A
Authority
IL
Israel
Prior art keywords
initiating
virtual ground
retrieval procedure
ground arrays
arrays
Prior art date
Application number
IL14468000A
Other languages
English (en)
Other versions
IL144680A0 (en
Original Assignee
Saifun Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Saifun Semiconductors Ltd filed Critical Saifun Semiconductors Ltd
Publication of IL144680A0 publication Critical patent/IL144680A0/xx
Publication of IL144680A publication Critical patent/IL144680A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
IL14468000A 1999-02-04 2000-02-03 Method for initiating a retrieval procedure in virtual ground arrays IL144680A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/246,776 US6134156A (en) 1999-02-04 1999-02-04 Method for initiating a retrieval procedure in virtual ground arrays
PCT/IL2000/000076 WO2000046808A1 (en) 1999-02-04 2000-02-03 Method for initiating a retrieval procedure in virtual ground arrays

Publications (2)

Publication Number Publication Date
IL144680A0 IL144680A0 (en) 2002-06-30
IL144680A true IL144680A (en) 2005-07-25

Family

ID=22932153

Family Applications (1)

Application Number Title Priority Date Filing Date
IL14468000A IL144680A (en) 1999-02-04 2000-02-03 Method for initiating a retrieval procedure in virtual ground arrays

Country Status (6)

Country Link
US (1) US6134156A (xx)
EP (1) EP1141964A4 (xx)
JP (1) JP2002536776A (xx)
AU (1) AU2318200A (xx)
IL (1) IL144680A (xx)
WO (1) WO2000046808A1 (xx)

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US6633499B1 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Method for reducing voltage drops in symmetric array architectures
US6633496B2 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Symmetric architecture for memory cells having widely spread metal bit lines
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
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US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
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US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
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EP1274095A3 (en) 2001-07-06 2005-05-25 Halo Lsi Design and Device Technology Inc. Twin MONOS cell array metal bitline organization and single cell operation
JP4859294B2 (ja) * 2001-07-10 2012-01-25 富士通セミコンダクター株式会社 不揮発性半導体記憶装置
US6525969B1 (en) * 2001-08-10 2003-02-25 Advanced Micro Devices, Inc. Decoder apparatus and methods for pre-charging bit lines
US6510082B1 (en) * 2001-10-23 2003-01-21 Advanced Micro Devices, Inc. Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
US6529412B1 (en) * 2002-01-16 2003-03-04 Advanced Micro Devices, Inc. Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
JP4156248B2 (ja) * 2002-02-18 2008-09-24 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US6747896B2 (en) 2002-05-06 2004-06-08 Multi Level Memory Technology Bi-directional floating gate nonvolatile memory
US7221591B1 (en) * 2002-05-06 2007-05-22 Samsung Electronics Co., Ltd. Fabricating bi-directional nonvolatile memory cells
US6914820B1 (en) 2002-05-06 2005-07-05 Multi Level Memory Technology Erasing storage nodes in a bi-directional nonvolatile memory cell
US6853587B2 (en) * 2002-06-21 2005-02-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per 1F2
JP4678760B2 (ja) * 2002-06-21 2011-04-27 マイクロン テクノロジー， インク． メモリセルのアレイ、メモリアレイ、メモリデバイス及び多重状態セルを有するメモリアレイを形成する方法
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6826107B2 (en) 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US6963505B2 (en) 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US6967896B2 (en) 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
KR100535651B1 (ko) * 2003-06-30 2005-12-08 주식회사 하이닉스반도체 플래시 메모리 셀과, 낸드 및 노아 타입의 플래시 메모리장치의 독출방법
US6979857B2 (en) 2003-07-01 2005-12-27 Micron Technology, Inc. Apparatus and method for split gate NROM memory
US7095075B2 (en) 2003-07-01 2006-08-22 Micron Technology, Inc. Apparatus and method for split transistor memory having improved endurance
US7085170B2 (en) * 2003-08-07 2006-08-01 Micron Technology, Ind. Method for erasing an NROM cell
US6873550B2 (en) * 2003-08-07 2005-03-29 Micron Technology, Inc. Method for programming and erasing an NROM cell
US6977412B2 (en) * 2003-09-05 2005-12-20 Micron Technology, Inc. Trench corner effect bidirectional flash memory cell
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US6954393B2 (en) * 2003-09-16 2005-10-11 Saifun Semiconductors Ltd. Reading array cell with matched reference cell
US6830963B1 (en) 2003-10-09 2004-12-14 Micron Technology, Inc. Fully depleted silicon-on-insulator CMOS logic
US7184315B2 (en) * 2003-11-04 2007-02-27 Micron Technology, Inc. NROM flash memory with self-aligned structural charge separation
US7202523B2 (en) * 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7050330B2 (en) * 2003-12-16 2006-05-23 Micron Technology, Inc. Multi-state NROM device
US7269072B2 (en) * 2003-12-16 2007-09-11 Micron Technology, Inc. NROM memory cell, memory array, related devices and methods
US7241654B2 (en) 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array
US7157769B2 (en) * 2003-12-18 2007-01-02 Micron Technology, Inc. Flash memory having a high-permittivity tunnel dielectric
US6878991B1 (en) 2004-01-30 2005-04-12 Micron Technology, Inc. Vertical device 4F2 EEPROM memory
US7221018B2 (en) * 2004-02-10 2007-05-22 Micron Technology, Inc. NROM flash memory with a high-permittivity gate dielectric
US6952366B2 (en) * 2004-02-10 2005-10-04 Micron Technology, Inc. NROM flash memory cell with integrated DRAM
US7075146B2 (en) 2004-02-24 2006-07-11 Micron Technology, Inc. 4F2 EEPROM NROM memory arrays with vertical devices
US7072217B2 (en) * 2004-02-24 2006-07-04 Micron Technology, Inc. Multi-state memory cell with asymmetric charge trapping
US7102191B2 (en) 2004-03-24 2006-09-05 Micron Technologies, Inc. Memory device with high dielectric constant gate dielectrics and metal floating gates
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7313649B2 (en) 2004-04-28 2007-12-25 Matsushita Electric Industrial Co., Ltd. Flash memory and program verify method for flash memory
US7274068B2 (en) 2004-05-06 2007-09-25 Micron Technology, Inc. Ballistic direct injection NROM cell on strained silicon structures
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
JP2007027760A (ja) 2005-07-18 2007-02-01 Saifun Semiconductors Ltd 高密度不揮発性メモリアレイ及び製造方法
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
JP2007133987A (ja) * 2005-11-11 2007-05-31 Toshiba Corp 半導体記憶装置および半導体記憶装置の駆動方法
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7782674B2 (en) * 2007-10-18 2010-08-24 Micron Technology, Inc. Sensing of memory cells in NAND flash
JP2009123294A (ja) * 2007-11-15 2009-06-04 Panasonic Corp 半導体不揮発性メモリ

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US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
US5477499A (en) * 1993-10-13 1995-12-19 Advanced Micro Devices, Inc. Memory architecture for a three volt flash EEPROM
JP3076185B2 (ja) * 1993-12-07 2000-08-14 日本電気株式会社 半導体メモリ装置及びその検査方法
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping

Also Published As

Publication number Publication date
EP1141964A4 (en) 2004-05-19
US6134156A (en) 2000-10-17
WO2000046808A1 (en) 2000-08-10
JP2002536776A (ja) 2002-10-29
AU2318200A (en) 2000-08-25
IL144680A0 (en) 2002-06-30
EP1141964A1 (en) 2001-10-10

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