IL124905A - Processor that supports code size reduction - Google Patents

Processor that supports code size reduction

Info

Publication number
IL124905A
IL124905A IL12490598A IL12490598A IL124905A IL 124905 A IL124905 A IL 124905A IL 12490598 A IL12490598 A IL 12490598A IL 12490598 A IL12490598 A IL 12490598A IL 124905 A IL124905 A IL 124905A
Authority
IL
Israel
Prior art keywords
constant
instruction
register
value
stored
Prior art date
Application number
IL12490598A
Other languages
English (en)
Hebrew (he)
Other versions
IL124905A0 (en
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP15904997A external-priority patent/JP3670801B2/ja
Priority claimed from JP23435697A external-priority patent/JPH1173331A/ja
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of IL124905A0 publication Critical patent/IL124905A0/xx
Publication of IL124905A publication Critical patent/IL124905A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
IL12490598A 1997-06-16 1998-06-15 Processor that supports code size reduction IL124905A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP15904997A JP3670801B2 (ja) 1997-06-16 1997-06-16 プロセッサ
JP23435697A JPH1173331A (ja) 1997-08-29 1997-08-29 プロセッサおよびコンテキストの退避または復帰の方法

Publications (2)

Publication Number Publication Date
IL124905A0 IL124905A0 (en) 1999-01-26
IL124905A true IL124905A (en) 2001-09-13

Family

ID=26485967

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12490598A IL124905A (en) 1997-06-16 1998-06-15 Processor that supports code size reduction

Country Status (8)

Country Link
US (1) US6219779B1 (ko)
EP (1) EP0897147A3 (ko)
KR (1) KR100618247B1 (ko)
CN (1) CN1269052C (ko)
IL (1) IL124905A (ko)
MY (1) MY126508A (ko)
SG (1) SG66480A1 (ko)
TW (1) TW393623B (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3790607B2 (ja) * 1997-06-16 2006-06-28 松下電器産業株式会社 Ｖｌｉｗプロセッサ
JP3327818B2 (ja) * 1997-08-29 2002-09-24 松下電器産業株式会社 プログラム変換装置及び記録媒体
US6412063B1 (en) * 1999-04-02 2002-06-25 Via-Cyrix, Inc. Multiple-operand instruction in a two operand pipeline and processor employing the same
JP2001142695A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd 記憶場所への定数のロード方法、宛先記憶場所への定数のロード方法、レジスタへの定数のロード方法、符号ビット数の決定方法、２進数の正規化方法、及びコンピュータシステム内の命令
US6950669B2 (en) 2000-07-05 2005-09-27 Telefonaktiebolaget Lm Ericsson (Publ) Power control algorithm for packet data based on queue/channel utilization
US7941651B1 (en) * 2002-06-27 2011-05-10 Intel Corporation Method and apparatus for combining micro-operations to process immediate data
EP1378824A1 (en) * 2002-07-02 2004-01-07 STMicroelectronics S.r.l. A method for executing programs on multiple processors and corresponding processor system
US8006071B2 (en) 2004-03-31 2011-08-23 Altera Corporation Processors operable to allow flexible instruction alignment
EP2041645B1 (en) * 2006-07-11 2016-12-07 Freescale Semiconductor, Inc. Microprocessor and method for register addressing therein
KR20090027358A (ko) * 2007-09-12 2009-03-17 엘지이노텍 주식회사 디지털 지상파 및 케이블 복합튜너
GB2486905A (en) * 2010-12-30 2012-07-04 Cambridge Silicon Radio Ltd Amalgamating instructions by replacing unencoded space
JP6214142B2 (ja) * 2012-10-09 2017-10-18 キヤノン株式会社 情報処理装置、情報処理方法およびプログラム
US10540148B2 (en) * 2014-06-12 2020-01-21 Oracle International Corporation Complex constants
JP6372250B2 (ja) * 2014-08-25 2018-08-15 サンケン電気株式会社 演算処理装置
US10297003B2 (en) 2015-09-21 2019-05-21 Qualcomm Incorporated Efficient saving and restoring of context information for context switches
TWI707272B (zh) * 2019-04-10 2020-10-11 瑞昱半導體股份有限公司 可執行指令的電子裝置以及指令執行方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979725A (en) * 1973-08-06 1976-09-07 Xerox Corporation Multi-way program branching circuits
US4107781A (en) * 1976-10-27 1978-08-15 Texas Instruments Incorporated Electronic calculator or microprocessor with indirect addressing
US4740893A (en) * 1985-08-07 1988-04-26 International Business Machines Corp. Method for reducing the time for switching between programs
US5001662A (en) * 1989-04-28 1991-03-19 Apple Computer, Inc. Method and apparatus for multi-gauge computation
JPH0353328A (ja) * 1989-07-20 1991-03-07 Hitachi Ltd レジスタ退避回復方法ならびに処理装置
JP2835103B2 (ja) * 1989-11-01 1998-12-14 富士通株式会社 命令指定方法及び命令実行方式
JPH05197545A (ja) 1991-12-10 1993-08-06 Mitsubishi Electric Corp マイクロコンピュータ
US5442576A (en) * 1994-05-26 1995-08-15 Motorola, Inc. Multibit shifting apparatus, data processor using same, and method therefor
JPH08161169A (ja) 1994-12-09 1996-06-21 Toshiba Corp Ｖｌｉｗ方式の計算機システム及びｖｌｉｗの解釈・実行方法
US5966514A (en) * 1995-05-31 1999-10-12 Matsushita Electric Industrial Co., Ltd. Microprocessor for supporting reduction of program codes in size
JPH0954693A (ja) 1995-08-11 1997-02-25 Toshiba Corp Ｖｌｉｗプロセッサ
JP3658072B2 (ja) * 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
US5890009A (en) * 1996-12-12 1999-03-30 International Business Machines Corporation VLIW architecture and method for expanding a parcel
JP3578883B2 (ja) * 1997-01-31 2004-10-20 三菱電機株式会社 データ処理装置

Also Published As

Publication number Publication date
IL124905A0 (en) 1999-01-26
CN1204089A (zh) 1999-01-06
TW393623B (en) 2000-06-11
KR19990007024A (ko) 1999-01-25
US6219779B1 (en) 2001-04-17
MY126508A (en) 2006-10-31
KR100618247B1 (ko) 2006-10-24
EP0897147A2 (en) 1999-02-17
CN1269052C (zh) 2006-08-09
EP0897147A3 (en) 2001-10-10
SG66480A1 (en) 1999-07-20

Similar Documents

Publication Publication Date Title
US6085306A (en) Processor for executing highly efficient VLIW
US5922066A (en) Multifunction data aligner in wide data width processor
US6490673B1 (en) Processor, compiling apparatus, and compile program recorded on a recording medium
JP2816248B2 (ja) データプロセッサ
US6219779B1 (en) Constant reconstructing processor which supports reductions in code size
KR100705507B1 (ko) 확장가능한 프로세서 아키텍처에 진보된 명령어들을부가하는 방법 및 장치
US20010021970A1 (en) Data processor
KR100254008B1 (ko) 2개의 명령을 동시에 실행할 수 있는 데이타 프로세서
EP1267257A2 (en) Conditional execution per data path slice
US6195740B1 (en) Constant reconstructing processor that execute an instruction using an operand divided between instructions
JP2004094959A (ja) 拡張ワード寸法及びアドレス空間を有する逆互換性コンピュータアーキテクチュア
US6209080B1 (en) Constant reconstruction processor that supports reductions in code size and processing time
JP3670801B2 (ja) プロセッサ
JP2004005733A (ja) Ｖｌｉｗプロセッサ
JP2000099329A (ja) プロセッサ

Legal Events

Date Code Title Description
KB Patent renewed
KB Patent renewed
KB Patent renewed
KB Patent renewed
EXP Patent expired